Date   

Re: [PATCH 4.19.y-cip 4/6] arm64: dts: renesas: r8a774e1: Add USB2.0 phy and host (EHCI/OHCI) device nodes

Pavel Machek
 

Hi!

--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1468,45 +1468,76 @@
};

ohci0: usb@ee080000 {
+ compatible = "generic-ohci";
Should this have more complete compatible listed, too, for the
unlikely case hardware problem is discovered?
Controller is compatible with the generic OHCI driver as of now there are no known hardware limitations. If in future if we come encounter any hardware issue we will add SoC specific platform string with the fix.

Hope this is OK with you.
Yes, OK with me, thanks.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH v2 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support

Pavel Machek
 

Hi!

This patch series adds SoC detection support for Renesas RZ/G1x SoC's.

All the patches apart from {7, 9, 11}/11 have been cherry picked from
Linux v5.10-rc6
Series looks good to me, I can apply it if there are no other
comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH v2 4.4.y-cip 03/11] soc: renesas: Identify SoC and register with the SoC bus

Pavel Machek
 

Hi!

From: Geert Uytterhoeven <geert+renesas@...>

commit 8d6799a9ba23acd675f3243580ee6f1756fb4381 upstream.

Identify the SoC type and revision, and register this information with
the SoC bus, so it is available under /sys/devices/soc0/, and can be
checked where needed using soc_device_match().

Identification is done using the Product Register or Common Chip Code
Register, as declared in DT (PRR only for now), or using a hardcoded
fallback if missing.
Just a minor nitpicks; no need to fix them for merge but maybe
consideration for mainline?

+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return -ENOMEM;
+
+ np = of_find_node_by_path("/");
+ of_property_read_string(np, "model", &soc_dev_attr->machine);
+ of_node_put(np);
+
+ soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
+ soc_dev_attr->soc_id = kstrdup_const(strchr(match->compatible, ',') + 1,
+ GFP_KERNEL);
+ if (chipid)
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
+ ((product >> 4) & 0x0f) + 1,
+ product & 0xf);
If memory allocations fail here, would it be better to fail the probe?

Would it be better to return error if !strchr(match->compatible, ',')
instead of trying to kstrdup_const((void *) 1) and oopsing?

+ pr_info("Detected Renesas %s %s %s\n", soc_dev_attr->family,
+ soc_dev_attr->soc_id, soc_dev_attr->revision ?: "");
Revision is NULL is handled here, but family may well be NULL, too, if
allocation failed. It is not going to cause problems here, but...

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


[PATCH v2 4.4.y-cip 11/11] ARM: dts: r8a77470: Add device node for PRR

Lad Prabhakar
 

Add a device node for the Product Register, which provides SoC product
and revision information.

PRR node is added as part of upstream commit 6929dfc591804 ("ARM: dts:
r8a77470: Initial SoC device tree") as this commit includes initial SoC
DTSI PRR node cannot be individually backported hence this new commit.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a77470.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 1057bff76cc8..3bf1a458593b 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -715,6 +715,11 @@
power-domains = <&cpg_clocks>;
};

+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a77470",
"renesas,cmt-48-gen2";
--
2.17.1


[PATCH v2 4.4.y-cip 10/11] soc: renesas: Identify RZ/G1C

Lad Prabhakar
 

From: Biju Das <biju.das@...>

commit 1daf13ba10378cad9ea4f5f26b83dd36c36dcdc0 upstream.

Add support for identifying the RZ/G1C (r8a77470) SoC.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
[PL: manually applied the changes, replaced fam_rzg1 to fam_rzg,
enabled SOC_BUS config for RZ/G1C]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/soc/renesas/renesas-soc.c | 8 ++++++++
2 files changed, 9 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 6812b3e19ba3..017d03d3e4e5 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -89,6 +89,7 @@ config ARCH_R8A7745
config ARCH_R8A77470
bool "RZ/G1C (R8A77470)"
select ARCH_RCAR_GEN2
+ select SOC_BUS

config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index eaa540bfc9bd..a267c7637003 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -55,6 +55,11 @@ static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
.id = 0x4c,
};

+static const struct renesas_soc soc_rz_g1c __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x53,
+};
+
static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A7742
{ .compatible = "renesas,r8a7742", .data = &soc_rz_g1h },
@@ -67,6 +72,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#endif
#ifdef CONFIG_ARCH_R8A7745
{ .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
+#endif
+#ifdef CONFIG_ARCH_R8A77470
+ { .compatible = "renesas,r8a77470", .data = &soc_rz_g1c },
#endif
{ /* sentinel */ }
};
--
2.17.1


[PATCH v2 4.4.y-cip 09/11] ARM: dts: r8a7742: Add device node for PRR

Lad Prabhakar
 

Add a device node for the Product Register, which provides SoC product
and revision information.

PRR node is added as part of upstream commit eb4cdda7a30b3 ("ARM: dts:
r8a7742: Initial SoC device tree") as this commit includes initial SoC
DTSI PRR node cannot be individually backported hence this new commit.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 0da46a2edddd..2ad6f965ccbd 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -1927,6 +1927,11 @@
renesas,#wpf = <4>;
};

+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7742",
"renesas,cmt-48-gen2";
--
2.17.1


[PATCH v2 4.4.y-cip 08/11] soc: renesas: Identify RZ/G1H

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 8848e1b14231a40ed66229fb3ee98519b32f2ae7 upstream.

Add support for identifying the RZ/G1H (r8a7742) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
[PL: manually applied the changes, enabled SOC_BUS config for RZ/G1N]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/soc/renesas/renesas-soc.c | 8 ++++++++
2 files changed, 9 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 8b84eb630dee..6812b3e19ba3 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -68,6 +68,7 @@ config ARCH_R8A7742
bool "RZ/G1H (R8A77420)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
+ select SOC_BUS

config ARCH_R8A7743
bool "RZ/G1M (R8A77430)"
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 2cf62855cc45..eaa540bfc9bd 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -35,6 +35,11 @@ struct renesas_soc {
u8 id;
};

+static const struct renesas_soc soc_rz_g1h __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x45,
+};
+
static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
.family = &fam_rzg,
.id = 0x47,
@@ -51,6 +56,9 @@ static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
};

static const struct of_device_id renesas_socs[] __initconst = {
+#ifdef CONFIG_ARCH_R8A7742
+ { .compatible = "renesas,r8a7742", .data = &soc_rz_g1h },
+#endif
#ifdef CONFIG_ARCH_R8A7743
{ .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
#endif
--
2.17.1


[PATCH v2 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR

Lad Prabhakar
 

Add a device node for the Product Register, which provides SoC product
and revision information.

PRR node is added as part of upstream commit d83010f87ab31 ("ARM: dts:
r8a7744: Initial SoC device tree") as this commit includes initial SoC
DTSI PRR node cannot be individually backported hence this new commit.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7744.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 079f46f17049..312c9aae8a10 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1526,6 +1526,11 @@
};
};

+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7744",
"renesas,cmt-48-gen2";
--
2.17.1


[PATCH v2 4.4.y-cip 06/11] soc: renesas: Identify RZ/G1N

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit cd59de80dd34dd2d1a3ca97d7a6e712c048b135a upstream.

Add support for identifying the RZ/G1N (r8a7744) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
[PL: Enabled SOC_BUS config for RZ/G1N]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/soc/renesas/renesas-soc.c | 8 ++++++++
2 files changed, 9 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3f1e27b76d59..8b84eb630dee 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -78,6 +78,7 @@ config ARCH_R8A7744
bool "RZ/G1N (R8A77440)"
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
+ select SOC_BUS

config ARCH_R8A7745
bool "RZ/G1E (R8A77450)"
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index e36b51a52dfc..2cf62855cc45 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -40,6 +40,11 @@ static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
.id = 0x47,
};

+static const struct renesas_soc soc_rz_g1n __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x4b,
+};
+
static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
.family = &fam_rzg,
.id = 0x4c,
@@ -49,6 +54,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A7743
{ .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
#endif
+#ifdef CONFIG_ARCH_R8A7744
+ { .compatible = "renesas,r8a7744", .data = &soc_rz_g1n },
+#endif
#ifdef CONFIG_ARCH_R8A7745
{ .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
#endif
--
2.17.1


[PATCH v2 4.4.y-cip 05/11] ARM: dts: r8a7745: Add device node for PRR

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 8916c7b58319fa27eae25c0c9b9a4cd68b9b30bd upstream.

Add a device node for the Product Register, which provides SoC product
and revision information.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
[PL: sorted the node as per address]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 5f603d9eafea..58bf2e52523e 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -1356,6 +1356,11 @@
};
};

+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7745",
"renesas,cmt-48-gen2";
--
2.17.1


[PATCH v2 4.4.y-cip 04/11] ARM: dts: r8a7743: Add device node for PRR

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 11d4407e939e74e89a29df88b1557b59ece9e9f9 upstream.

Add a device node for the Product Register, which provides SoC product
and revision information.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
[PL: sorted the node]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index aff5ebbdb4bd..73b8f7f341f4 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1781,6 +1781,11 @@
status = "disabled";
};

+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7743",
"renesas,cmt-48-gen2";
--
2.17.1


[PATCH v2 4.4.y-cip 03/11] soc: renesas: Identify SoC and register with the SoC bus

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 8d6799a9ba23acd675f3243580ee6f1756fb4381 upstream.

Identify the SoC type and revision, and register this information with
the SoC bus, so it is available under /sys/devices/soc0/, and can be
checked where needed using soc_device_match().

Identification is done using the Product Register or Common Chip Code
Register, as declared in DT (PRR only for now), or using a hardcoded
fallback if missing.

Example:

Detected Renesas R-Car Gen2 r8a7791 ES1.0
...
# cat /sys/devices/soc0/{machine,family,soc_id,revision}
Koelsch
R-Car Gen2
r8a7791
ES1.0

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
[PL: Dropped references to other platforms apart from RZ/G1{ME},
dropped SOC_BUS config option from arm64, enabled SOC_BUS config
option for ARCH_R8A7743 and ARCH_R8A7745]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/mach-shmobile/Kconfig | 2 +
drivers/soc/renesas/Makefile | 2 +
drivers/soc/renesas/renesas-soc.c | 123 ++++++++++++++++++++++++++++++
3 files changed, 127 insertions(+)
create mode 100644 drivers/soc/renesas/renesas-soc.c

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a51df53f0914..3f1e27b76d59 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -72,6 +72,7 @@ config ARCH_R8A7742
config ARCH_R8A7743
bool "RZ/G1M (R8A77430)"
select ARCH_RCAR_GEN2
+ select SOC_BUS

config ARCH_R8A7744
bool "RZ/G1N (R8A77440)"
@@ -81,6 +82,7 @@ config ARCH_R8A7744
config ARCH_R8A7745
bool "RZ/G1E (R8A77450)"
select ARCH_RCAR_GEN2
+ select SOC_BUS

config ARCH_R8A77470
bool "RZ/G1C (R8A77470)"
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 87517569af13..77e8f953f4c8 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -1 +1,3 @@
obj-$(CONFIG_ARCH_RCAR_GEN2) += rcar-rst.o
+
+obj-$(CONFIG_SOC_BUS) += renesas-soc.o
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
new file mode 100644
index 000000000000..e36b51a52dfc
--- /dev/null
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -0,0 +1,123 @@
+/*
+ * Renesas SoC Identification
+ *
+ * Copyright (C) 2014-2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+
+struct renesas_family {
+ const char name[16];
+ u32 reg; /* CCCR or PRR, if not in DT */
+};
+
+static const struct renesas_family fam_rzg __initconst __maybe_unused = {
+ .name = "RZ/G",
+ .reg = 0xff000044, /* PRR (Product Register) */
+};
+
+struct renesas_soc {
+ const struct renesas_family *family;
+ u8 id;
+};
+
+static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x47,
+};
+
+static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
+ .family = &fam_rzg,
+ .id = 0x4c,
+};
+
+static const struct of_device_id renesas_socs[] __initconst = {
+#ifdef CONFIG_ARCH_R8A7743
+ { .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
+#endif
+#ifdef CONFIG_ARCH_R8A7745
+ { .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
+#endif
+ { /* sentinel */ }
+};
+
+static int __init renesas_soc_init(void)
+{
+ struct soc_device_attribute *soc_dev_attr;
+ const struct renesas_family *family;
+ const struct of_device_id *match;
+ const struct renesas_soc *soc;
+ void __iomem *chipid = NULL;
+ struct soc_device *soc_dev;
+ struct device_node *np;
+ unsigned int product;
+
+ match = of_match_node(renesas_socs, of_root);
+ if (!match)
+ return -ENODEV;
+
+ soc = match->data;
+ family = soc->family;
+
+ /* Try PRR first, then hardcoded fallback */
+ np = of_find_compatible_node(NULL, NULL, "renesas,prr");
+ if (np) {
+ chipid = of_iomap(np, 0);
+ of_node_put(np);
+ } else if (soc->id) {
+ chipid = ioremap(family->reg, 4);
+ }
+ if (chipid) {
+ product = readl(chipid);
+ iounmap(chipid);
+ if (soc->id && ((product >> 8) & 0xff) != soc->id) {
+ pr_warn("SoC mismatch (product = 0x%x)\n", product);
+ return -ENODEV;
+ }
+ }
+
+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return -ENOMEM;
+
+ np = of_find_node_by_path("/");
+ of_property_read_string(np, "model", &soc_dev_attr->machine);
+ of_node_put(np);
+
+ soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
+ soc_dev_attr->soc_id = kstrdup_const(strchr(match->compatible, ',') + 1,
+ GFP_KERNEL);
+ if (chipid)
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
+ ((product >> 4) & 0x0f) + 1,
+ product & 0xf);
+
+ pr_info("Detected Renesas %s %s %s\n", soc_dev_attr->family,
+ soc_dev_attr->soc_id, soc_dev_attr->revision ?: "");
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR(soc_dev)) {
+ kfree(soc_dev_attr->revision);
+ kfree_const(soc_dev_attr->soc_id);
+ kfree_const(soc_dev_attr->family);
+ kfree(soc_dev_attr);
+ return PTR_ERR(soc_dev);
+ }
+
+ return 0;
+}
+core_initcall(renesas_soc_init);
--
2.17.1


[PATCH v2 4.4.y-cip 02/11] dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema

Lad Prabhakar
 

From: Simon Horman <horms+renesas@...>

commit 09f156d97e530c2ac631620f7b29508ff5cc4e6f upstream.

Convert Renesas Product Register bindings documentation to json-schema.

Signed-off-by: Simon Horman <horms+renesas@...>
Reviewed-by: Rob Herring <robh@...>
Link: https://lore.kernel.org/r/20190908120528.9392-1-horms+renesas@verge.net.au
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[PL: Initially in upstream commit 5384f45cd9714287f198771bfb057eda799af9a8
("ARM: shmobile: Document DT bindings for Product Register" added DT
documentation later this was moved into separate file (renesas,prr.txt) in
commit 74791d15fd7c405511e3cc097c2f043171ecbdb0 ("dt-bindings: arm:
renesas: Move 'renesas,prr' binding to its own doc") and finally this was
converted into json-schema so using the same commit to backport]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
.../devicetree/bindings/arm/renesas,prr.yaml | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.yaml

diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
new file mode 100644
index 000000000000..1f80767da38b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/renesas,prr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Product Register
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@...>
+ - Magnus Damm <magnus.damm@...>
+
+description: |
+ Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
+ Register that allows to retrieve SoC product and revision information.
+ If present, a device node for this register should be added.
+
+properties:
+ compatible:
+ enum:
+ - renesas,prr
+ - renesas,bsid
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0xff000044 4>;
+ };
--
2.17.1


[PATCH v2 4.4.y-cip 01/11] base: soc: Early register bus when needed

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 1da1b3628df34a2a5e38b70c8551770aadce969d upstream.

If soc_device_register() is called before soc_bus_register(), it crashes
with a NULL pointer dereference.

soc_bus_register() is already a core_initcall(), but drivers/base/ is
entered later than e.g. drivers/pinctrl/ and drivers/soc/. Hence there
are several subsystems that may need to know SoC revision information,
while it's not so easy to initialize the SoC bus even earlier using an
initcall.

To fix this, let soc_device_register() register the bus early if that
hasn't happened yet.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Acked-by: Arnd Bergmann <arnd@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/base/soc.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/base/soc.c b/drivers/base/soc.c
index 84242e6b2897..c9fd0ee2ba50 100644
--- a/drivers/base/soc.c
+++ b/drivers/base/soc.c
@@ -114,6 +114,12 @@ struct soc_device *soc_device_register(struct soc_device_attribute *soc_dev_attr
struct soc_device *soc_dev;
int ret;

+ if (!soc_bus_type.p) {
+ ret = bus_register(&soc_bus_type);
+ if (ret)
+ goto out1;
+ }
+
soc_dev = kzalloc(sizeof(*soc_dev), GFP_KERNEL);
if (!soc_dev) {
ret = -ENOMEM;
@@ -159,6 +165,9 @@ EXPORT_SYMBOL_GPL(soc_device_unregister);

static int __init soc_bus_register(void)
{
+ if (soc_bus_type.p)
+ return 0;
+
return bus_register(&soc_bus_type);
}
core_initcall(soc_bus_register);
--
2.17.1


[PATCH v2 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support

Lad Prabhakar
 

Hi All,

This patch series adds SoC detection support for Renesas RZ/G1x SoC's.

All the patches apart from {7, 9, 11}/11 have been cherry picked from
Linux v5.10-rc6

Cheers,
Prabhakar

Changes for v2:
* Added upstream commit-id for patches {7, 9, 11}/11

Biju Das (1):
soc: renesas: Identify RZ/G1C

Geert Uytterhoeven (6):
base: soc: Early register bus when needed
soc: renesas: Identify SoC and register with the SoC bus
ARM: dts: r8a7743: Add device node for PRR
ARM: dts: r8a7745: Add device node for PRR
soc: renesas: Identify RZ/G1N
soc: renesas: Identify RZ/G1H

Lad Prabhakar (3):
ARM: dts: r8a7744: Add device node for PRR
ARM: dts: r8a7742: Add device node for PRR
ARM: dts: r8a77470: Add device node for PRR

Simon Horman (1):
dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema

.../devicetree/bindings/arm/renesas,prr.yaml | 37 +++++
arch/arm/boot/dts/r8a7742.dtsi | 5 +
arch/arm/boot/dts/r8a7743.dtsi | 5 +
arch/arm/boot/dts/r8a7744.dtsi | 5 +
arch/arm/boot/dts/r8a7745.dtsi | 5 +
arch/arm/boot/dts/r8a77470.dtsi | 5 +
arch/arm/mach-shmobile/Kconfig | 5 +
drivers/base/soc.c | 9 ++
drivers/soc/renesas/Makefile | 2 +
drivers/soc/renesas/renesas-soc.c | 147 ++++++++++++++++++
10 files changed, 225 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.yaml
create mode 100644 drivers/soc/renesas/renesas-soc.c

--
2.17.1


Re: [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR

Lad Prabhakar
 

Hi Nobuhiro,

Thank you for the review.

-----Original Message-----
From: nobuhiro1.iwamatsu@... <nobuhiro1.iwamatsu@...>
Sent: 01 December 2020 00:52
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>; cip-dev@...;
pavel@...
Cc: Biju Das <biju.das.jz@...>
Subject: RE: [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR

Hi,

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@...]
Sent: Monday, November 30, 2020 11:19 PM
To: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@...>; Pavel Machek <pavel@...>
Cc: Biju Das <biju.das.jz@...>
Subject: [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR

Add a device node for the Product Register, which provides SoC product
and revision information.

Changes are already present in upstream but the PRR node is part of
initial SoC DTSI and cannot be individually backported hence this
new commit.
I thought it would be good to include the relevant commit ID.
For example, this should be included as 6929dfc5918049272e07653b1760b0b305f098e6,
but has been removed by 605e89568fafe57c1791219b411ab0771981beea.

If you accept this suggestion, please add the same comment to other similar patches.
Agreed I will update the commit message and repost.

Cheers,
Prabhakar

Best regards,
Nobuhiro


Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7744.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 079f46f17049..312c9aae8a10 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1526,6 +1526,11 @@
};
};

+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7744",
"renesas,cmt-48-gen2";
--
2.17.1


Re: [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@...]
Sent: Monday, November 30, 2020 11:19 PM
To: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@...>; Pavel Machek <pavel@...>
Cc: Biju Das <biju.das.jz@...>
Subject: [PATCH 4.4.y-cip 00/11] Renesas RZ/G1x add SoC detection support

Hi All,

This patch series adds SoC detection support for Renesas RZ/G1x SoC's.

All the patches apart from {7, 9, 11}/11 have been cherry picked from
Linux v5.10-rc6

Cheers,
Prabhakar

Biju Das (1):
soc: renesas: Identify RZ/G1C

Geert Uytterhoeven (6):
base: soc: Early register bus when needed
soc: renesas: Identify SoC and register with the SoC bus
ARM: dts: r8a7743: Add device node for PRR
ARM: dts: r8a7745: Add device node for PRR
soc: renesas: Identify RZ/G1N
soc: renesas: Identify RZ/G1H

Lad Prabhakar (3):
ARM: dts: r8a7744: Add device node for PRR
ARM: dts: r8a7742: Add device node for PRR
ARM: dts: r8a77470: Add device node for PRR

Simon Horman (1):
dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema

.../devicetree/bindings/arm/renesas,prr.yaml | 37 +++++
arch/arm/boot/dts/r8a7742.dtsi | 5 +
arch/arm/boot/dts/r8a7743.dtsi | 5 +
arch/arm/boot/dts/r8a7744.dtsi | 5 +
arch/arm/boot/dts/r8a7745.dtsi | 5 +
arch/arm/boot/dts/r8a77470.dtsi | 5 +
arch/arm/mach-shmobile/Kconfig | 5 +
drivers/base/soc.c | 9 ++
drivers/soc/renesas/Makefile | 2 +
drivers/soc/renesas/renesas-soc.c | 147 ++++++++++++++++++
10 files changed, 225 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.yaml
create mode 100644 drivers/soc/renesas/renesas-soc.c
I reviewed this patch series, there is not issue.
I can apply and push if there is no objection.

Best regards,
Nobuhiro


Re: [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@...]
Sent: Monday, November 30, 2020 11:19 PM
To: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@...>; Pavel Machek <pavel@...>
Cc: Biju Das <biju.das.jz@...>
Subject: [PATCH 4.4.y-cip 07/11] ARM: dts: r8a7744: Add device node for PRR

Add a device node for the Product Register, which provides SoC product
and revision information.

Changes are already present in upstream but the PRR node is part of
initial SoC DTSI and cannot be individually backported hence this
new commit.
I thought it would be good to include the relevant commit ID.
For example, this should be included as 6929dfc5918049272e07653b1760b0b305f098e6,
but has been removed by 605e89568fafe57c1791219b411ab0771981beea.

If you accept this suggestion, please add the same comment to other similar patches.

Best regards,
Nobuhiro


Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7744.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 079f46f17049..312c9aae8a10 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1526,6 +1526,11 @@
};
};

+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7744",
"renesas,cmt-48-gen2";
--
2.17.1


[isar-cip-core][PATCH 2/3] Update Isar revision

Jan Kiszka
 

From: Jan Kiszka <jan.kiszka@...>

Allows to drop one patch, needs explicit setting of DISTRO_APT_SOURCES.

Signed-off-by: Jan Kiszka <jan.kiszka@...>
---
conf/distro/cip-core-buster.conf | 2 +
conf/distro/cip-core-stretch.conf | 2 +
.../0001-u-boot-add-libubootenv.patch | 168 ------------------
kas-cip.yml | 5 +-
.../wic/plugins/source/efibootguard-boot.py | 2 +-
.../wic/plugins/source/efibootguard-efi.py | 2 +-
6 files changed, 7 insertions(+), 174 deletions(-)
delete mode 100644 isar-patches/0001-u-boot-add-libubootenv.patch

diff --git a/conf/distro/cip-core-buster.conf b/conf/distro/cip-core-buster.conf
index c5cb39c..ef60d24 100644
--- a/conf/distro/cip-core-buster.conf
+++ b/conf/distro/cip-core-buster.conf
@@ -12,5 +12,7 @@
require conf/distro/debian-buster.conf
require cip-core-common.inc

+DISTRO_APT_SOURCES = "conf/distro/debian-buster.list"
+
PREFERRED_VERSION_linux-cip ?= "4.19.%"
PREFERRED_VERSION_linux-cip-rt ?= "4.19.%"
diff --git a/conf/distro/cip-core-stretch.conf b/conf/distro/cip-core-stretch.conf
index 31900fa..ad185dd 100644
--- a/conf/distro/cip-core-stretch.conf
+++ b/conf/distro/cip-core-stretch.conf
@@ -12,5 +12,7 @@
require conf/distro/debian-stretch.conf
require cip-core-common.inc

+DISTRO_APT_SOURCES = "conf/distro/debian-stretch.list"
+
PREFERRED_VERSION_linux-cip ?= "4.19.%"
PREFERRED_VERSION_linux-cip-rt ?= "4.19.%"
diff --git a/isar-patches/0001-u-boot-add-libubootenv.patch b/isar-patches/0001-u-boot-add-libubootenv.patch
deleted file mode 100644
index 6002cf1..0000000
--- a/isar-patches/0001-u-boot-add-libubootenv.patch
+++ /dev/null
@@ -1,168 +0,0 @@
-From dda00e6addc7c51862b8175d473a1ea42dcd5c9e Mon Sep 17 00:00:00 2001
-From: Quirin Gylstorff <quirin.gylstorff@...>
-Date: Fri, 19 Jun 2020 17:00:36 +0200
-Subject: [PATCH v2] u-boot: add libubootenv
-
-Add the new library libubootenv and remove fw_printenv and fw_setenv
-form u-boot-tools as the are now part of the new library.
-
-libubootenv is a library that provides a hardware independent
-way to access to U-Boot environment. U-Boot has its default environment
-compiled board-dependently and this means that tools to access the environment
-are also board specific, too.
-
-libubootenv conflicts with u-boot-tools from Debian 10
-as both try to install fw_printenv and fw_sentenv. This conflict is not
-part of the control file as it breaks the installation of custom u-boot-tools
-from the u-boot-sources.
-
-This patch uses dpkg-gdb to build the package from salsa.debian.org and adds
-a fix for https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=967487.
-
-Signed-off-by: Quirin Gylstorff <quirin.gylstorff@...>
----
-
-Changes V2:
-- use dpkg-gbd instead dpkg
-- use salsa.debian.org as source
-- add fix for https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=967487
-
- meta-isar/conf/machine/de0-nano-soc.conf | 2 +-
- .../0002-Add-support-GNUInstallDirs.patch | 48 +++++++++++++++++++
- .../libubootenv/libubootenv_0.2.bb | 30 ++++++++++++
- .../files/debian/u-boot-tools.conffiles | 1 -
- .../u-boot/files/debian/u-boot-tools.install | 2 -
- .../u-boot/files/debian/u-boot-tools.links | 1 -
- 6 files changed, 79 insertions(+), 5 deletions(-)
- create mode 100644 meta/recipes-bsp/libubootenv/files/0002-Add-support-GNUInstallDirs.patch
- create mode 100644 meta/recipes-bsp/libubootenv/libubootenv_0.2.bb
- delete mode 100644 meta/recipes-bsp/u-boot/files/debian/u-boot-tools.conffiles
- delete mode 100644 meta/recipes-bsp/u-boot/files/debian/u-boot-tools.links
-
-diff --git a/meta-isar/conf/machine/de0-nano-soc.conf b/meta-isar/conf/machine/de0-nano-soc.conf
-index 3a2c009..6558d90 100644
---- a/meta-isar/conf/machine/de0-nano-soc.conf
-+++ b/meta-isar/conf/machine/de0-nano-soc.conf
-@@ -15,4 +15,4 @@ WKS_FILE ?= "de0-nano-soc.wks.in"
- IMAGER_INSTALL += "u-boot-de0-nano-soc"
- IMAGER_BUILD_DEPS += "u-boot-de0-nano-soc"
-
--IMAGE_INSTALL += "u-boot-tools u-boot-script"
-+IMAGE_INSTALL += "u-boot-tools libubootenv u-boot-script"
-diff --git a/meta/recipes-bsp/libubootenv/files/0002-Add-support-GNUInstallDirs.patch b/meta/recipes-bsp/libubootenv/files/0002-Add-support-GNUInstallDirs.patch
-new file mode 100644
-index 0000000..f8c3038
---- /dev/null
-+++ b/meta/recipes-bsp/libubootenv/files/0002-Add-support-GNUInstallDirs.patch
-@@ -0,0 +1,48 @@
-+From b17d194bd8285a19382a902a0bec9e5e042df064 Mon Sep 17 00:00:00 2001
-+From: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>
-+Date: Tue, 16 Apr 2019 08:52:01 +0900
-+Subject: [PATCH 2/4] Add support GNUInstallDirs
-+
-+This adds the functionality of the module "GNUInstallDirs" to make the
-+installation compatible with GNU.
-+
-+https://cmake.org/cmake/help/v3.14/module/GNUInstallDirs.html
-+
-+Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>
-+---
-+ CMakeLists.txt | 2 ++
-+ src/CMakeLists.txt | 8 ++++----
-+ 2 files changed, 6 insertions(+), 4 deletions(-)
-+
-+diff --git a/CMakeLists.txt b/CMakeLists.txt
-+index 104969e..57477fc 100644
-+--- a/CMakeLists.txt
-++++ b/CMakeLists.txt
-+@@ -10,6 +10,8 @@ add_definitions(-DVERSION="${VERSION}")
-+
-+ set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=gnu99")
-+
-++include("GNUInstallDirs")
-++
-+ #set(CMAKE_C_FLAGS_DEBUG "-g")
-+ include_directories ("${PROJECT_SOURCE_DIR}/src")
-+ add_subdirectory (src)
-+diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
-+index ea5979c..d97f221 100644
-+--- a/src/CMakeLists.txt
-++++ b/src/CMakeLists.txt
-+@@ -19,7 +19,7 @@ add_executable(fw_setenv fw_setenv.c)
-+ target_link_libraries(fw_printenv ubootenv z)
-+ target_link_libraries(fw_setenv ubootenv z)
-+
-+-install (TARGETS ubootenv DESTINATION lib)
-+-install (FILES libuboot.h DESTINATION include)
-+-install (TARGETS fw_printenv DESTINATION bin)
-+-install (TARGETS fw_setenv DESTINATION bin)
-++install (TARGETS ubootenv DESTINATION "${CMAKE_INSTALL_LIBDIR}")
-++install (FILES libuboot.h DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}")
-++install (TARGETS fw_printenv DESTINATION "${CMAKE_INSTALL_BINDIR}")
-++install (TARGETS fw_setenv DESTINATION "${CMAKE_INSTALL_BINDIR}")
-+--
-+2.20.1
-+
-diff --git a/meta/recipes-bsp/libubootenv/libubootenv_0.2.bb b/meta/recipes-bsp/libubootenv/libubootenv_0.2.bb
-new file mode 100644
-index 0000000..995e581
---- /dev/null
-+++ b/meta/recipes-bsp/libubootenv/libubootenv_0.2.bb
-@@ -0,0 +1,30 @@
-+# libubootenv
-+#
-+# This software is a part of ISAR.
-+# Copyright (c) Siemens AG, 2020
-+#
-+# SPDX-License-Identifier: MIT
-+
-+DESCRIPTION = "swupdate utility for software updates"
-+HOMEPAGE= "https://github.com/sbabic/swupdate"
-+LICENSE = "GPL-2.0"
-+LIC_FILES_CHKSUM = "file://${LAYERDIR_isar}/licenses/COPYING.GPLv2;md5=751419260aa954499f7abaabaa882bbe"
-+
-+inherit dpkg-gbp
-+
-+SRC_URI = "git://salsa.debian.org/debian/libubootenv.git;protocol=https \
-+ file://0002-Add-support-GNUInstallDirs.patch;apply=no "
-+SRCREV = "2c7cb6d941d906dcc1d2e447cc17e418485dff12"
-+
-+S = "${WORKDIR}/git"
-+
-+do_prepare_build() {
-+ cd ${S}
-+ export QUILT_PATCHES=debian/patches
-+ quilt import -f ${WORKDIR}/*.patch
-+ quilt push -a
-+}
-+
-+dpkg_runbuild_prepend() {
-+ export DEB_BUILD_OPTIONS="nocheck"
-+}
-diff --git a/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.conffiles b/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.conffiles
-deleted file mode 100644
-index d49a8fb..0000000
---- a/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.conffiles
-+++ /dev/null
-@@ -1 +0,0 @@
--/etc/fw_env.config
-diff --git a/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.install b/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.install
-index d1ae3e0..2893b9a 100644
---- a/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.install
-+++ b/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.install
-@@ -1,5 +1,3 @@
- tools/dumpimage /usr/bin/
--tools/env/fw_printenv /usr/bin/
- tools/mkenvimage /usr/bin/
- tools/mkimage /usr/bin/
--tools/env/fw_env.config /etc
-diff --git a/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.links b/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.links
-deleted file mode 100644
-index 92f5a6c..0000000
---- a/meta/recipes-bsp/u-boot/files/debian/u-boot-tools.links
-+++ /dev/null
-@@ -1 +0,0 @@
--/usr/bin/fw_printenv /usr/bin/fw_setenv
---
-2.20.1
-
diff --git a/kas-cip.yml b/kas-cip.yml
index 66a58f1..922ee7e 100644
--- a/kas-cip.yml
+++ b/kas-cip.yml
@@ -20,13 +20,10 @@ repos:

isar:
url: https://github.com/ilbers/isar.git
- refspec: 351af175bc54a201c6f44307d4e998bd6c0afdb8
+ refspec: 76eac233f1b1d0d117b3f05b3dec8a6da1cdf4c7
layers:
meta:
patches:
- 01-libubootenv:
- path: isar-patches/0001-u-boot-add-libubootenv.patch
- repo: cip-core
02-initramfs:
path: isar-patches/v7-0001-meta-support-Generate-a-custom-initramfs.patch
repo: cip-core
diff --git a/scripts/lib/wic/plugins/source/efibootguard-boot.py b/scripts/lib/wic/plugins/source/efibootguard-boot.py
index d291f75..b85cfca 100644
--- a/scripts/lib/wic/plugins/source/efibootguard-boot.py
+++ b/scripts/lib/wic/plugins/source/efibootguard-boot.py
@@ -35,7 +35,7 @@ import logging
msger = logging.getLogger('wic')

from wic.pluginbase import SourcePlugin
-from wic.utils.misc import exec_cmd, get_bitbake_var, BOOTDD_EXTRA_SPACE
+from wic.misc import exec_cmd, get_bitbake_var, BOOTDD_EXTRA_SPACE

class EfibootguardBootPlugin(SourcePlugin):
"""
diff --git a/scripts/lib/wic/plugins/source/efibootguard-efi.py b/scripts/lib/wic/plugins/source/efibootguard-efi.py
index 6647212..9eb2353 100644
--- a/scripts/lib/wic/plugins/source/efibootguard-efi.py
+++ b/scripts/lib/wic/plugins/source/efibootguard-efi.py
@@ -33,7 +33,7 @@ import os
msger = logging.getLogger('wic')

from wic.pluginbase import SourcePlugin
-from wic.utils.misc import exec_cmd, get_bitbake_var, BOOTDD_EXTRA_SPACE
+from wic.misc import exec_cmd, get_bitbake_var, BOOTDD_EXTRA_SPACE

class EfibootguardEFIPlugin(SourcePlugin):
"""
--
2.26.2


[isar-cip-core][PATCH 1/3] README: Add some community resources

Jan Kiszka
 

From: Jan Kiszka <jan.kiszka@...>

Signed-off-by: Jan Kiszka <jan.kiszka@...>
---
README.md | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 4f74af7..0d2374f 100644
--- a/README.md
+++ b/README.md
@@ -48,8 +48,23 @@ Run the generated securiy images on QEMU (x86-64bit)

## Community Resources

-TBD
+Mailing list:

+ - cip-dev@...
+
+ - Subscription:
+ - cip-dev+subscribe@...
+ - https://lists.cip-project.org/g/cip-dev
+
+ - Archives:
+ - https://lore.kernel.org/cip-dev/
+ - https://lists.cip-project.org/g/cip-dev
+
+Continuous integration:
+
+ - https://gitlab.com/cip-project/cip-core/isar-cip-core/-/pipelines
+
+
## License

Unless otherwise stated in the respective file, files in this layer are
--
2.26.2

2701 - 2720 of 8627