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[PATCH v2 5.10.y-cip 08/12] watchdog: rzg2l_wdt: Fix 'BUG: Invalid wait context'

Biju Das
 

commit e4cf89596c1f1e33309556699f910ced4abbaf44 upstream.

This patch fixes the issue 'BUG: Invalid wait context' during restart()
callback by using clk_prepare_enable() instead of pm_runtime_get_sync()
for turning on the clocks during restart.

This issue is noticed when testing with renesas_defconfig.

[ 42.213802] reboot: Restarting system
[ 42.217860]
[ 42.219364] =============================
[ 42.223368] [ BUG: Invalid wait context ]
[ 42.227372] 5.17.0-rc5-arm64-renesas-00002-g10393723e35e #522 Not tainted
[ 42.234153] -----------------------------
[ 42.238155] systemd-shutdow/1 is trying to lock:
[ 42.242766] ffff00000a650828 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x14/0x20
[ 42.250709] other info that might help us debug this:
[ 42.255753] context-{4:4}
[ 42.258368] 2 locks held by systemd-shutdow/1:
[ 42.262806] #0: ffff80000944e1c8 (system_transition_mutex#2){+.+.}-{3:3}, at: __do_sys_reboot+0xd0/0x250
[ 42.272388] #1: ffff8000094c4e40 (rcu_read_lock){....}-{1:2}, at: atomic_notifier_call_chain+0x0/0x150
[ 42.281795] stack backtrace:
[ 42.284672] CPU: 0 PID: 1 Comm: systemd-shutdow Not tainted 5.17.0-rc5-arm64-renesas-00002-g10393723e35e #522
[ 42.294577] Hardware name: Renesas SMARC EVK based on r9a07g044c2 (DT)
[ 42.301096] Call trace:
[ 42.303538] dump_backtrace+0xcc/0xd8
[ 42.307203] show_stack+0x14/0x30
[ 42.310517] dump_stack_lvl+0x88/0xb0
[ 42.314180] dump_stack+0x14/0x2c
[ 42.317492] __lock_acquire+0x1b24/0x1b50
[ 42.321502] lock_acquire+0x120/0x3a8
[ 42.325162] __mutex_lock+0x84/0x8f8
[ 42.328737] mutex_lock_nested+0x30/0x58
[ 42.332658] genpd_lock_mtx+0x14/0x20
[ 42.336319] genpd_runtime_resume+0xc4/0x228
[ 42.340587] __rpm_callback+0x44/0x170
[ 42.344337] rpm_callback+0x64/0x70
[ 42.347824] rpm_resume+0x4e0/0x6b8
[ 42.351310] __pm_runtime_resume+0x50/0x78
[ 42.355404] rzg2l_wdt_restart+0x28/0x68
[ 42.359329] watchdog_restart_notifier+0x1c/0x30
[ 42.363943] atomic_notifier_call_chain+0x94/0x150
[ 42.368732] do_kernel_restart+0x24/0x30
[ 42.372652] machine_restart+0x44/0x70
[ 42.376399] kernel_restart+0x3c/0x60
[ 42.380058] __do_sys_reboot+0x228/0x250
[ 42.383977] __arm64_sys_reboot+0x20/0x28
[ 42.387983] invoke_syscall+0x40/0xf8

Fixes: 2cbc5cd0b55fa2 ("watchdog: Add Watchdog Timer driver for RZ/G2L")
Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Guenter Roeck <linux@...>
Link: https://lore.kernel.org/r/20220225175320.11041-4-biju.das.jz@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/watchdog/rzg2l_wdt.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c
index 0fc73b8a9567..48dfe6e5e64f 100644
--- a/drivers/watchdog/rzg2l_wdt.c
+++ b/drivers/watchdog/rzg2l_wdt.c
@@ -43,6 +43,8 @@ struct rzg2l_wdt_priv {
struct reset_control *rstc;
unsigned long osc_clk_rate;
unsigned long delay;
+ struct clk *pclk;
+ struct clk *osc_clk;
};

static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
@@ -118,7 +120,9 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev,

/* Reset the module before we modify any register */
reset_control_reset(priv->rstc);
- pm_runtime_get_sync(wdev->parent);
+
+ clk_prepare_enable(priv->pclk);
+ clk_prepare_enable(priv->osc_clk);

/* smallest counter value to reboot soon */
rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(1), WDTSET);
@@ -165,7 +169,6 @@ static int rzg2l_wdt_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct rzg2l_wdt_priv *priv;
unsigned long pclk_rate;
- struct clk *wdt_clk;
int ret;

priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -177,22 +180,20 @@ static int rzg2l_wdt_probe(struct platform_device *pdev)
return PTR_ERR(priv->base);

/* Get watchdog main clock */
- wdt_clk = clk_get(&pdev->dev, "oscclk");
- if (IS_ERR(wdt_clk))
- return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no oscclk");
+ priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk");
+ if (IS_ERR(priv->osc_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk");

- priv->osc_clk_rate = clk_get_rate(wdt_clk);
- clk_put(wdt_clk);
+ priv->osc_clk_rate = clk_get_rate(priv->osc_clk);
if (!priv->osc_clk_rate)
return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");

/* Get Peripheral clock */
- wdt_clk = clk_get(&pdev->dev, "pclk");
- if (IS_ERR(wdt_clk))
- return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no pclk");
+ priv->pclk = devm_clk_get(&pdev->dev, "pclk");
+ if (IS_ERR(priv->pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");

- pclk_rate = clk_get_rate(wdt_clk);
- clk_put(wdt_clk);
+ pclk_rate = clk_get_rate(priv->pclk);
if (!pclk_rate)
return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");

--
2.25.1


[PATCH v2 5.10.y-cip 07/12] watchdog: rzg2l_wdt: Fix Runtime PM usage

Biju Das
 

commit 95abafe76297fa057de6c3486ef844bd446bdf18 upstream.

Both rzg2l_wdt_probe() and rzg2l_wdt_start() calls pm_runtime_get() which
results in a usage counter imbalance. This patch fixes this issue by
removing pm_runtime_get() call from probe.

Fixes: 2cbc5cd0b55fa2 ("watchdog: Add Watchdog Timer driver for RZ/G2L")
Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Guenter Roeck <linux@...>
Link: https://lore.kernel.org/r/20220225175320.11041-3-biju.das.jz@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/watchdog/rzg2l_wdt.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)

diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c
index 96f2a018ab62..0fc73b8a9567 100644
--- a/drivers/watchdog/rzg2l_wdt.c
+++ b/drivers/watchdog/rzg2l_wdt.c
@@ -151,12 +151,11 @@ static const struct watchdog_ops rzg2l_wdt_ops = {
.restart = rzg2l_wdt_restart,
};

-static void rzg2l_wdt_reset_assert_pm_disable_put(void *data)
+static void rzg2l_wdt_reset_assert_pm_disable(void *data)
{
struct watchdog_device *wdev = data;
struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);

- pm_runtime_put(wdev->parent);
pm_runtime_disable(wdev->parent);
reset_control_assert(priv->rstc);
}
@@ -206,11 +205,6 @@ static int rzg2l_wdt_probe(struct platform_device *pdev)

reset_control_deassert(priv->rstc);
pm_runtime_enable(&pdev->dev);
- ret = pm_runtime_resume_and_get(&pdev->dev);
- if (ret < 0) {
- dev_err(dev, "pm_runtime_resume_and_get failed ret=%pe", ERR_PTR(ret));
- goto out_pm_get;
- }

priv->wdev.info = &rzg2l_wdt_ident;
priv->wdev.ops = &rzg2l_wdt_ops;
@@ -222,7 +216,7 @@ static int rzg2l_wdt_probe(struct platform_device *pdev)

watchdog_set_drvdata(&priv->wdev, priv);
ret = devm_add_action_or_reset(&pdev->dev,
- rzg2l_wdt_reset_assert_pm_disable_put,
+ rzg2l_wdt_reset_assert_pm_disable,
&priv->wdev);
if (ret < 0)
return ret;
@@ -235,12 +229,6 @@ static int rzg2l_wdt_probe(struct platform_device *pdev)
dev_warn(dev, "Specified timeout invalid, using default");

return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
-
-out_pm_get:
- pm_runtime_disable(dev);
- reset_control_assert(priv->rstc);
-
- return ret;
}

static const struct of_device_id rzg2l_wdt_ids[] = {
--
2.25.1


[PATCH v2 5.10.y-cip 06/12] watchdog: rzg2l_wdt: Fix 32bit overflow issue

Biju Das
 

commit ea2949df22a533cdf75e4583c00b1ce94cd5a83b upstream.

The value of timer_cycle_us can be 0 due to 32bit overflow.
For eg:- If we assign the counter value "0xfff" for computing
maxval.

This patch fixes this issue by appending ULL to 1024, so that
it is promoted to 64bit.

This patch also fixes the warning message, 'watchdog: Invalid min and
max timeout values, resetting to 0!'.

Fixes: 2cbc5cd0b55fa2 ("watchdog: Add Watchdog Timer driver for RZ/G2L")
Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Guenter Roeck <linux@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/20220225175320.11041-2-biju.das.jz@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/watchdog/rzg2l_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c
index 6b426df34fd6..96f2a018ab62 100644
--- a/drivers/watchdog/rzg2l_wdt.c
+++ b/drivers/watchdog/rzg2l_wdt.c
@@ -53,7 +53,7 @@ static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)

static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime)
{
- u64 timer_cycle_us = 1024 * 1024 * (wdttime + 1) * MICRO;
+ u64 timer_cycle_us = 1024 * 1024ULL * (wdttime + 1) * MICRO;

return div64_ul(timer_cycle_us, cycle);
}
--
2.25.1


[PATCH v2 5.10.y-cip 05/12] arm64: defconfig: Enable additional support for Renesas platforms

Biju Das
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 2e8a3335472461927e57d1741ccf1791ff416075 upstream.

Increase build and test coverage by enabling support for more hardware
present on Renesas SoCs and boards:
- Renesas RSPI, RZ/G2L thermal, RZ/G2L WDT watchdog, and OSTM timer,
as used on the RZ/G2L SMARC EVK board,
- R-Car Image Signal Processor (ISP) and Display Unit embedded MIPI
DSI encoder on R-Car V3U, as used on the Falcon board.

All of the above are modular, except for thermal, watchdog, and timer.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/c9800d67f91a90d418a3ce44c59109ae0a87b2d8.1643373223.git.geert+renesas@glider.be
Signed-off-by: Biju Das <biju.das.jz@...>
[biju: Removed R-Car V3U configs]
---
arch/arm64/configs/defconfig | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7575dbd6f57c..58a79a3e1cd0 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -465,6 +465,7 @@ CONFIG_SPI_ORION=y
CONFIG_SPI_PL022=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_RPCIF=m
+CONFIG_SPI_RSPI=m
CONFIG_SPI_QCOM_QSPI=m
CONFIG_SPI_QUP=y
CONFIG_SPI_QCOM_GENI=m
@@ -540,6 +541,7 @@ CONFIG_IMX8MM_THERMAL=m
CONFIG_ROCKCHIP_THERMAL=m
CONFIG_RCAR_THERMAL=y
CONFIG_RCAR_GEN3_THERMAL=y
+CONFIG_RZG2L_THERMAL=y
CONFIG_ARMADA_THERMAL=y
CONFIG_BCM2711_THERMAL=m
CONFIG_BCM2835_THERMAL=m
@@ -563,6 +565,7 @@ CONFIG_QCOM_WDT=m
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
CONFIG_RENESAS_WDT=y
+CONFIG_RENESAS_RZG2LWDT=y
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_BCM2835_WDT=y
CONFIG_MFD_ALTERA_SYSMGR=y
@@ -909,6 +912,7 @@ CONFIG_SM_GPUCC_8250=y
CONFIG_QCOM_HFPLL=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_RENESAS_OSTM=y
CONFIG_ARM_MHU=y
CONFIG_IMX_MBOX=y
CONFIG_PLATFORM_MHU=y
--
2.25.1


[PATCH v2 5.10.y-cip 04/12] thermal/drivers/rz2gl: Fix OTP Calibration Register values

Biju Das
 

commit 2d37f5c90bdc659b329dac7cf6d165a4bbf34cb6 upstream.

As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the bit 31 of TSU OTP Calibration Register(OTPTSUTRIM) indicates
whether bit [11:0] of OTPTSUTRIM is valid or invalid.

This patch updates the code to reflect this change.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/20220428093346.7552-1-biju.das.jz@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/thermal/rzg2l_thermal.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/rzg2l_thermal.c b/drivers/thermal/rzg2l_thermal.c
index a4c22123ad81..3e0e2e4fe27d 100644
--- a/drivers/thermal/rzg2l_thermal.c
+++ b/drivers/thermal/rzg2l_thermal.c
@@ -32,6 +32,8 @@
#define TSU_SS 0x10

#define OTPTSUTRIM_REG(n) (0x18 + ((n) * 0x4))
+#define OTPTSUTRIM_EN_MASK BIT(31)
+#define OTPTSUTRIM_MASK GENMASK(11, 0)

/* Sensor Mode Register(TSU_SM) */
#define TSU_SM_EN_TS BIT(0)
@@ -183,11 +185,15 @@ static int rzg2l_thermal_probe(struct platform_device *pdev)
pm_runtime_get_sync(dev);

priv->calib0 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0));
- if (!priv->calib0)
+ if (priv->calib0 & OTPTSUTRIM_EN_MASK)
+ priv->calib0 &= OTPTSUTRIM_MASK;
+ else
priv->calib0 = SW_CALIB0_VAL;

priv->calib1 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(1));
- if (!priv->calib1)
+ if (priv->calib1 & OTPTSUTRIM_EN_MASK)
+ priv->calib1 &= OTPTSUTRIM_MASK;
+ else
priv->calib1 = SW_CALIB1_VAL;

platform_set_drvdata(pdev, priv);
--
2.25.1


[PATCH v2 5.10.y-cip 03/12] thermal/drivers/rz2gl: Add error check for reset_control_deassert()

Biju Das
 

commit 8ee1c0f6526ce942b7595951c7bb0165010051c2 upstream.

If reset_control_deassert() fails, then we won't be able to access
the device registers. Therefore check the return code of
reset_control_deassert() and bail out in case of error.

While at it replace the parameter "&pdev->dev" -> "dev" in
devm_reset_control_get_exclusive().

Suggested-by: Philipp Zabel <p.zabel@...>
Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Philipp Zabel <p.zabel@...>
Link: https://lore.kernel.org/r/20211208164010.4130-1-biju.das.jz@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/thermal/rzg2l_thermal.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/rzg2l_thermal.c b/drivers/thermal/rzg2l_thermal.c
index 19062739e213..a4c22123ad81 100644
--- a/drivers/thermal/rzg2l_thermal.c
+++ b/drivers/thermal/rzg2l_thermal.c
@@ -170,12 +170,14 @@ static int rzg2l_thermal_probe(struct platform_device *pdev)
return PTR_ERR(priv->base);

priv->dev = dev;
- priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ priv->rstc = devm_reset_control_get_exclusive(dev, NULL);
if (IS_ERR(priv->rstc))
return dev_err_probe(dev, PTR_ERR(priv->rstc),
"failed to get cpg reset");

- reset_control_deassert(priv->rstc);
+ ret = reset_control_deassert(priv->rstc);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to deassert");

pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
--
2.25.1


[PATCH v2 5.10.y-cip 02/12] thermal/drivers: Add TSU driver for RZ/G2L

Biju Das
 

commit 673c68bd48390dad01f7d17670de3e33b60860ac upstream.

The RZ/G2L SoC incorporates a thermal sensor unit (TSU) that measures the
temperature inside the LSI.

The thermal sensor in this unit measures temperatures in the range from
−40 degree Celsius to 125 degree Celsius with an accuracy of ±3°C. The
TSU repeats measurement at 20 microseconds intervals and automatically
updates the results of measurement.

The TSU has no interrupts as well as no external pins.

This patch adds Thermal Sensor Unit(TSU) driver for RZ/G2L SoC.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211130155757.17837-3-biju.das.jz@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@...>
[biju: Replaced math.h->kernel.h]
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/thermal/Kconfig | 9 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/rzg2l_thermal.c | 240 ++++++++++++++++++++++++++++++++
3 files changed, 250 insertions(+)
create mode 100644 drivers/thermal/rzg2l_thermal.c

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 7edc8dc6bbab..e51c8cc989d8 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -354,6 +354,15 @@ config RCAR_GEN3_THERMAL
Enable this to plug the R-Car Gen3 or RZ/G2 thermal sensor driver into
the Linux thermal framework.

+config RZG2L_THERMAL
+ tristate "Renesas RZ/G2L thermal driver"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on HAS_IOMEM
+ depends on OF
+ help
+ Enable this to plug the RZ/G2L thermal sensor driver into the Linux
+ thermal framework.
+
config KIRKWOOD_THERMAL
tristate "Temperature sensor on Marvell Kirkwood SoCs"
depends on MACH_KIRKWOOD || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index b64dd50a6629..b71f9b88b567 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_SUN8I_THERMAL) += sun8i_thermal.o
obj-$(CONFIG_ROCKCHIP_THERMAL) += rockchip_thermal.o
obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o
obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o
+obj-$(CONFIG_RZG2L_THERMAL) += rzg2l_thermal.o
obj-$(CONFIG_KIRKWOOD_THERMAL) += kirkwood_thermal.o
obj-y += samsung/
obj-$(CONFIG_DOVE_THERMAL) += dove_thermal.o
diff --git a/drivers/thermal/rzg2l_thermal.c b/drivers/thermal/rzg2l_thermal.c
new file mode 100644
index 000000000000..19062739e213
--- /dev/null
+++ b/drivers/thermal/rzg2l_thermal.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L TSU Thermal Sensor Driver
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+#include <linux/units.h>
+
+#include "thermal_hwmon.h"
+
+#define CTEMP_MASK 0xFFF
+
+/* default calibration values, if FUSE values are missing */
+#define SW_CALIB0_VAL 3148
+#define SW_CALIB1_VAL 503
+
+/* Register offsets */
+#define TSU_SM 0x00
+#define TSU_ST 0x04
+#define TSU_SAD 0x0C
+#define TSU_SS 0x10
+
+#define OTPTSUTRIM_REG(n) (0x18 + ((n) * 0x4))
+
+/* Sensor Mode Register(TSU_SM) */
+#define TSU_SM_EN_TS BIT(0)
+#define TSU_SM_ADC_EN_TS BIT(1)
+#define TSU_SM_NORMAL_MODE (TSU_SM_EN_TS | TSU_SM_ADC_EN_TS)
+
+/* TSU_ST bits */
+#define TSU_ST_START BIT(0)
+
+#define TSU_SS_CONV_RUNNING BIT(0)
+
+#define TS_CODE_AVE_SCALE(x) ((x) * 1000000)
+#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE)
+#define TS_CODE_CAP_TIMES 8 /* Capture times */
+
+#define RZG2L_THERMAL_GRAN 500 /* milli Celsius */
+#define RZG2L_TSU_SS_TIMEOUT_US 1000
+
+#define CURVATURE_CORRECTION_CONST 13
+
+struct rzg2l_thermal_priv {
+ struct device *dev;
+ void __iomem *base;
+ struct thermal_zone_device *zone;
+ struct reset_control *rstc;
+ u32 calib0, calib1;
+};
+
+static inline u32 rzg2l_thermal_read(struct rzg2l_thermal_priv *priv, u32 reg)
+{
+ return ioread32(priv->base + reg);
+}
+
+static inline void rzg2l_thermal_write(struct rzg2l_thermal_priv *priv, u32 reg,
+ u32 data)
+{
+ iowrite32(data, priv->base + reg);
+}
+
+static int rzg2l_thermal_get_temp(void *devdata, int *temp)
+{
+ struct rzg2l_thermal_priv *priv = devdata;
+ u32 result = 0, dsensor, ts_code_ave;
+ int val, i;
+
+ for (i = 0; i < TS_CODE_CAP_TIMES ; i++) {
+ /* TSU repeats measurement at 20 microseconds intervals and
+ * automatically updates the results of measurement. As per
+ * the HW manual for measuring temperature we need to read 8
+ * values consecutively and then take the average.
+ * ts_code_ave = (ts_code[0] + ⋯ + ts_code[7]) / 8
+ */
+ result += rzg2l_thermal_read(priv, TSU_SAD) & CTEMP_MASK;
+ usleep_range(20, 30);
+ }
+
+ ts_code_ave = result / TS_CODE_CAP_TIMES;
+
+ /* Calculate actual sensor value by applying curvature correction formula
+ * dsensor = ts_code_ave / (1 + ts_code_ave * 0.000013). Here we are doing
+ * integer calculation by scaling all the values by 1000000.
+ */
+ dsensor = TS_CODE_AVE_SCALE(ts_code_ave) /
+ (TS_CODE_AVE_SCALE(1) + (ts_code_ave * CURVATURE_CORRECTION_CONST));
+
+ /* The temperature Tj is calculated by the formula
+ * Tj = (dsensor − calib1) * 165/ (calib0 − calib1) − 40
+ * where calib0 and calib1 are the caliberation values.
+ */
+ val = ((dsensor - priv->calib1) * (MCELSIUS(165) /
+ (priv->calib0 - priv->calib1))) - MCELSIUS(40);
+
+ *temp = roundup(val, RZG2L_THERMAL_GRAN);
+
+ return 0;
+}
+
+static const struct thermal_zone_of_device_ops rzg2l_tz_of_ops = {
+ .get_temp = rzg2l_thermal_get_temp,
+};
+
+static int rzg2l_thermal_init(struct rzg2l_thermal_priv *priv)
+{
+ u32 reg_val;
+
+ rzg2l_thermal_write(priv, TSU_SM, TSU_SM_NORMAL_MODE);
+ rzg2l_thermal_write(priv, TSU_ST, 0);
+
+ /* Before setting the START bit, TSU should be in normal operating
+ * mode. As per the HW manual, it will take 60 µs to place the TSU
+ * into normal operating mode.
+ */
+ usleep_range(60, 80);
+
+ reg_val = rzg2l_thermal_read(priv, TSU_ST);
+ reg_val |= TSU_ST_START;
+ rzg2l_thermal_write(priv, TSU_ST, reg_val);
+
+ return readl_poll_timeout(priv->base + TSU_SS, reg_val,
+ reg_val == TSU_SS_CONV_RUNNING, 50,
+ RZG2L_TSU_SS_TIMEOUT_US);
+}
+
+static void rzg2l_thermal_reset_assert_pm_disable_put(struct platform_device *pdev)
+{
+ struct rzg2l_thermal_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ pm_runtime_put(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ reset_control_assert(priv->rstc);
+}
+
+static int rzg2l_thermal_remove(struct platform_device *pdev)
+{
+ struct rzg2l_thermal_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ thermal_remove_hwmon_sysfs(priv->zone);
+ rzg2l_thermal_reset_assert_pm_disable_put(pdev);
+
+ return 0;
+}
+
+static int rzg2l_thermal_probe(struct platform_device *pdev)
+{
+ struct thermal_zone_device *zone;
+ struct rzg2l_thermal_priv *priv;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->dev = dev;
+ priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(priv->rstc))
+ return dev_err_probe(dev, PTR_ERR(priv->rstc),
+ "failed to get cpg reset");
+
+ reset_control_deassert(priv->rstc);
+
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
+ priv->calib0 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0));
+ if (!priv->calib0)
+ priv->calib0 = SW_CALIB0_VAL;
+
+ priv->calib1 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(1));
+ if (!priv->calib1)
+ priv->calib1 = SW_CALIB1_VAL;
+
+ platform_set_drvdata(pdev, priv);
+ ret = rzg2l_thermal_init(priv);
+ if (ret) {
+ dev_err(dev, "Failed to start TSU");
+ goto err;
+ }
+
+ zone = devm_thermal_zone_of_sensor_register(dev, 0, priv,
+ &rzg2l_tz_of_ops);
+ if (IS_ERR(zone)) {
+ dev_err(dev, "Can't register thermal zone");
+ ret = PTR_ERR(zone);
+ goto err;
+ }
+
+ priv->zone = zone;
+ priv->zone->tzp->no_hwmon = false;
+ ret = thermal_add_hwmon_sysfs(priv->zone);
+ if (ret)
+ goto err;
+
+ dev_dbg(dev, "TSU probed with %s caliberation values",
+ rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0)) ? "hw" : "sw");
+
+ return 0;
+
+err:
+ rzg2l_thermal_reset_assert_pm_disable_put(pdev);
+ return ret;
+}
+
+static const struct of_device_id rzg2l_thermal_dt_ids[] = {
+ { .compatible = "renesas,rzg2l-tsu", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_thermal_dt_ids);
+
+static struct platform_driver rzg2l_thermal_driver = {
+ .driver = {
+ .name = "rzg2l_thermal",
+ .of_match_table = rzg2l_thermal_dt_ids,
+ },
+ .probe = rzg2l_thermal_probe,
+ .remove = rzg2l_thermal_remove,
+};
+module_platform_driver(rzg2l_thermal_driver);
+
+MODULE_DESCRIPTION("Renesas RZ/G2L TSU Thermal Sensor Driver");
+MODULE_AUTHOR("Biju Das <biju.das.jz@...>");
+MODULE_LICENSE("GPL v2");
--
2.25.1


[PATCH v2 5.10.y-cip 01/12] units: Add SI metric prefix definitions

Biju Das
 

From: Andy Shevchenko <andriy.shevchenko@...>

commit 26471d4a6cf8d5d0bd0fb55c7169de7d67cc703a upstream.

Sometimes it's useful to have well-defined SI metric prefix to be used
to self-describe the formulas or equations.

List most popular ones in the units.h.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@...>
Signed-off-by: Wolfram Sang <wsa@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
include/linux/units.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)

diff --git a/include/linux/units.h b/include/linux/units.h
index aaf716364ec3..3457179f7116 100644
--- a/include/linux/units.h
+++ b/include/linux/units.h
@@ -4,6 +4,26 @@

#include <linux/kernel.h>

+/* Metric prefixes in accordance with Système international (d'unités) */
+#define PETA 1000000000000000ULL
+#define TERA 1000000000000ULL
+#define GIGA 1000000000UL
+#define MEGA 1000000UL
+#define KILO 1000UL
+#define HECTO 100UL
+#define DECA 10UL
+#define DECI 10UL
+#define CENTI 100UL
+#define MILLI 1000UL
+#define MICRO 1000000UL
+#define NANO 1000000000UL
+#define PICO 1000000000000ULL
+#define FEMTO 1000000000000000ULL
+
+#define MILLIWATT_PER_WATT 1000L
+#define MICROWATT_PER_MILLIWATT 1000L
+#define MICROWATT_PER_WATT 1000000L
+
#define ABSOLUTE_ZERO_MILLICELSIUS -273150

static inline long milli_kelvin_to_millicelsius(long t)
--
2.25.1


[PATCH v2 5.10.y-cip 00/12] Add thermal driver and watchdog driver enhancements

Biju Das
 

This patch series aims to add thermal driver support and watchdog driver enhancments
for RZ/G2L platform.

v1->v2:
* Removed patch#1 and updated rzg2l_thermal.c to use kernel.h.

Andy Shevchenko (1):
units: Add SI metric prefix definitions

Biju Das (10):
thermal/drivers: Add TSU driver for RZ/G2L
thermal/drivers/rz2gl: Add error check for reset_control_deassert()
thermal/drivers/rz2gl: Fix OTP Calibration Register values
watchdog: rzg2l_wdt: Fix 32bit overflow issue
watchdog: rzg2l_wdt: Fix Runtime PM usage
watchdog: rzg2l_wdt: Fix 'BUG: Invalid wait context'
watchdog: rzg2l_wdt: Fix reset control imbalance
watchdog: rzg2l_wdt: Add error check for reset_control_deassert
watchdog: rzg2l_wdt: Use force reset for WDT reset
watchdog: rzg2l_wdt: Add set_timeout callback

Geert Uytterhoeven (1):
arm64: defconfig: Enable additional support for Renesas platforms

arch/arm64/configs/defconfig | 4 +
drivers/thermal/Kconfig | 9 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/rzg2l_thermal.c | 248 ++++++++++++++++++++++++++++++++
drivers/watchdog/rzg2l_wdt.c | 83 ++++++-----
include/linux/units.h | 20 +++
6 files changed, 329 insertions(+), 36 deletions(-)
create mode 100644 drivers/thermal/rzg2l_thermal.c

--
2.25.1


4.4 & my availability this week

Pavel Machek
 

Hi!

It would not be bad to do 4.4 release this week, but Ill be traveling without internet
access. 4.4-st tree and -cip trees are up-to-date with 4.9.320, with exceptions of random
(and we should probably ignore those) and some TCP changes. I believe we can turn that
into -cip release.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers: Add TSU driver for RZ/G2L

Biju Das
 

Subject: Re: [cip-dev] [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers:
Add TSU driver for RZ/G2L

Hi!

commit 673c68bd48390dad01f7d17670de3e33b60860ac upstream.

The RZ/G2L SoC incorporates a thermal sensor unit (TSU) that
measures the temperature inside the LSI.

The thermal sensor in this unit measures temperatures in the
range from
???40 degree Celsius to 125 degree Celsius with an accuracy of
??3°C.
The TSU repeats measurement at 20 microseconds intervals and
automatically updates the results of measurement.

The TSU has no interrupts as well as no external pins.

This patch adds Thermal Sensor Unit(TSU) driver for RZ/G2L SoC.
+#define TSU_SS_CONV_RUNNING BIT(0)
+
+#define TS_CODE_AVE_SCALE(x) ((x) * 1000000)
+#define MCELSIUS(temp) ((temp) *
MILLIDEGREE_PER_DEGREE)
+#define TS_CODE_CAP_TIMES 8 /* Capture times */
Two spaces, plus "capture times" does not really explain much.
OK, will fix the 2 spaces. For " capture times" Basically we need to
read TSU_SAD register eight times consecutively at 20 microseconds
interval.

I will try to drop the comment /* Capture times */ from mainline,
if it does not really explain the intention.
Or

What about "Total number of ADC data samples"? Does it better?
Please let me know.
Yes, that sounds better.
OK, will upstream these changes.

Thanks and regards,
Biju


Re: [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers: Add TSU driver for RZ/G2L

Pavel Machek
 

Hi!

commit 673c68bd48390dad01f7d17670de3e33b60860ac upstream.

The RZ/G2L SoC incorporates a thermal sensor unit (TSU) that
measures the temperature inside the LSI.

The thermal sensor in this unit measures temperatures in the range
from
???40 degree Celsius to 125 degree Celsius with an accuracy of ??3°C.
The TSU repeats measurement at 20 microseconds intervals and
automatically updates the results of measurement.

The TSU has no interrupts as well as no external pins.

This patch adds Thermal Sensor Unit(TSU) driver for RZ/G2L SoC.
+#define TSU_SS_CONV_RUNNING BIT(0)
+
+#define TS_CODE_AVE_SCALE(x) ((x) * 1000000)
+#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE)
+#define TS_CODE_CAP_TIMES 8 /* Capture times */
Two spaces, plus "capture times" does not really explain much.
OK, will fix the 2 spaces. For " capture times" Basically we need to read
TSU_SAD register eight times consecutively at 20 microseconds interval.

I will try to drop the comment /* Capture times */ from mainline, if it
does not really explain the intention.
Or

What about "Total number of ADC data samples"? Does it better?
Please let me know.
Yes, that sounds better.

Thanks,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers: Add TSU driver for RZ/G2L

Biju Das
 

Hi Pavel,

Subject: RE: [cip-dev] [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers:
Add TSU driver for RZ/G2L

Hi Pavel,

Thanks for the feedback.

Subject: Re: [cip-dev] [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers:
Add TSU driver for RZ/G2L

Hi!

commit 673c68bd48390dad01f7d17670de3e33b60860ac upstream.

The RZ/G2L SoC incorporates a thermal sensor unit (TSU) that
measures the temperature inside the LSI.

The thermal sensor in this unit measures temperatures in the range
from
−40 degree Celsius to 125 degree Celsius with an accuracy of ±3°C.
The TSU repeats measurement at 20 microseconds intervals and
automatically updates the results of measurement.

The TSU has no interrupts as well as no external pins.

This patch adds Thermal Sensor Unit(TSU) driver for RZ/G2L SoC.
+#define TSU_SS_CONV_RUNNING BIT(0)
+
+#define TS_CODE_AVE_SCALE(x) ((x) * 1000000)
+#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE)
+#define TS_CODE_CAP_TIMES 8 /* Capture times */
Two spaces, plus "capture times" does not really explain much.
OK, will fix the 2 spaces. For " capture times" Basically we need to read
TSU_SAD register eight times consecutively at 20 microseconds interval.

I will try to drop the comment /* Capture times */ from mainline, if it
does not really explain the intention.
Or

What about "Total number of ADC data samples"? Does it better?
Please let me know.

Cheers,
Biju


Re: [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers: Add TSU driver for RZ/G2L

Biju Das
 

Hi Pavel,

Thanks for the feedback.

Subject: Re: [cip-dev] [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers:
Add TSU driver for RZ/G2L

Hi!

commit 673c68bd48390dad01f7d17670de3e33b60860ac upstream.

The RZ/G2L SoC incorporates a thermal sensor unit (TSU) that measures
the temperature inside the LSI.

The thermal sensor in this unit measures temperatures in the range
from
−40 degree Celsius to 125 degree Celsius with an accuracy of ±3°C. The
TSU repeats measurement at 20 microseconds intervals and automatically
updates the results of measurement.

The TSU has no interrupts as well as no external pins.

This patch adds Thermal Sensor Unit(TSU) driver for RZ/G2L SoC.
+#define TSU_SS_CONV_RUNNING BIT(0)
+
+#define TS_CODE_AVE_SCALE(x) ((x) * 1000000)
+#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE)
+#define TS_CODE_CAP_TIMES 8 /* Capture times */
Two spaces, plus "capture times" does not really explain much.
OK, will fix the 2 spaces. For " capture times" Basically we need to read
TSU_SAD register eight times consecutively at 20 microseconds interval.

I will try to drop the comment /* Capture times */ from mainline, if it does
not really explain the intention.


+static int rzg2l_thermal_get_temp(void *devdata, int *temp) {
+ struct rzg2l_thermal_priv *priv = devdata;
+ u32 result = 0, dsensor, ts_code_ave;
+ int val, i;
+
+ for (i = 0; i < TS_CODE_CAP_TIMES ; i++) {
+ /* TSU repeats measurement at 20 microseconds intervals and
+ * automatically updates the results of
According to CodingStyle, /* should be on separate line.
My bad, will fix this.


+ dev_dbg(dev, "TSU probed with %s caliberation values",
+ rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0)) ? "hw" : "sw");
Typo, should be "calibration" I guess.
OK, will fix this.

Cheers,
Biju


Re: [PATCH RESEND 5.10.y-cip 13/13] watchdog: rzg2l_wdt: Add set_timeout callback

Biju Das
 

Hi Pavel,

Thanks for the feedback.

Subject: Re: [PATCH RESEND 5.10.y-cip 13/13] watchdog: rzg2l_wdt: Add
set_timeout callback

Hi!

commit 4055ee81009e606e830af1acd9e2e35a36249713 upstream.

This patch adds support for set_timeout callback.

Once WDT is started, the WDT cycle setting register(WDTSET) can be
updated only after issuing a module reset. Otherwise, it will ignore
the writes and will hold the previous value. This patch updates the
WDTSET register if it is active.

+++ b/drivers/watchdog/rzg2l_wdt.c
@@ -115,6 +115,25 @@ static int rzg2l_wdt_stop(struct watchdog_device
*wdev)
return 0;
}

+static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev,
+unsigned int timeout) {
+ struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
+
+ wdev->timeout = timeout;
+
+ /*
+ * If the watchdog is active, reset the module for updating the
WDTSET
+ * register so that it is updated with new timeout values.
+ */
values->value?
Ok, Will fix this in mainline.


+ if (watchdog_active(wdev)) {
+ pm_runtime_put(wdev->parent);
+ reset_control_reset(priv->rstc);
+ rzg2l_wdt_start(wdev);
+ }
This code is quite tricky. AFAICT it is correct, but calling
rzg2l_wdt_stop() instead would make it more readable.
From readability point, this code holds good as we need to do
Module reset for changing time out values for WDT.

But from code optimization point, whatever you suggested is ok.

What do we do here, readability or optimization? Please suggest.

Cheers,
Biju


Re: [PATCH RESEND 5.10.y-cip 01/13] kernel.h: split out mathematical helpers

Biju Das
 

Hi Pavel,

Thanks for the feedback.

Subject: Re: [PATCH RESEND 5.10.y-cip 01/13] kernel.h: split out
mathematical helpers

Hi!

From: Andy Shevchenko <andriy.shevchenko@...>

commit aa6159ab99a9ab5df835b4750b66cf132a5aa292 upstream

kernel.h is being used as a dump for all kinds of stuff for a long
time.
Here is the attempt to start cleaning it up by splitting out
mathematical helpers.

At the same time convert users in header and lib folder to use new
header. Though for time being include new header back to kernel.h to
avoid twisted indirected includes for existing users.
This is rather intrusive for two lines which we really need, and may
cause rejects in future.

I'd suggest identifying the defines needed by the driver, and just adding
those. kernel.h would be acceptable. Or you can add math.h with just
defines needed, but please avoid code movement.
OK, will send v2. By adding needed defines in kernel.h and replacing driver include
math.h->kernel.h

Cheers,
Biju


---
fs/nfs/callback_proc.c | 5 +
include/linux/bitops.h | 11 ++-
include/linux/dcache.h | 1 +
include/linux/iommu-helper.h | 4 +-
include/linux/kernel.h | 173 +--------------------------------
include/linux/math.h | 177 ++++++++++++++++++++++++++++++++++
include/linux/rcu_node_tree.h | 2 +
include/linux/units.h | 2 +-
lib/errname.c | 1 +
lib/errseq.c | 1 +
lib/find_bit.c | 3 +-
lib/math/div64.c | 4 +-
lib/math/int_pow.c | 2 +-
lib/math/int_sqrt.c | 3 +-
lib/math/reciprocal_div.c | 9 +-
15 files changed, 215 insertions(+), 183 deletions(-) create mode
100644 include/linux/math.h


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH RESEND 5.10.y-cip 13/13] watchdog: rzg2l_wdt: Add set_timeout callback

Pavel Machek
 

Hi!

commit 4055ee81009e606e830af1acd9e2e35a36249713 upstream.

This patch adds support for set_timeout callback.

Once WDT is started, the WDT cycle setting register(WDTSET) can be updated
only after issuing a module reset. Otherwise, it will ignore the writes
and will hold the previous value. This patch updates the WDTSET register
if it is active.

+++ b/drivers/watchdog/rzg2l_wdt.c
@@ -115,6 +115,25 @@ static int rzg2l_wdt_stop(struct watchdog_device *wdev)
return 0;
}

+static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
+{
+ struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
+
+ wdev->timeout = timeout;
+
+ /*
+ * If the watchdog is active, reset the module for updating the WDTSET
+ * register so that it is updated with new timeout values.
+ */
values->value?

+ if (watchdog_active(wdev)) {
+ pm_runtime_put(wdev->parent);
+ reset_control_reset(priv->rstc);
+ rzg2l_wdt_start(wdev);
+ }
This code is quite tricky. AFAICT it is correct, but calling
rzg2l_wdt_stop() instead would make it more readable.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH RESEND 5.10.y-cip 03/13] thermal/drivers: Add TSU driver for RZ/G2L

Pavel Machek
 

Hi!

commit 673c68bd48390dad01f7d17670de3e33b60860ac upstream.

The RZ/G2L SoC incorporates a thermal sensor unit (TSU) that measures the
temperature inside the LSI.

The thermal sensor in this unit measures temperatures in the range from
−40 degree Celsius to 125 degree Celsius with an accuracy of ±3°C. The
TSU repeats measurement at 20 microseconds intervals and automatically
updates the results of measurement.

The TSU has no interrupts as well as no external pins.

This patch adds Thermal Sensor Unit(TSU) driver for RZ/G2L SoC.
+#define TSU_SS_CONV_RUNNING BIT(0)
+
+#define TS_CODE_AVE_SCALE(x) ((x) * 1000000)
+#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE)
+#define TS_CODE_CAP_TIMES 8 /* Capture times */
Two spaces, plus "capture times" does not really explain much.

+static int rzg2l_thermal_get_temp(void *devdata, int *temp)
+{
+ struct rzg2l_thermal_priv *priv = devdata;
+ u32 result = 0, dsensor, ts_code_ave;
+ int val, i;
+
+ for (i = 0; i < TS_CODE_CAP_TIMES ; i++) {
+ /* TSU repeats measurement at 20 microseconds intervals and
+ * automatically updates the results of
According to CodingStyle, /* should be on separate line.

+ dev_dbg(dev, "TSU probed with %s caliberation values",
+ rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0)) ? "hw" : "sw");
Typo, should be "calibration" I guess.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: cip/linux-4.4.y-cip build: 187 builds: 5 failed, 182 passed, 6 errors, 200 warnings (v4.4.302-cip69-508-gd887d54a1be6) #kernelci

Pavel Machek
 

Hi!

cip/linux-4.4.y-cip build: 187 builds: 5 failed, 182 passed, 6 errors, 200 warnings (v4.4.302-cip69-508-gd887d54a1be6)

Full Build Summary: https://kernelci.org/build/cip/branch/linux-4.4.y-cip/kernel/v4.4.302-cip69-508-gd887d54a1be6/

Tree: cip
Branch: linux-4.4.y-cip
Git Describe: v4.4.302-cip69-508-gd887d54a1be6
Git Commit: d887d54a1be6de9a74cb732ba80ecaf1cedefb61
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git
Built: 6 unique architectures

Build Failures Detected:

arm:
rpc_defconfig: (gcc-10) FAIL
The log tells me:

arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3
arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’

AFAIK armv3 support has been removed from gcc 9, we're using gcc 10
here. If we still care about such boards we would have to switch to a
older compiler (for that config). Don't know yet if that is possible in
kernelci configuration.
I'm not sure what machine "rpc" is. It is quite probable it does not
really need armv3 instruction set.

mips:
fuloong2e_defconfig: (gcc-10) FAIL
ip27_defconfig: (gcc-10) FAIL
ip28_defconfig: (gcc-10) FAIL
lemote2f_defconfig: (gcc-10) FAIL
According to [1] CIP does not have a single mips reference board, so I
assume we could simply skip mips completely, right?

Should we disable mips unconditionally for all branches, or just for
4.4. because it makes problems here? I would vote for 4.4 disablement
only, but no idea if we can configure that in kernelci configuration.
Let's see...
We could. Even better would be running 4.4-stable with same configs,
and see if they fail, too. If -stable works and -cip fails, we might
want to look into that.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH RESEND 5.10.y-cip 01/13] kernel.h: split out mathematical helpers

Pavel Machek
 

Hi!

From: Andy Shevchenko <andriy.shevchenko@...>

commit aa6159ab99a9ab5df835b4750b66cf132a5aa292 upstream

kernel.h is being used as a dump for all kinds of stuff for a long time.
Here is the attempt to start cleaning it up by splitting out
mathematical helpers.

At the same time convert users in header and lib folder to use new
header. Though for time being include new header back to kernel.h to
avoid twisted indirected includes for existing users.
This is rather intrusive for two lines which we really need, and may
cause rejects in future.

I'd suggest identifying the defines needed by the driver, and just
adding those. kernel.h would be acceptable. Or you can add math.h with
just defines needed, but please avoid code movement.

Best regards,
Pavel

---
fs/nfs/callback_proc.c | 5 +
include/linux/bitops.h | 11 ++-
include/linux/dcache.h | 1 +
include/linux/iommu-helper.h | 4 +-
include/linux/kernel.h | 173 +--------------------------------
include/linux/math.h | 177 ++++++++++++++++++++++++++++++++++
include/linux/rcu_node_tree.h | 2 +
include/linux/units.h | 2 +-
lib/errname.c | 1 +
lib/errseq.c | 1 +
lib/find_bit.c | 3 +-
lib/math/div64.c | 4 +-
lib/math/int_pow.c | 2 +-
lib/math/int_sqrt.c | 3 +-
lib/math/reciprocal_div.c | 9 +-
15 files changed, 215 insertions(+), 183 deletions(-)
create mode 100644 include/linux/math.h


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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