Date   

Cip-kernel-sec Updates for Week of 2021-03-18

Chen-Yu Tsai (Moxa) <wens@...>
 

Hi everyone,

Six new issues this week from the Ubuntu tracker:

- CVE-2020-35519 [net/x25: buffer overflow] - fixed
Looks like a few configs still have X.25 enabled:
4.4.y-cip/x86/plathome_obsvx1.config:CONFIG_X25=m
4.19.y-cip-rt/x86/siemens_i386-rt.config:CONFIG_X25=m
5.10.y-cip-rt/x86/siemens_i386-rt_defconfig:CONFIG_X25=m
Maybe they should be revisited? cip-kernel-config also gives warnings
for CONFIG_X25.

- CVE-2021-20219 [improper synchronization in flush_to_ldisc()] -
likely RedHat only
Report mentions incorrect backport in RedHat kernels.

- CVE-2021-20261 [floppy: race condition data corruption] - fixed
No member enables this except:
4.4.y-cip-rt/x86/siemens_i386-rt.config:CONFIG_BLK_DEV_FD=m
which should probably be turned off.

- CVE-2021-28375 [fastrpc: allows sending kernel RPCs] - fixed
No member enables this.

- CVE-2021-28660 [rtl8188eu: array access out-of-bounds] - fixed
No member enables this.

- CVE-2021-3428 [integer overflow in ext4_es_cache_extent] - unclear [1]
Requires a specially-crafted ext4 FS image, so we likely don't care.

Unfortunately Debian's Salsa service, where the Debian kernel security
issue tracker is
hosted, is currently down, so we only have one source of data this week.


Regards
ChenYu


[1] https://lore.kernel.org/stable/20210317151834.GE2541@quack2.suse.cz/


CIP LAVA maintenance

Chris Paterson
 

Hello all,

The CIP LAVA infrastructure will be going down for maintenance very soon.
Upgrade Gods permitting, it will all be back online later today.

I'll keep you updated.

Kind regards, Chris


Re: CIP IRC weekly meeting today

Kento Yoshida
 

Hi Kudo-san,

I cannot attend. From SWG, I don't have any update, then please skip the SWG part.

Best regards,
Kent

-----Original Message-----
From: cip-dev@... <cip-dev@...> On Behalf Of
masashi.kudo@... via lists.cip-project.org
Sent: Thursday, March 18, 2021 11:51 AM
To: cip-dev@...
Subject: [cip-dev] CIP IRC weekly meeting today

Hi all,

Kindly be reminded to attend the weekly meeting through IRC to discuss technical
topics with CIP kernel today.

*Please note that the IRC meeting was rescheduled to UTC (GMT) 09:00 starting
from the first week of Apr. according to TSC meeting*
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.timea
nddate.com%2Fworldclock%2Fmeetingdetails.html%3Fyear%3D2021%26month%
3D3%26day%3D18%26hour%3D9%26min%3D0%26sec%3D0%26p1%3D224%26
p2%3D179%26p3%3D136%26p4%3D37%26p5%3D241%26p6%3D248&amp;dat
a=04%7C01%7Ckento.yoshida.wz%40renesas.com%7C8feaff5f928f495e215908d
8e9b8ab75%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6375163
26656218276%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoi
V2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=MVtQ4yd%2F
KPMEP%2BXP9ontYfH6t7M1VW50jL2%2FND2Cxng%3D&amp;reserved=0

USWest USEast UK DE TW JP
02:00 05:00 9:00 10:00 17:00 18:00

Channel:
* irc:chat.freenode.net:6667/cip

Last meeting minutes:
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Firclogs.base
rock.org%2Fmeetings%2Fcip%2F2021%2F03%2Fcip.2021-03-11-09.00.log.html&
amp;data=04%7C01%7Ckento.yoshida.wz%40renesas.com%7C8feaff5f928f495e2
15908d8e9b8ab75%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6
37516326656218276%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=e3IqI
DzA9JSf%2BQXMIjX4xGqM5pu3%2Fc2EiSPHIjqmGZw%3D&amp;reserved=0

* Action item
1. Combine root filesystem with kselftest binary - iwamatsu
2. Do some experiment to lower burdens on CI - patersonc

* Kernel maintenance updates
* Kernel testing
* CIP Security
* AOB

The meeting will take 30 min, although it can be extended to an hour if it makes
sense and those involved in the topics can stay. Otherwise, the topic will be taken
offline or in the next meeting.

Best regards,
--
M. Kudo
Cybertrust Japan Co., Ltd.


Re: CIP IRC weekly meeting today

Pavel Machek
 

Hi!


Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today.
I'll not be able to make it to the irc meeting in time.

I have reviewed patches queued for 5.10.24, and am still working on
those.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


CIP IRC weekly meeting today

masashi.kudo@cybertrust.co.jp <masashi.kudo@...>
 

Hi all,

Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today.

*Please note that the IRC meeting was rescheduled to UTC (GMT) 09:00 starting from the first week of Apr. according to TSC meeting*
https://www.timeanddate.com/worldclock/meetingdetails.html?year=2021&month=3&day=18&hour=9&min=0&sec=0&p1=224&p2=179&p3=136&p4=37&p5=241&p6=248

USWest USEast UK DE TW JP
02:00 05:00 9:00 10:00 17:00 18:00

Channel:
* irc:chat.freenode.net:6667/cip

Last meeting minutes:
https://irclogs.baserock.org/meetings/cip/2021/03/cip.2021-03-11-09.00.log.html

* Action item
1. Combine root filesystem with kselftest binary - iwamatsu
2. Do some experiment to lower burdens on CI - patersonc

* Kernel maintenance updates
* Kernel testing
* CIP Security
* AOB

The meeting will take 30 min, although it can be extended to an hour if it makes sense and those involved in the topics can stay. Otherwise, the topic will be taken offline or in the next meeting.

Best regards,
--
M. Kudo
Cybertrust Japan Co., Ltd.


[Solved] RE: [cip-dev] Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Hi,

-----Original Message-----
From: cip-dev@... <cip-dev@...> On Behalf Of Nobuhiro Iwamatsu
Sent: Tuesday, March 16, 2021 3:54 PM
To: cip-dev@...
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi,

-----Original Message-----
From: cip-dev@...
[mailto:cip-dev@...] On Behalf Of Takuo Koguchi
Sent: Tuesday, March 16, 2021 2:54 PM
To: cip-dev@...
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};t
};
```
I am going to look into the difference.
I confirmed that "n25q512a" in the node name and the compatible string are the only difference.
Interestingly, if I used compatible = "n25q512a" instead of compatible
= "s25fl128s1" or "s25fl128s", which is the current setting for
linux-4.19.177-cip, the kernel prints the following message and is able to detect spi-nor flash as expected.

[ 2.701294] spi-nor spi0.0: found s25fl128s1, expected n25q512a
[ 2.711093] spi-nor spi0.0: s25fl128s1 (16384 Kbytes)

Probably the detect mechanism has been changed by the commit.
Apparently setting compatible = "n25q512a" for my board does not make
sense. I'd like to find out why compatible = "s25fl128s1" does not work.
Probably because they are not registered as compatible strings in the driver. They seem to be used as chip names rather
than compatible strings.
Currently, the implementation is to specify "jedec,spi-nor" for the compatible string.
Adding "jedec,spi-nor" to the compatible string has solved the issue.
Now I can confirm that "[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework" is good, and cadence-quadspi is working fine on cyclone V with linux-5.10.y

Thanks!

Takuo Koguchi

Best regards,
Nobuhiro

-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Monday, March 15, 2021 2:31 PM
To: cip-dev@...
Subject: RE: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

Thank you for the information.
It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```
I am going to look into the difference.

Takuo Koguchi

-----Original Message-----
From: cip-dev@...
<cip-dev@...> On Behalf Of Nobuhiro Iwamatsu
Sent: Monday, March 15, 2021 2:25 PM
To: cip-dev@...
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@...
[mailto:cip-dev@...] On Behalf Of Takuo
Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@...
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to
drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result; # first bad commit:
[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476
+++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error
messages, but it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.

https://secure-web.cisco.com/1ChOMrKnSBR5QZeejvrNs3Pf4x8__M_QVUHEr
nB9s
lV-TAWP3NUwe0LEzsirvM7rr-Oqv
RKrgxgI3iQo5ITdUehFyDppd2GljkEzx7izv16pERniX0DeDmzwE5h9pUYqtIxO3WA
FTDu
H_EG-RNhNFqK4LQakZ90sESF6
DMvs_jovN55Xj5u9kNOC_ew76pLtAMAOdN3BZSV_fR_n6tcWlhvqJ6OlUEfrpz9xvy
-gu1
VHrgcgj1BICaBid9bVUza1-T7rBc
I2EjECtd0qCMcsvLYZPxvzfZ9-Hu6rFlaCQ0ruhxZVfHuVWEB37eQmm0HLHYJG2_R_
ousV
eVDk8bJa2iA/https%3A%2F%2
Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fcip%2Flinux-c
ip.g
it%2Ftree%2Farch%2Farm%2Fboot%2Fd
ts%2Fsocfpga_cyclone5_sodia.dts%3Fh%3Dlinux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@...
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to
drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@...>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to
drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194
Groebenzell, Germany



Re: Is cadence-quadspi working on cyclone V?

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: cip-dev@... [mailto:cip-dev@...] On Behalf Of Takuo Koguchi
Sent: Tuesday, March 16, 2021 2:54 PM
To: cip-dev@...
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};t
};
```
I am going to look into the difference.
I confirmed that "n25q512a" in the node name and the compatible string are the only difference.
Interestingly, if I used compatible = "n25q512a" instead of compatible = "s25fl128s1" or "s25fl128s",
which is the current setting for linux-4.19.177-cip,
the kernel prints the following message and is able to detect spi-nor flash as expected.

[ 2.701294] spi-nor spi0.0: found s25fl128s1, expected n25q512a
[ 2.711093] spi-nor spi0.0: s25fl128s1 (16384 Kbytes)

Probably the detect mechanism has been changed by the commit.
Apparently setting compatible = "n25q512a" for my board does not make sense. I'd like to find out why
compatible = "s25fl128s1" does not work.
Probably because they are not registered as compatible strings in the driver. They seem to be used as
chip names rather than compatible strings.
Currently, the implementation is to specify "jedec,spi-nor" for the compatible string.

Best regards,
Nobuhiro

-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Monday, March 15, 2021 2:31 PM
To: cip-dev@...
Subject: RE: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

Thank you for the information.
It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```
I am going to look into the difference.

Takuo Koguchi

-----Original Message-----
From: cip-dev@... <cip-dev@...> On
Behalf Of Nobuhiro Iwamatsu
Sent: Monday, March 15, 2021 2:25 PM
To: cip-dev@...
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@...
[mailto:cip-dev@...] On Behalf Of Takuo Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@...
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result; # first bad commit:
[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476
+++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages,
but it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.

https://secure-web.cisco.com/1ChOMrKnSBR5QZeejvrNs3Pf4x8__M_QVUHErnB9s
lV-TAWP3NUwe0LEzsirvM7rr-Oqv
RKrgxgI3iQo5ITdUehFyDppd2GljkEzx7izv16pERniX0DeDmzwE5h9pUYqtIxO3WAFTDu
H_EG-RNhNFqK4LQakZ90sESF6
DMvs_jovN55Xj5u9kNOC_ew76pLtAMAOdN3BZSV_fR_n6tcWlhvqJ6OlUEfrpz9xvy-gu1
VHrgcgj1BICaBid9bVUza1-T7rBc
I2EjECtd0qCMcsvLYZPxvzfZ9-Hu6rFlaCQ0ruhxZVfHuVWEB37eQmm0HLHYJG2_R_ousV
eVDk8bJa2iA/https%3A%2F%2
Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fcip%2Flinux-cip.g
it%2Ftree%2Farch%2Farm%2Fboot%2Fd
ts%2Fsocfpga_cyclone5_sodia.dts%3Fh%3Dlinux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@...
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@...>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
Germany



Re: Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Iwamatsu-san,

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};t
};
```
I am going to look into the difference.
I confirmed that "n25q512a" in the node name and the compatible string are the only difference.
Interestingly, if I used compatible = "n25q512a" instead of compatible = "s25fl128s1" or "s25fl128s",
which is the current setting for linux-4.19.177-cip,
the kernel prints the following message and is able to detect spi-nor flash as expected.

[ 2.701294] spi-nor spi0.0: found s25fl128s1, expected n25q512a
[ 2.711093] spi-nor spi0.0: s25fl128s1 (16384 Kbytes)

Probably the detect mechanism has been changed by the commit.
Apparently setting compatible = "n25q512a" for my board does not make sense. I'd like to find out why
compatible = "s25fl128s1" does not work.

Regards,

Takuo Koguchi

-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Monday, March 15, 2021 2:31 PM
To: cip-dev@...
Subject: RE: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

Thank you for the information.
It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```
I am going to look into the difference.

Takuo Koguchi

-----Original Message-----
From: cip-dev@... <cip-dev@...> On
Behalf Of Nobuhiro Iwamatsu
Sent: Monday, March 15, 2021 2:25 PM
To: cip-dev@...
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@...
[mailto:cip-dev@...] On Behalf Of Takuo Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@...
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result; # first bad commit:
[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476
+++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages,
but it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.

https://secure-web.cisco.com/1ChOMrKnSBR5QZeejvrNs3Pf4x8__M_QVUHErnB9s
lV-TAWP3NUwe0LEzsirvM7rr-Oqv
RKrgxgI3iQo5ITdUehFyDppd2GljkEzx7izv16pERniX0DeDmzwE5h9pUYqtIxO3WAFTDu
H_EG-RNhNFqK4LQakZ90sESF6
DMvs_jovN55Xj5u9kNOC_ew76pLtAMAOdN3BZSV_fR_n6tcWlhvqJ6OlUEfrpz9xvy-gu1
VHrgcgj1BICaBid9bVUza1-T7rBc
I2EjECtd0qCMcsvLYZPxvzfZ9-Hu6rFlaCQ0ruhxZVfHuVWEB37eQmm0HLHYJG2_R_ousV
eVDk8bJa2iA/https%3A%2F%2
Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fcip%2Flinux-cip.g
it%2Ftree%2Farch%2Farm%2Fboot%2Fd
ts%2Fsocfpga_cyclone5_sodia.dts%3Fh%3Dlinux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@...
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@...>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
Germany



Re: CIP kernel release delayed

Chris Paterson
 

Hello,

From: cip-dev@... <cip-dev@...> On
Behalf Of Nobuhiro Iwamatsu via lists.cip-project.org
Sent: 15 March 2021 21:08

Hello,

The kernel team are planning to release new CIP kernel last weekend, but
we are currently having problems[0]
with the LAVA lab and can't run test it on some reference boards. Therefore,
the release will be delayed.
As soon as LAVA lab is restored, we will test and release it.
Sorry about this!
lab-cip-renesas has been having network issues. We installed a new router today but it didn't fix our woes.
Discussions with the ISP are ongoing.

Kind regards, Chris


Sorry for contacting you late.

Best regards,
Nobuhiro

[0]:
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flava.c
iplatform.org%2Fscheduler%2Falldevices%2Factive&amp;data=04%7C01%7C
chris.paterson2%40renesas.com%7Caa69b8b4019844448bc708d8e7f67837%7
C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637514393074524293%
7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC
JBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=nWs9tSorSmUA3j9A
bhIUc8hk08fDdiNfKNIUNrNlH74%3D&amp;reserved=0


CIP kernel release delayed

Nobuhiro Iwamatsu
 

Hello,

The kernel team are planning to release new CIP kernel last weekend, but we are currently having problems[0]
with the LAVA lab and can't run test it on some reference boards. Therefore, the release will be delayed.
As soon as LAVA lab is restored, we will test and release it.

Sorry for contacting you late.

Best regards,
Nobuhiro

[0]: https://lava.ciplatform.org/scheduler/alldevices/active


Re: Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Iwamatsu-san,

Thank you for the information.
It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```
I am going to look into the difference.

Takuo Koguchi

-----Original Message-----
From: cip-dev@... <cip-dev@...> On Behalf Of Nobuhiro Iwamatsu
Sent: Monday, March 15, 2021 2:25 PM
To: cip-dev@...
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@...
[mailto:cip-dev@...] On Behalf Of Takuo Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@...
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But
it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result; # first bad commit:
[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476
+++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages, but
it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.

https://secure-web.cisco.com/1ChOMrKnSBR5QZeejvrNs3Pf4x8__M_QVUHErnB9slV-TAWP3NUwe0LEzsirvM7rr-Oqv
RKrgxgI3iQo5ITdUehFyDppd2GljkEzx7izv16pERniX0DeDmzwE5h9pUYqtIxO3WAFTDuH_EG-RNhNFqK4LQakZ90sESF6
DMvs_jovN55Xj5u9kNOC_ew76pLtAMAOdN3BZSV_fR_n6tcWlhvqJ6OlUEfrpz9xvy-gu1VHrgcgj1BICaBid9bVUza1-T7rBc
I2EjECtd0qCMcsvLYZPxvzfZ9-Hu6rFlaCQ0ruhxZVfHuVWEB37eQmm0HLHYJG2_R_ousVeVDk8bJa2iA/https%3A%2F%2
Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fcip%2Flinux-cip.git%2Ftree%2Farch%2Farm%2Fboot%2Fd
ts%2Fsocfpga_cyclone5_sodia.dts%3Fh%3Dlinux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@...
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But
it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@...>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But
it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
Germany



Re: Is cadence-quadspi working on cyclone V?

Nobuhiro Iwamatsu
 

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@... [mailto:cip-dev@...] On Behalf Of Takuo Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@...
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result;
# first bad commit: [a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert cadence-quadspi to use spi-mem
framework

It contains significant amount of changes;

cadence-quadspi.c | 476 +++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages, but it does not detect NOR flash on a custom cyclone
V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/tree/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts?h=linux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@...
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@...>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany



Re: Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result;
# first bad commit: [a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476 +++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages, but it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.

Thanks,

Takuo Koguchi

-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@...
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@...>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany



Re: master branch at git.kernel.org/...cip

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: cip-dev@... [mailto:cip-dev@...] On Behalf Of Pavel Machek
Sent: Thursday, March 11, 2021 9:43 PM
To: Chris.Paterson2@...; cip-dev@...
Subject: [cip-dev] master branch at git.kernel.org/...cip

Hi!

Chris pointed out our master branch at git.kernel.org is rather old:

https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/refs/heads

master CIP: Bump version suffix to -cip28 after Renesas patches Ben Hutchings 2 years


Master branch is really not too applicable for our workflow. Yes, 2
years old version of 4.4 looks out of place.

I see these options:

1) leave it alone. (+) It is quite obvious development is not
happening there (-) It looks strange.

2) delete it. (-) I'm not sure that is possible or what problems it
might cause.

3) update it to Linus' 5.12-rc1 and keep it updated. (-) Extra work to
keep it updated, (-) we don't really do anything with mainline commits
newer than 5.10

4) update it to Linus' 5.10, and only touch it when the linux-5.21-cip
is branched out.

Any other ideas?

My preference would be (1) and (4).
I want to choose 1 or 3.
We have multiple release branches, so setting the branch that manages a particular version to
the master branch can be a bit confusing. How about managing a branch similar to LTS tree?

Best regards,
Nobuhiro


Re: Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@...>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany



Re: Is cadence-quadspi working on cyclone V?

Pavel Machek
 

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Hi CIP developers,

 

Can anyone confirm that spi-cadence-quadspi works fine with SPI-NOR on cyclone V?

I recently moved to 5.10.y-cip from 4.19.y-cip, then my custom board with cyclone V failed to detect SPI-NOR

 

Git bisect has told me the first bad commit is

31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/

 

Does this change requires device tree modification?

Any suggestions or comments would be appreciated.

 

Takuo Koguchi

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V


master branch at git.kernel.org/...cip

Pavel Machek
 

Hi!

Chris pointed out our master branch at git.kernel.org is rather old:

https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/refs/heads

master CIP: Bump version suffix to -cip28 after Renesas patches Ben Hutchings 2 years


Master branch is really not too applicable for our workflow. Yes, 2
years old version of 4.4 looks out of place.

I see these options:

1) leave it alone. (+) It is quite obvious development is not
happening there (-) It looks strange.

2) delete it. (-) I'm not sure that is possible or what problems it
might cause.

3) update it to Linus' 5.12-rc1 and keep it updated. (-) Extra work to
keep it updated, (-) we don't really do anything with mainline commits
newer than 5.10

4) update it to Linus' 5.10, and only touch it when the linux-5.21-cip
is branched out.

Any other ideas?

My preference would be (1) and (4).

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


4.4 futex: Change locking rules

Pavel Machek
 

Hi!

There was some discussion about futexes in 4.4 on irc.

https://lore.kernel.org/stable/20210309030605.3295183-2-zhengyejian1@huawei.com/

I don't believe we need to do anything there. Peter Zijlstra is
re-doing locking for futexes, which will have benefits for future
realtime releases. But we have separate patches for 4.4-rt, so we
should be fine.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Cip-kernel-sec Updates for Week of 2021-03-11

Chen-Yu Tsai (Moxa) <wens@...>
 

Hi everyone,

Seven new CVEs this week:
- CVE-2021-20265 [af_unix: memory leak] - fixed
- CVE-2021-20268 [ebpf: signed type overflow] - fixed
- CVE-2021-27363 [iscsi: iscsi_host_get_param() allows sysfs params
larger than 4k] - fixed
- CVE-2021-27364 [iscsi: iscsi_if_recv_msg allows non-root user] - fixed
- CVE-2021-27365 [iscsi: heap buffer overflow] - fixed
- CVE-2021-28038 [xen: netback: fails to honor errors] - fixed
- CVE-2021-28039 [xen: incorrect foreign pages mapping under special
config] - fixed

All fixes have been backported to all relevant stable kernels.

Also, 4.9.y specific follow-up patch for CVE-2020-29368 was merged in 4.9.259.


Regards
ChenYu

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