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[PATCH 5.10.y-cip 08/24] iio: adc: Kconfig: Make RZG2L_ADC depend on ARCH_RZG2L
Biju Das
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit 024b58a30274a9e28d5c7c17b1ec405714047f2a upstream. ADC block is common on Renesas RZ/G2L and RZ/V2L SoC's, so instead of adding dependency for each SoC's add dependency on ARCH_RZG2L. The ARCH_RZG2L config option is already selected by ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Link: https://lore.kernel.org/r/20220406070315.13862-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/iio/adc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index dfa5e1d2a0ca..cbf3defb0732 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -878,7 +878,7 @@ config ROCKCHIP_SARADC config RZG2L_ADC tristate "Renesas RZ/G2L ADC driver" - depends on ARCH_R9A07G044 || COMPILE_TEST + depends on ARCH_RZG2L || COMPILE_TEST help Say yes here to build support for the ADC found in Renesas RZ/G2L family. -- 2.25.1
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[PATCH 5.10.y-cip 07/24] ASoC: sh: Make SND_SOC_RZ depend on ARCH_RZG2L
Biju Das
commit cc691ba94cf8d6c586076ed489bb9d385a2650ad upstream.
The SSI block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of adding dependency for each SoC's add dependency on ARCH_RZG2L. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Link: https://lore.kernel.org/r/20220423164443.146299-1-biju.das.jz@bp.renesas.com Signed-off-by: Mark Brown <broonie@...> Signed-off-by: Biju Das <biju.das.jz@...> --- sound/soc/sh/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig index f19bd15c0900..96d9d7160f30 100644 --- a/sound/soc/sh/Kconfig +++ b/sound/soc/sh/Kconfig @@ -46,7 +46,7 @@ config SND_SOC_RCAR config SND_SOC_RZ tristate "RZ/G2L series SSIF-2 support" - depends on ARCH_R9A07G044 || COMPILE_TEST + depends on ARCH_RZG2L || COMPILE_TEST help This option enables RZ/G2L SSIF-2 sound support. -- 2.25.1
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[PATCH 5.10.y-cip 06/24] soc: renesas: Kconfig: Introduce ARCH_RZG2L config option
Biju Das
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit 088659ad2a830124407edc38da278010c95bcc96 upstream. The Renesas RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L SoCs have identical IP blocks for which drivers are common. To avoid updating the Kconfig files for drivers in common to each SoC, introduce the ARCH_RZG2L config option. The ARCH_RZG2L config option will be selected by the above mentioned SoCs, and the ARCH_RZG2L config option will be used as a dependency for the drivers in common. While at it, move PM and PM_GENERIC_DOMAINS under the ARCH_RZG2L config option instead of keeping it for individual SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220224092114.25737-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/soc/renesas/Kconfig | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 3469021427dd..cf695f624d79 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -40,6 +40,11 @@ config ARCH_RMOBILE select SYS_SUPPORTS_SH_TMU select SYSC_RMOBILE +config ARCH_RZG2L + bool + select PM + select PM_GENERIC_DOMAINS + config ARCH_RZN1 bool select ARM_AMBA @@ -281,15 +286,13 @@ config ARCH_R8A774B1 config ARCH_R9A07G044 bool "ARM64 Platform support for RZ/G2L" - select PM - select PM_GENERIC_DOMAINS + select ARCH_RZG2L help This enables support for the Renesas RZ/G2L SoC variants. config ARCH_R9A07G054 bool "ARM64 Platform support for RZ/V2L" - select PM - select PM_GENERIC_DOMAINS + select ARCH_RZG2L help This enables support for the Renesas RZ/V2L SoC variants. -- 2.25.1
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[PATCH 5.10.y-cip 05/24] soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configs
Biju Das
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit b89acaf8cad188d9a1387d3049ae036a10d9a1f3 upstream. Explicitly select PM and PM_GENERIC_DOMAINS configs for ARCH_R9A07G044 and ARCH_R9A07G054 configs. PM and PM_GENERIC_DOMAINS configs are required for RZ/{G2L,V2L} SoC without these configs the SMARC EVK's won't boot. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Link: https://lore.kernel.org/r/20220221222450.5393-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/soc/renesas/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index bddf91db18fe..3469021427dd 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -281,11 +281,15 @@ config ARCH_R8A774B1 config ARCH_R9A07G044 bool "ARM64 Platform support for RZ/G2L" + select PM + select PM_GENERIC_DOMAINS help This enables support for the Renesas RZ/G2L SoC variants. config ARCH_R9A07G054 bool "ARM64 Platform support for RZ/V2L" + select PM + select PM_GENERIC_DOMAINS help This enables support for the Renesas RZ/V2L SoC variants. -- 2.25.1
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[PATCH 5.10.y-cip 04/24] soc: renesas: Add support for reading product revision for RZ/G2L family
Biju Das
commit cb5508e47e60b85ac033edd8c52245ad51360eb4 upstream.
As per RZ/G2L HW manual (Rev.1.00 Sep, 2021) DEV_ID [31:28] indicates product revision. Use this information to populate the revision info for RZ/G2L family. Signed-off-by: Biju Das <biju.das.jz@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Link: https://lore.kernel.org/r/20220121014117.21248-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/soc/renesas/renesas-soc.c | 55 ++++++++++++++++++------------- 1 file changed, 33 insertions(+), 22 deletions(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index f06a6a160215..1ab78deaa239 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -370,9 +370,11 @@ static int __init renesas_soc_init(void) const struct renesas_soc *soc; const struct renesas_id *id; void __iomem *chipid = NULL; + const char *rev_prefix = ""; struct soc_device *soc_dev; struct device_node *np; const char *soc_id; + int ret; match = of_match_node(renesas_socs, of_root); if (!match) @@ -393,6 +395,17 @@ static int __init renesas_soc_init(void) chipid = ioremap(family->reg, 4); } + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + np = of_find_node_by_path("/"); + of_property_read_string(np, "model", &soc_dev_attr->machine); + of_node_put(np); + + soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL); + soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL); + if (chipid) { product = readl(chipid + id->offset); iounmap(chipid); @@ -407,41 +420,39 @@ static int __init renesas_soc_init(void) eshi = ((product >> 4) & 0x0f) + 1; eslo = product & 0xf; + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", + eshi, eslo); + } else if (id == &id_rzg2l) { + eshi = ((product >> 28) & 0x0f); + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", + eshi); + rev_prefix = "Rev "; } if (soc->id && ((product & id->mask) >> __ffs(id->mask)) != soc->id) { pr_warn("SoC mismatch (product = 0x%x)\n", product); - return -ENODEV; + ret = -ENODEV; + goto free_soc_dev_attr; } } - soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return -ENOMEM; - - np = of_find_node_by_path("/"); - of_property_read_string(np, "model", &soc_dev_attr->machine); - of_node_put(np); - - soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL); - soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL); - if (eshi) - soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi, - eslo); - - pr_info("Detected Renesas %s %s %s\n", soc_dev_attr->family, - soc_dev_attr->soc_id, soc_dev_attr->revision ?: ""); + pr_info("Detected Renesas %s %s %s%s\n", soc_dev_attr->family, + soc_dev_attr->soc_id, rev_prefix, soc_dev_attr->revision ?: ""); soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { - kfree(soc_dev_attr->revision); - kfree_const(soc_dev_attr->soc_id); - kfree_const(soc_dev_attr->family); - kfree(soc_dev_attr); - return PTR_ERR(soc_dev); + ret = PTR_ERR(soc_dev); + goto free_soc_dev_attr; } return 0; + +free_soc_dev_attr: + kfree(soc_dev_attr->revision); + kfree_const(soc_dev_attr->soc_id); + kfree_const(soc_dev_attr->family); + kfree(soc_dev_attr); + return ret; } early_initcall(renesas_soc_init); -- 2.25.1
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[PATCH 5.10.y-cip 03/24] soc: renesas: Identify RZ/V2L SoC
Biju Das
commit 860122d80251c64484883324128ca82fa35423ef upstream.
Add support for identifying the RZ/V2L (R9A07G054) SoC. Signed-off-by: Biju Das <biju.das.jz@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Link: https://lore.kernel.org/r/20220110134659.30424-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/soc/renesas/Kconfig | 5 +++++ drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 71b44c31b012..bddf91db18fe 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -284,6 +284,11 @@ config ARCH_R9A07G044 help This enables support for the Renesas RZ/G2L SoC variants. +config ARCH_R9A07G054 + bool "ARM64 Platform support for RZ/V2L" + help + This enables support for the Renesas RZ/V2L SoC variants. + endif # ARM64 config RST_RCAR diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 95d5e7063ef4..f06a6a160215 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -60,6 +60,10 @@ static const struct renesas_family fam_rzg2l __initconst __maybe_unused = { .name = "RZ/G2L", }; +static const struct renesas_family fam_rzv2l __initconst __maybe_unused = { + .name = "RZ/V2L", +}; + static const struct renesas_family fam_shmobile __initconst __maybe_unused = { .name = "SH-Mobile", .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ @@ -140,6 +144,11 @@ static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = { .id = 0x841c447, }; +static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = { + .family = &fam_rzv2l, + .id = 0x8447447, +}; + static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = { .family = &fam_rcar_gen1, }; @@ -311,6 +320,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #if defined(CONFIG_ARCH_R9A07G044) { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, #endif +#if defined(CONFIG_ARCH_R9A07G054) + { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, +#endif #ifdef CONFIG_ARCH_SH73A0 { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 }, #endif @@ -344,6 +356,7 @@ static const struct renesas_id id_prr __initconst = { static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,bsid", .data = &id_bsid }, { .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l }, + { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, { .compatible = "renesas,prr", .data = &id_prr }, { /* sentinel */ } }; -- 2.25.1
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[PATCH 5.10.y-cip 02/24] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC
Biju Das
commit 4b4a0fd666303a06bbe159552bc055b490b77cdc upstream.
Add DT binding documentation for the SYSC controller found on the RZ/V2L SoC. This SYSC controller is almost identical to the one found on the RZ/G2L SoC, the only difference being that SYSC on RZ/V2L has an additional register to control the DRP-AI. Signed-off-by: Biju Das <biju.das.jz@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Acked-by: Rob Herring <robh@...> Link: https://lore.kernel.org/r/20220110134659.30424-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Biju Das <biju.das.jz@...> --- .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index 84ddc772b003..bb433e75a0ee 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -4,14 +4,14 @@ $id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/G2L System Controller (SYSC) +title: Renesas RZ/{G2L,V2L} System Controller (SYSC) maintainers: - Geert Uytterhoeven <geert+renesas@...> description: - The RZ/G2L System Controller (SYSC) performs system control of the LSI and - supports following functions, + The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI + and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -21,6 +21,7 @@ properties: compatible: enum: - renesas,r9a07g044-sysc # RZ/G2{L,LC} + - renesas,r9a07g054-sysc # RZ/V2L reg: maxItems: 1 -- 2.25.1
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[PATCH 5.10.y-cip 01/24] soc: renesas: Consolidate product register handling
Biju Das
From: Geert Uytterhoeven <geert+renesas@...>
commit 05b22caa7490e4f4c94bbde33c61cf72d187b8f7 upstream. Currently renesas_soc_init() scans the whole device tree up to three times, to find a device node describing a product register. Furthermore, the product register handling for the different variants is very similar, with the major difference being the location of the product bitfield inside the product register. Reduce scanning to a single pass using of_find_matching_node_and_match() instead. Switch to a common handling of product registers, by storing the intrinsics of each product register type in the data field of the corresponding match entry. Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Link: https://lore.kernel.org/r/057721f46c7499de4133135488f0f3da7fb39265.1636570669.git.geert+renesas@glider.be Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/soc/renesas/renesas-soc.c | 115 +++++++++++++++--------------- 1 file changed, 56 insertions(+), 59 deletions(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 8310fce7714e..95d5e7063ef4 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -317,94 +317,92 @@ static const struct of_device_id renesas_socs[] __initconst = { { /* sentinel */ } }; +struct renesas_id { + unsigned int offset; + u32 mask; +}; + +static const struct renesas_id id_bsid __initconst = { + .offset = 0, + .mask = 0xff0000, + /* + * TODO: Upper 4 bits of BSID are for chip version, but the format is + * not known at this time so we don't know how to specify eshi and eslo + */ +}; + +static const struct renesas_id id_rzg2l __initconst = { + .offset = 0xa04, + .mask = 0xfffffff, +}; + +static const struct renesas_id id_prr __initconst = { + .offset = 0, + .mask = 0xff00, +}; + +static const struct of_device_id renesas_ids[] __initconst = { + { .compatible = "renesas,bsid", .data = &id_bsid }, + { .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l }, + { .compatible = "renesas,prr", .data = &id_prr }, + { /* sentinel */ } +}; + static int __init renesas_soc_init(void) { struct soc_device_attribute *soc_dev_attr; + unsigned int product, eshi = 0, eslo; const struct renesas_family *family; const struct of_device_id *match; const struct renesas_soc *soc; + const struct renesas_id *id; void __iomem *chipid = NULL; struct soc_device *soc_dev; struct device_node *np; - unsigned int product, eshi = 0, eslo; + const char *soc_id; match = of_match_node(renesas_socs, of_root); if (!match) return -ENODEV; + soc_id = strchr(match->compatible, ',') + 1; soc = match->data; family = soc->family; - np = of_find_compatible_node(NULL, NULL, "renesas,bsid"); + np = of_find_matching_node_and_match(NULL, renesas_ids, &match); if (np) { + id = match->data; chipid = of_iomap(np, 0); of_node_put(np); - - if (chipid) { - product = readl(chipid); - iounmap(chipid); - - if (soc->id && ((product >> 16) & 0xff) != soc->id) { - pr_warn("SoC mismatch (product = 0x%x)\n", - product); - return -ENODEV; - } - } - - /* - * TODO: Upper 4 bits of BSID are for chip version, but the - * format is not known at this time so we don't know how to - * specify eshi and eslo - */ - - goto done; + } else if (soc->id && family->reg) { + /* Try hardcoded CCCR/PRR fallback */ + id = &id_prr; + chipid = ioremap(family->reg, 4); } - np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc"); - if (np) { - chipid = of_iomap(np, 0); - of_node_put(np); + if (chipid) { + product = readl(chipid + id->offset); + iounmap(chipid); - if (chipid) { - product = readl(chipid + 0x0a04); - iounmap(chipid); + if (id == &id_prr) { + /* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */ + if ((product & 0x7fff) == 0x5210) + product ^= 0x11; + /* R-Car M3-W ES1.3 incorrectly identifies as ES2.1 */ + if ((product & 0x7fff) == 0x5211) + product ^= 0x12; - if (soc->id && (product & 0xfffffff) != soc->id) { - pr_warn("SoC mismatch (product = 0x%x)\n", - product); - return -ENODEV; - } + eshi = ((product >> 4) & 0x0f) + 1; + eslo = product & 0xf; } - goto done; - } - - /* Try PRR first, then hardcoded fallback */ - np = of_find_compatible_node(NULL, NULL, "renesas,prr"); - if (np) { - chipid = of_iomap(np, 0); - of_node_put(np); - } else if (soc->id && family->reg) { - chipid = ioremap(family->reg, 4); - } - if (chipid) { - product = readl(chipid); - iounmap(chipid); - /* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */ - if ((product & 0x7fff) == 0x5210) - product ^= 0x11; - /* R-Car M3-W ES1.3 incorrectly identifies as ES2.1 */ - if ((product & 0x7fff) == 0x5211) - product ^= 0x12; - if (soc->id && ((product >> 8) & 0xff) != soc->id) { + if (soc->id && + ((product & id->mask) >> __ffs(id->mask)) != soc->id) { pr_warn("SoC mismatch (product = 0x%x)\n", product); return -ENODEV; } - eshi = ((product >> 4) & 0x0f) + 1; - eslo = product & 0xf; } -done: soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); if (!soc_dev_attr) return -ENOMEM; @@ -414,8 +412,7 @@ static int __init renesas_soc_init(void) of_node_put(np); soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL); - soc_dev_attr->soc_id = kstrdup_const(strchr(match->compatible, ',') + 1, - GFP_KERNEL); + soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL); if (eshi) soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi, eslo); -- 2.25.1
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[PATCH 5.10.y-cip 00/24] RZ/G2L Fixes from mainline
Biju Das
This patch series are backported from Mainline for supporting
future SoCs as well as various bugs and improvements related to RZ/g2L SMARC EVK Platform. All these patches are cherry-picked from mainline. Biju Das (6): dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC soc: renesas: Identify RZ/V2L SoC soc: renesas: Add support for reading product revision for RZ/G2L family ASoC: sh: Make SND_SOC_RZ depend on ARCH_RZG2L dt-bindings: dma: rz-dmac: Document RZ/V2L SoC arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions Geert Uytterhoeven (2): soc: renesas: Consolidate product register handling arm64: dts: renesas: Fix pin controller node names Heiner Kallweit (2): reset: renesas: Fix Runtime PM usage reset: renesas: Check return value of reset_control_deassert() Jialin Zhang (1): iio: adc: rzg2l_adc: add missing fwnode_handle_put() in rzg2l_adc_parse_properties() Lad Prabhakar (12): soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configs soc: renesas: Kconfig: Introduce ARCH_RZG2L config option iio: adc: Kconfig: Make RZG2L_ADC depend on ARCH_RZG2L dmaengine: sh: Kconfig: Add ARCH_R9A07G054 dependency for RZ_DMAC config option dmaengine: sh: Kconfig: Make RZ_DMAC depend on ARCH_RZG2L reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add description for power-source property ASoC: sh: rz-ssi: Drop SSIFSR_TDC and SSIFSR_RDC macros ASoC: sh: rz-ssi: Propagate error codes returned from platform_get_irq_byname() ASoC: sh: rz-ssi: Release the DMA channels in rz_ssi_probe() error path iio: adc: rzg2l_adc: Fix typo i2c: riic: Simplify reset handling Xu Wang (1): iio: adc: rzg2l_adc: Remove unnecessary print function dev_err() .../bindings/dma/renesas,rz-dmac.yaml | 3 +- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 1 + .../bindings/power/renesas,rzg2l-sysc.yaml | 7 +- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 +- .../boot/dts/renesas/r9a07g044l2-smarc.dts | 1 + .../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 137 ++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 127 ------------- drivers/dma/sh/Kconfig | 6 +- drivers/i2c/busses/i2c-riic.c | 34 ++-- drivers/iio/adc/Kconfig | 2 +- drivers/iio/adc/rzg2l_adc.c | 16 +- drivers/reset/Kconfig | 2 +- drivers/reset/reset-rzg2l-usbphy-ctrl.c | 11 +- drivers/soc/renesas/Kconfig | 12 ++ drivers/soc/renesas/renesas-soc.c | 173 ++++++++++-------- sound/soc/sh/Kconfig | 2 +- sound/soc/sh/rz-ssi.c | 24 +-- 17 files changed, 309 insertions(+), 251 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi -- 2.25.1
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Re: [isar-cip-core] README.secuirty-testing.md: Add steps to verify CIP security image
Jan Kiszka
On 15.07.22 08:04, Shreyas.Karmahe@... wrote:
Hi Jan-San,At least it made it to my inbox - and got lost there as well. Applied now. Thanks, Jan -- Siemens AG, Technology Competence Center Embedded Linux
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Re: cip/linux-4.4.y-cip build: 187 builds: 5 failed, 182 passed, 6 errors, 200 warnings (v4.4.302-cip69-508-gd887d54a1be6)
#kernelci
Florian Bezdeka
Hi all,
On Thu, 2022-07-14 at 05:56 -0700, kernelci.org bot via lists.cip- project.org wrote: cip/linux-4.4.y-cip build: 187 builds: 5 failed, 182 passed, 6 errors, 200 warnings (v4.4.302-cip69-508-gd887d54a1be6)The log tells me: arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3 arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’ AFAIK armv3 support has been removed from gcc 9, we're using gcc 10 here. If we still care about such boards we would have to switch to a older compiler (for that config). Don't know yet if that is possible in kernelci configuration. mips:According to [1] CIP does not have a single mips reference board, so I assume we could simply skip mips completely, right? Should we disable mips unconditionally for all branches, or just for 4.4. because it makes problems here? I would vote for 4.4 disablement only, but no idea if we can configure that in kernelci configuration. Let's see... Alice, Pavel, any further comments? I would try to open a MR within the kernelci-core repository and try to trigger some builds. [1] https://wiki.linuxfoundation.org/civilinfrastructureplatform/ciptesting/cipreferencehardware Best regards, Florian
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[PATCH [5.10.y-cip] 13/13] watchdog: rzg2l_wdt: Add set_timeout callback
Biju Das
commit 4055ee81009e606e830af1acd9e2e35a36249713 upstream.
This patch adds support for set_timeout callback. Once WDT is started, the WDT cycle setting register(WDTSET) can be updated only after issuing a module reset. Otherwise, it will ignore the writes and will hold the previous value. This patch updates the WDTSET register if it is active. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Reviewed-by: Guenter Roeck <linux@...> Link: https://lore.kernel.org/r/20220225175320.11041-8-biju.das.jz@bp.renesas.com Signed-off-by: Guenter Roeck <linux@...> Signed-off-by: Wim Van Sebroeck <wim@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/watchdog/rzg2l_wdt.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 4e7107655cc2..6eea0ee4af49 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -115,6 +115,25 @@ static int rzg2l_wdt_stop(struct watchdog_device *wdev) return 0; } +static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev, unsigned int timeout) +{ + struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev); + + wdev->timeout = timeout; + + /* + * If the watchdog is active, reset the module for updating the WDTSET + * register so that it is updated with new timeout values. + */ + if (watchdog_active(wdev)) { + pm_runtime_put(wdev->parent); + reset_control_reset(priv->rstc); + rzg2l_wdt_start(wdev); + } + + return 0; +} + static int rzg2l_wdt_restart(struct watchdog_device *wdev, unsigned long action, void *data) { @@ -151,6 +170,7 @@ static const struct watchdog_ops rzg2l_wdt_ops = { .start = rzg2l_wdt_start, .stop = rzg2l_wdt_stop, .ping = rzg2l_wdt_ping, + .set_timeout = rzg2l_wdt_set_timeout, .restart = rzg2l_wdt_restart, }; -- 2.25.1
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[PATCH [5.10.y-cip] 12/13] watchdog: rzg2l_wdt: Use force reset for WDT reset
Biju Das
commit f43e6ddbd7d7b63b9e71927a1f50860f8d55f9cc upstream.
This patch uses the force reset(WDTRSTB) for triggering WDT reset for restart callback. This method(ie, Generate Reset (WDTRSTB) Signal on parity error)is faster compared to the overflow method for triggering watchdog reset. Overflow method: reboot: Restarting system Reboot failed -- System halted NOTICE: BL2: v2.5(release):v2.5/rzg2l-1.00-27-gf48f1440c Parity error method: reboot: Restarting system NOTICE: BL2: v2.5(release):v2.5/rzg2l-1.00-27-gf48f1440c Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Reviewed-by: Guenter Roeck <linux@...> Link: https://lore.kernel.org/r/20220225175320.11041-7-biju.das.jz@bp.renesas.com Signed-off-by: Guenter Roeck <linux@...> Signed-off-by: Wim Van Sebroeck <wim@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/watchdog/rzg2l_wdt.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 73b667ed3e99..4e7107655cc2 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -21,8 +21,11 @@ #define WDTSET 0x04 #define WDTTIM 0x08 #define WDTINT 0x0C +#define PECR 0x10 +#define PEEN 0x14 #define WDTCNT_WDTEN BIT(0) #define WDTINT_INTDISP BIT(0) +#define PEEN_FORCE BIT(0) #define WDT_DEFAULT_TIMEOUT 60U @@ -117,17 +120,14 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev, { struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev); - /* Reset the module before we modify any register */ - reset_control_reset(priv->rstc); - clk_prepare_enable(priv->pclk); clk_prepare_enable(priv->osc_clk); - /* smallest counter value to reboot soon */ - rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(1), WDTSET); + /* Generate Reset (WDTRSTB) Signal on parity error */ + rzg2l_wdt_write(priv, 0, PECR); - /* Enable watchdog timer*/ - rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT); + /* Force parity error */ + rzg2l_wdt_write(priv, PEEN_FORCE, PEEN); return 0; } -- 2.25.1
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[PATCH [5.10.y-cip] 11/13] watchdog: rzg2l_wdt: Add error check for reset_control_deassert
Biju Das
commit baf1aace9ad15401f08e048a7f1fdec79821bc61 upstream.
If reset_control_deassert() fails, then we won't be able to access the device registers. Therefore check the return code of reset_control_deassert() and bailout in case of error. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Reviewed-by: Guenter Roeck <linux@...> Link: https://lore.kernel.org/r/20220225175320.11041-6-biju.das.jz@bp.renesas.com Signed-off-by: Guenter Roeck <linux@...> Signed-off-by: Wim Van Sebroeck <wim@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/watchdog/rzg2l_wdt.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 88274704b260..73b667ed3e99 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -203,7 +203,10 @@ static int rzg2l_wdt_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc), "failed to get cpg reset"); - reset_control_deassert(priv->rstc); + ret = reset_control_deassert(priv->rstc); + if (ret) + return dev_err_probe(dev, ret, "failed to deassert"); + pm_runtime_enable(&pdev->dev); priv->wdev.info = &rzg2l_wdt_ident; -- 2.25.1
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[PATCH [5.10.y-cip] 10/13] watchdog: rzg2l_wdt: Fix reset control imbalance
Biju Das
commit 33d04d0fdba9fae18c7d58364643d2c606a43dba upstream.
Both rzg2l_wdt_probe() and rzg2l_wdt_start() calls reset_control_ deassert() which results in a reset control imbalance. This patch fixes reset control imbalance by removing reset_control_ deassert() from rzg2l_wdt_start() and replaces reset_control_assert with reset_control_reset in rzg2l_wdt_stop() as watchdog module can be stopped only by a module reset. This change will allow us to restart WDT after stop() by configuring WDT timeout and enable registers. Fixes: 2cbc5cd0b55fa2 ("watchdog: Add Watchdog Timer driver for RZ/G2L") Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Reviewed-by: Guenter Roeck <linux@...> Link: https://lore.kernel.org/r/20220225175320.11041-5-biju.das.jz@bp.renesas.com Signed-off-by: Guenter Roeck <linux@...> Signed-off-by: Wim Van Sebroeck <wim@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/watchdog/rzg2l_wdt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 48dfe6e5e64f..88274704b260 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -88,7 +88,6 @@ static int rzg2l_wdt_start(struct watchdog_device *wdev) { struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev); - reset_control_deassert(priv->rstc); pm_runtime_get_sync(wdev->parent); /* Initialize time out */ @@ -108,7 +107,7 @@ static int rzg2l_wdt_stop(struct watchdog_device *wdev) struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev); pm_runtime_put(wdev->parent); - reset_control_assert(priv->rstc); + reset_control_reset(priv->rstc); return 0; } -- 2.25.1
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[PATCH [5.10.y-cip] 09/13] watchdog: rzg2l_wdt: Fix 'BUG: Invalid wait context'
Biju Das
commit e4cf89596c1f1e33309556699f910ced4abbaf44 upstream.
This patch fixes the issue 'BUG: Invalid wait context' during restart() callback by using clk_prepare_enable() instead of pm_runtime_get_sync() for turning on the clocks during restart. This issue is noticed when testing with renesas_defconfig. [ 42.213802] reboot: Restarting system [ 42.217860] [ 42.219364] ============================= [ 42.223368] [ BUG: Invalid wait context ] [ 42.227372] 5.17.0-rc5-arm64-renesas-00002-g10393723e35e #522 Not tainted [ 42.234153] ----------------------------- [ 42.238155] systemd-shutdow/1 is trying to lock: [ 42.242766] ffff00000a650828 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x14/0x20 [ 42.250709] other info that might help us debug this: [ 42.255753] context-{4:4} [ 42.258368] 2 locks held by systemd-shutdow/1: [ 42.262806] #0: ffff80000944e1c8 (system_transition_mutex#2){+.+.}-{3:3}, at: __do_sys_reboot+0xd0/0x250 [ 42.272388] #1: ffff8000094c4e40 (rcu_read_lock){....}-{1:2}, at: atomic_notifier_call_chain+0x0/0x150 [ 42.281795] stack backtrace: [ 42.284672] CPU: 0 PID: 1 Comm: systemd-shutdow Not tainted 5.17.0-rc5-arm64-renesas-00002-g10393723e35e #522 [ 42.294577] Hardware name: Renesas SMARC EVK based on r9a07g044c2 (DT) [ 42.301096] Call trace: [ 42.303538] dump_backtrace+0xcc/0xd8 [ 42.307203] show_stack+0x14/0x30 [ 42.310517] dump_stack_lvl+0x88/0xb0 [ 42.314180] dump_stack+0x14/0x2c [ 42.317492] __lock_acquire+0x1b24/0x1b50 [ 42.321502] lock_acquire+0x120/0x3a8 [ 42.325162] __mutex_lock+0x84/0x8f8 [ 42.328737] mutex_lock_nested+0x30/0x58 [ 42.332658] genpd_lock_mtx+0x14/0x20 [ 42.336319] genpd_runtime_resume+0xc4/0x228 [ 42.340587] __rpm_callback+0x44/0x170 [ 42.344337] rpm_callback+0x64/0x70 [ 42.347824] rpm_resume+0x4e0/0x6b8 [ 42.351310] __pm_runtime_resume+0x50/0x78 [ 42.355404] rzg2l_wdt_restart+0x28/0x68 [ 42.359329] watchdog_restart_notifier+0x1c/0x30 [ 42.363943] atomic_notifier_call_chain+0x94/0x150 [ 42.368732] do_kernel_restart+0x24/0x30 [ 42.372652] machine_restart+0x44/0x70 [ 42.376399] kernel_restart+0x3c/0x60 [ 42.380058] __do_sys_reboot+0x228/0x250 [ 42.383977] __arm64_sys_reboot+0x20/0x28 [ 42.387983] invoke_syscall+0x40/0xf8 Fixes: 2cbc5cd0b55fa2 ("watchdog: Add Watchdog Timer driver for RZ/G2L") Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Reviewed-by: Guenter Roeck <linux@...> Link: https://lore.kernel.org/r/20220225175320.11041-4-biju.das.jz@bp.renesas.com Signed-off-by: Guenter Roeck <linux@...> Signed-off-by: Wim Van Sebroeck <wim@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/watchdog/rzg2l_wdt.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 0fc73b8a9567..48dfe6e5e64f 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -43,6 +43,8 @@ struct rzg2l_wdt_priv { struct reset_control *rstc; unsigned long osc_clk_rate; unsigned long delay; + struct clk *pclk; + struct clk *osc_clk; }; static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv) @@ -118,7 +120,9 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev, /* Reset the module before we modify any register */ reset_control_reset(priv->rstc); - pm_runtime_get_sync(wdev->parent); + + clk_prepare_enable(priv->pclk); + clk_prepare_enable(priv->osc_clk); /* smallest counter value to reboot soon */ rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(1), WDTSET); @@ -165,7 +169,6 @@ static int rzg2l_wdt_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct rzg2l_wdt_priv *priv; unsigned long pclk_rate; - struct clk *wdt_clk; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -177,22 +180,20 @@ static int rzg2l_wdt_probe(struct platform_device *pdev) return PTR_ERR(priv->base); /* Get watchdog main clock */ - wdt_clk = clk_get(&pdev->dev, "oscclk"); - if (IS_ERR(wdt_clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no oscclk"); + priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk"); + if (IS_ERR(priv->osc_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk"); - priv->osc_clk_rate = clk_get_rate(wdt_clk); - clk_put(wdt_clk); + priv->osc_clk_rate = clk_get_rate(priv->osc_clk); if (!priv->osc_clk_rate) return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0"); /* Get Peripheral clock */ - wdt_clk = clk_get(&pdev->dev, "pclk"); - if (IS_ERR(wdt_clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no pclk"); + priv->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(priv->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk"); - pclk_rate = clk_get_rate(wdt_clk); - clk_put(wdt_clk); + pclk_rate = clk_get_rate(priv->pclk); if (!pclk_rate) return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0"); -- 2.25.1
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[PATCH [5.10.y-cip] 08/13] watchdog: rzg2l_wdt: Fix Runtime PM usage
Biju Das
commit 95abafe76297fa057de6c3486ef844bd446bdf18 upstream.
Both rzg2l_wdt_probe() and rzg2l_wdt_start() calls pm_runtime_get() which results in a usage counter imbalance. This patch fixes this issue by removing pm_runtime_get() call from probe. Fixes: 2cbc5cd0b55fa2 ("watchdog: Add Watchdog Timer driver for RZ/G2L") Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Reviewed-by: Guenter Roeck <linux@...> Link: https://lore.kernel.org/r/20220225175320.11041-3-biju.das.jz@bp.renesas.com Signed-off-by: Guenter Roeck <linux@...> Signed-off-by: Wim Van Sebroeck <wim@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/watchdog/rzg2l_wdt.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 96f2a018ab62..0fc73b8a9567 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -151,12 +151,11 @@ static const struct watchdog_ops rzg2l_wdt_ops = { .restart = rzg2l_wdt_restart, }; -static void rzg2l_wdt_reset_assert_pm_disable_put(void *data) +static void rzg2l_wdt_reset_assert_pm_disable(void *data) { struct watchdog_device *wdev = data; struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev); - pm_runtime_put(wdev->parent); pm_runtime_disable(wdev->parent); reset_control_assert(priv->rstc); } @@ -206,11 +205,6 @@ static int rzg2l_wdt_probe(struct platform_device *pdev) reset_control_deassert(priv->rstc); pm_runtime_enable(&pdev->dev); - ret = pm_runtime_resume_and_get(&pdev->dev); - if (ret < 0) { - dev_err(dev, "pm_runtime_resume_and_get failed ret=%pe", ERR_PTR(ret)); - goto out_pm_get; - } priv->wdev.info = &rzg2l_wdt_ident; priv->wdev.ops = &rzg2l_wdt_ops; @@ -222,7 +216,7 @@ static int rzg2l_wdt_probe(struct platform_device *pdev) watchdog_set_drvdata(&priv->wdev, priv); ret = devm_add_action_or_reset(&pdev->dev, - rzg2l_wdt_reset_assert_pm_disable_put, + rzg2l_wdt_reset_assert_pm_disable, &priv->wdev); if (ret < 0) return ret; @@ -235,12 +229,6 @@ static int rzg2l_wdt_probe(struct platform_device *pdev) dev_warn(dev, "Specified timeout invalid, using default"); return devm_watchdog_register_device(&pdev->dev, &priv->wdev); - -out_pm_get: - pm_runtime_disable(dev); - reset_control_assert(priv->rstc); - - return ret; } static const struct of_device_id rzg2l_wdt_ids[] = { -- 2.25.1
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[PATCH [5.10.y-cip] 07/13] watchdog: rzg2l_wdt: Fix 32bit overflow issue
Biju Das
commit ea2949df22a533cdf75e4583c00b1ce94cd5a83b upstream.
The value of timer_cycle_us can be 0 due to 32bit overflow. For eg:- If we assign the counter value "0xfff" for computing maxval. This patch fixes this issue by appending ULL to 1024, so that it is promoted to 64bit. This patch also fixes the warning message, 'watchdog: Invalid min and max timeout values, resetting to 0!'. Fixes: 2cbc5cd0b55fa2 ("watchdog: Add Watchdog Timer driver for RZ/G2L") Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Guenter Roeck <linux@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Link: https://lore.kernel.org/r/20220225175320.11041-2-biju.das.jz@bp.renesas.com Signed-off-by: Guenter Roeck <linux@...> Signed-off-by: Wim Van Sebroeck <wim@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/watchdog/rzg2l_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 6b426df34fd6..96f2a018ab62 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -53,7 +53,7 @@ static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv) static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime) { - u64 timer_cycle_us = 1024 * 1024 * (wdttime + 1) * MICRO; + u64 timer_cycle_us = 1024 * 1024ULL * (wdttime + 1) * MICRO; return div64_ul(timer_cycle_us, cycle); } -- 2.25.1
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[PATCH [5.10.y-cip] 06/13] arm64: defconfig: Enable additional support for Renesas platforms
Biju Das
From: Geert Uytterhoeven <geert+renesas@...>
commit 2e8a3335472461927e57d1741ccf1791ff416075 upstream. Increase build and test coverage by enabling support for more hardware present on Renesas SoCs and boards: - Renesas RSPI, RZ/G2L thermal, RZ/G2L WDT watchdog, and OSTM timer, as used on the RZ/G2L SMARC EVK board, - R-Car Image Signal Processor (ISP) and Display Unit embedded MIPI DSI encoder on R-Car V3U, as used on the Falcon board. All of the above are modular, except for thermal, watchdog, and timer. Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Link: https://lore.kernel.org/r/c9800d67f91a90d418a3ce44c59109ae0a87b2d8.1643373223.git.geert+renesas@glider.be Signed-off-by: Biju Das <biju.das.jz@...> [biju: Removed R-Car V3U configs] --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7575dbd6f57c..58a79a3e1cd0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -465,6 +465,7 @@ CONFIG_SPI_ORION=y CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_RPCIF=m +CONFIG_SPI_RSPI=m CONFIG_SPI_QCOM_QSPI=m CONFIG_SPI_QUP=y CONFIG_SPI_QCOM_GENI=m @@ -540,6 +541,7 @@ CONFIG_IMX8MM_THERMAL=m CONFIG_ROCKCHIP_THERMAL=m CONFIG_RCAR_THERMAL=y CONFIG_RCAR_GEN3_THERMAL=y +CONFIG_RZG2L_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_BCM2711_THERMAL=m CONFIG_BCM2835_THERMAL=m @@ -563,6 +565,7 @@ CONFIG_QCOM_WDT=m CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_WATCHDOG=m CONFIG_RENESAS_WDT=y +CONFIG_RENESAS_RZG2LWDT=y CONFIG_UNIPHIER_WATCHDOG=y CONFIG_BCM2835_WDT=y CONFIG_MFD_ALTERA_SYSMGR=y @@ -909,6 +912,7 @@ CONFIG_SM_GPUCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y +CONFIG_RENESAS_OSTM=y CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=y -- 2.25.1
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[PATCH [5.10.y-cip] 05/13] thermal/drivers/rz2gl: Fix OTP Calibration Register values
Biju Das
commit 2d37f5c90bdc659b329dac7cf6d165a4bbf34cb6 upstream.
As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022), the bit 31 of TSU OTP Calibration Register(OTPTSUTRIM) indicates whether bit [11:0] of OTPTSUTRIM is valid or invalid. This patch updates the code to reflect this change. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Link: https://lore.kernel.org/r/20220428093346.7552-1-biju.das.jz@bp.renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@...> Signed-off-by: Biju Das <biju.das.jz@...> --- drivers/thermal/rzg2l_thermal.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/rzg2l_thermal.c b/drivers/thermal/rzg2l_thermal.c index 7a9cdc1f37ca..be07e04c6926 100644 --- a/drivers/thermal/rzg2l_thermal.c +++ b/drivers/thermal/rzg2l_thermal.c @@ -32,6 +32,8 @@ #define TSU_SS 0x10 #define OTPTSUTRIM_REG(n) (0x18 + ((n) * 0x4)) +#define OTPTSUTRIM_EN_MASK BIT(31) +#define OTPTSUTRIM_MASK GENMASK(11, 0) /* Sensor Mode Register(TSU_SM) */ #define TSU_SM_EN_TS BIT(0) @@ -183,11 +185,15 @@ static int rzg2l_thermal_probe(struct platform_device *pdev) pm_runtime_get_sync(dev); priv->calib0 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0)); - if (!priv->calib0) + if (priv->calib0 & OTPTSUTRIM_EN_MASK) + priv->calib0 &= OTPTSUTRIM_MASK; + else priv->calib0 = SW_CALIB0_VAL; priv->calib1 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(1)); - if (!priv->calib1) + if (priv->calib1 & OTPTSUTRIM_EN_MASK) + priv->calib1 &= OTPTSUTRIM_MASK; + else priv->calib1 = SW_CALIB1_VAL; platform_set_drvdata(pdev, priv); -- 2.25.1
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