Date   

[PATCH 4.4.y-cip 12/14] ARM: dts: r8a7742-iwg21d-q7: Add can1 support to carrier board

Lad Prabhakar
 

commit 68ee7720a01cf20e1de20a2e770b6568db18c253 upstream.

This patch enables CAN1 interface exposed through connector J20 on the
carrier board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200907155541.2011-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[PL: Manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
index 728664e901fc..4adcf97ae7c4 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
@@ -130,10 +130,26 @@
};
};

+&can1 {
+ pinctrl-0 = <&can1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
&cmt0 {
status = "okay";
};

+&gpio1 {
+ can-trx-en-gpio{
+ gpio-hog;
+ gpios = <28 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can-trx-en-gpio";
+ };
+};
+
&msiof0 {
pinctrl-0 = <&msiof0_pins>;
pinctrl-names = "default";
@@ -178,6 +194,11 @@
function = "avb";
};

+ can1_pins: can1 {
+ groups = "can1_data_b";
+ function = "can1";
+ };
+
i2c2_pins: i2c2 {
groups = "i2c2_b";
function = "i2c2";
--
2.17.1


[PATCH 4.4.y-cip 11/14] ARM: dts: r8a7742: Add CAN support

Lad Prabhakar
 

commit 5a81ade1dd284a25c25b7582e94e33e5690c3da5 upstream.

Add the definitions for can0 and can1 to the r8a7742 SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200816190732.6905-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[PL: dropped resets property. changed clocks and power-domains properties.]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index a8ce139e9fc5..af6888521595 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -35,6 +35,14 @@
clock-frequency = <0>;
};

+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
@@ -1106,6 +1114,30 @@
status = "disabled";
};

+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7742",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7742_CLK_RCAN0>,
+ <&cpg_clocks R8A7742_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7742",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7742_CLK_RCAN1>,
+ <&cpg_clocks R8A7742_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
scifb0: serial@e6c20000 {
compatible = "renesas,scifb-r8a7742",
"renesas,scifb";
--
2.17.1


[PATCH 4.4.y-cip 10/14] dt-bindings: can: rcar_can: Add r8a7742 support

Lad Prabhakar
 

commit df73446a2882a4336cad473d8eb9d895e49f092b upstream.

Document RZ/G1H (r8a7742) SoC specific bindings. The R8A7742 CAN module
is identical to R-Car Gen2 family.

No driver change is needed due to the fallback compatible value
"renesas,rcar-gen2-can".

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200816190732.6905-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Acked-by: Rob Herring <robh@...>
Signed-off-by: Marc Kleine-Budde <mkl@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
Documentation/devicetree/bindings/net/can/rcar_can.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
index fbad4d514a41..1a179e578541 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
@@ -2,7 +2,8 @@ Renesas R-Car CAN controller Device Tree Bindings
-------------------------------------------------

Required properties:
-- compatible: "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
+- compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC.
+ "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
"renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC.
"renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
"renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
--
2.17.1


[PATCH 4.4.y-cip 09/14] pinctrl: sh-pfc: r8a7790: Add CAN pins, groups and functions

Lad Prabhakar
 

commit bbf369d4e59a248ed715041267951f5cd051b317 upstream.

Add pins, groups and functions for the CAN{0,1} interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200825095448.13093-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[PL: Manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 112 ++++++++++++++++++++++++++-
1 file changed, 110 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 00b64c5ec866..d87f9dbbb302 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1890,6 +1890,86 @@ static const unsigned int avb_gmii_mux[] = {
AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
};
+/* - CAN0 ----------------------------------------------------------------- */
+static const unsigned int can0_data_pins[] = {
+ /* CAN0 RX */
+ RCAR_GP_PIN(1, 17),
+ /* CAN0 TX */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int can0_data_mux[] = {
+ CAN0_RX_MARK,
+ CAN0_TX_MARK,
+};
+static const unsigned int can0_data_b_pins[] = {
+ /* CAN0 RXB */
+ RCAR_GP_PIN(4, 5),
+ /* CAN0 TXB */
+ RCAR_GP_PIN(4, 4),
+};
+static const unsigned int can0_data_b_mux[] = {
+ CAN0_RX_B_MARK,
+ CAN0_TX_B_MARK,
+};
+static const unsigned int can0_data_c_pins[] = {
+ /* CAN0 RXC */
+ RCAR_GP_PIN(4, 26),
+ /* CAN0 TXC */
+ RCAR_GP_PIN(4, 23),
+};
+static const unsigned int can0_data_c_mux[] = {
+ CAN0_RX_C_MARK,
+ CAN0_TX_C_MARK,
+};
+static const unsigned int can0_data_d_pins[] = {
+ /* CAN0 RXD */
+ RCAR_GP_PIN(4, 26),
+ /* CAN0 TXD */
+ RCAR_GP_PIN(4, 18),
+};
+static const unsigned int can0_data_d_mux[] = {
+ CAN0_RX_D_MARK,
+ CAN0_TX_D_MARK,
+};
+/* - CAN1 ----------------------------------------------------------------- */
+static const unsigned int can1_data_pins[] = {
+ /* CAN1 RX */
+ RCAR_GP_PIN(1, 22),
+ /* CAN1 TX */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int can1_data_mux[] = {
+ CAN1_RX_MARK,
+ CAN1_TX_MARK,
+};
+static const unsigned int can1_data_b_pins[] = {
+ /* CAN1 RXB */
+ RCAR_GP_PIN(4, 7),
+ /* CAN1 TXB */
+ RCAR_GP_PIN(4, 6),
+};
+static const unsigned int can1_data_b_mux[] = {
+ CAN1_RX_B_MARK,
+ CAN1_TX_B_MARK,
+};
+/* - CAN Clock -------------------------------------------------------------- */
+static const unsigned int can_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(1, 21),
+};
+
+static const unsigned int can_clk_mux[] = {
+ CAN_CLK_MARK,
+};
+
+static const unsigned int can_clk_b_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(4, 3),
+};
+
+static const unsigned int can_clk_b_mux[] = {
+ CAN_CLK_B_MARK,
+};
/* - DU RGB ----------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
@@ -3958,7 +4038,7 @@ static const unsigned int vin3_clk_mux[] = {
};

static const struct {
- struct sh_pfc_pin_group common[289];
+ struct sh_pfc_pin_group common[297];
struct sh_pfc_pin_group automotive[1];
} pinmux_groups = {
.common = {
@@ -3975,6 +4055,14 @@ static const struct {
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(can0_data),
+ SH_PFC_PIN_GROUP(can0_data_b),
+ SH_PFC_PIN_GROUP(can0_data_c),
+ SH_PFC_PIN_GROUP(can0_data_d),
+ SH_PFC_PIN_GROUP(can1_data),
+ SH_PFC_PIN_GROUP(can1_data_b),
+ SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(can_clk_b),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -4276,6 +4364,23 @@ static const char * const avb_groups[] = {
"avb_gmii",
};

+static const char * const can0_groups[] = {
+ "can0_data",
+ "can0_data_b",
+ "can0_data_c",
+ "can0_data_d",
+};
+
+static const char * const can1_groups[] = {
+ "can1_data",
+ "can1_data_b",
+};
+
+static const char * const can_clk_groups[] = {
+ "can_clk",
+ "can_clk_b",
+};
+
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
@@ -4716,13 +4821,16 @@ static const char * const vin3_groups[] = {
};

static const struct {
- struct sh_pfc_function common[55];
+ struct sh_pfc_function common[58];
struct sh_pfc_function automotive[1];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(can0),
+ SH_PFC_FUNCTION(can1),
+ SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(du2),
--
2.17.1


[PATCH 4.4.y-cip 08/14] ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support

Lad Prabhakar
 

commit 8368ca1540f0ff5bf4cfe92b1ea7fc8045f61d50 upstream.

Add support for the SPI NOR device which is connected to MSIOF0 interface
on the iWave RainboW-G21d-q7 board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200907155541.2011-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[PL: Manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 31 +++++++++++++++++++++++++
1 file changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
index 858d206514e0..728664e901fc 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
@@ -134,6 +134,32 @@
status = "okay";
};

+&msiof0 {
+ pinctrl-0 = <&msiof0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+
+ flash1: flash@0 {
+ compatible = "sst,sst25vf016b", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "user";
+ reg = <0x00000000 0x00200000>;
+ };
+ };
+ };
+};
+
&pcie_bus_clk {
clock-frequency = <100000000>;
};
@@ -157,6 +183,11 @@
function = "i2c2";
};

+ msiof0_pins: msiof0 {
+ groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx";
+ function = "msiof0";
+ };
+
scifa2_pins: scifa2 {
groups = "scifa2_data_c";
function = "scifa2";
--
2.17.1


[PATCH 4.4.y-cip 07/14] spi: sh-msiof: Implement cs-gpios configuration

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit b8761434bdec32fa46a644c26a12d16a9b0f58d8 upstream.

The current support for GPIO chip selects assumes the GPIOs have been
configured by platform code or the boot loader. This includes pinmux
setup and GPIO direction. Hence it does not work as expected when just
described in DT using the "cs-gpios" property.

Fix this by:
1. using devm_gpiod_get_index() to request the GPIO, and thus
configure pinmux, if needed,
2. configuring the GPIO direction is the spi_master.setup() callback.

Use gpio_is_valid() instead of a check on positive numbers.

Note that when using GPIO chip selects, at least one native chip select
must be left unused, as that native chip select will be driven anyway,
and (global) native chip select polarity must be taken into account.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Mark Brown <broonie@...>
[PL: Manually applied the changes, dropped multiple slave support]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/spi/spi-sh-msiof.c | 62 +++++++++++++++++++++++++++++++++++---
1 file changed, 57 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 13aa354aa2e9..2c8690cd0058 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -18,6 +18,7 @@
#include <linux/dmaengine.h>
#include <linux/err.h>
#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
@@ -58,6 +59,8 @@ struct sh_msiof_spi_priv {
bool native_cs_high;
};

+#define MAX_SS 3 /* Maximum number of native chip selects */
+
#define TMDR1 0x00 /* Transmit Mode Register 1 */
#define TMDR2 0x04 /* Transmit Mode Register 2 */
#define TMDR3 0x08 /* Transmit Mode Register 3 */
@@ -534,8 +537,8 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
spi->cs_gpio = (uintptr_t)spi->controller_data;
}

- if (spi->cs_gpio >= 0) {
- gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
+ if (gpio_is_valid(spi->cs_gpio)) {
+ gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
return 0;
}

@@ -564,13 +567,18 @@ static int sh_msiof_prepare_message(struct spi_master *master,
{
struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
const struct spi_device *spi = msg->spi;
+ u32 cs_high;
+
+ if (gpio_is_valid(spi->cs_gpio))
+ cs_high = p->native_cs_high;
+ else
+ cs_high = !!(spi->mode & SPI_CS_HIGH);

/* Configure pins before asserting CS */
sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
!!(spi->mode & SPI_CPHA),
!!(spi->mode & SPI_3WIRE),
- !!(spi->mode & SPI_LSB_FIRST),
- !!(spi->mode & SPI_CS_HIGH));
+ !!(spi->mode & SPI_LSB_FIRST), cs_high);
return 0;
}

@@ -1030,6 +1038,45 @@ static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
}
#endif

+static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
+{
+ struct device *dev = &p->pdev->dev;
+ unsigned int used_ss_mask = 0;
+ unsigned int cs_gpios = 0;
+ unsigned int num_cs, i;
+ int ret;
+
+ ret = gpiod_count(dev, "cs");
+ if (ret <= 0)
+ return 0;
+
+ num_cs = max_t(unsigned int, ret, p->master->num_chipselect);
+ for (i = 0; i < num_cs; i++) {
+ struct gpio_desc *gpiod;
+
+ gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
+ if (!IS_ERR(gpiod)) {
+ cs_gpios++;
+ continue;
+ }
+
+ if (PTR_ERR(gpiod) != -ENOENT)
+ return PTR_ERR(gpiod);
+
+ if (i >= MAX_SS) {
+ dev_err(dev, "Invalid native chip select %d\n", i);
+ return -EINVAL;
+ }
+ used_ss_mask |= BIT(i);
+ }
+ used_ss_mask = ffz(used_ss_mask);
+ if (cs_gpios && used_ss_mask >= MAX_SS) {
+ dev_err(dev, "No unused native chip select available\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
{
@@ -1241,13 +1288,18 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
if (p->info->rx_fifo_override)
p->rx_fifo_size = p->info->rx_fifo_override;

+ /* Setup GPIO chip selects */
+ master->num_chipselect = p->info->num_chipselect;
+ ret = sh_msiof_get_cs_gpios(p);
+ if (ret)
+ goto err1;
+
/* init master code */
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
master->flags = p->chipdata->master_flags;
master->bus_num = pdev->id;
master->dev.of_node = pdev->dev.of_node;
- master->num_chipselect = p->info->num_chipselect;
master->setup = sh_msiof_spi_setup;
master->prepare_message = sh_msiof_prepare_message;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
--
2.17.1


[PATCH 4.4.y-cip 06/14] spi: sh-msiof: Avoid writing to registers from spi_master.setup()

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 7ff0b53c4051145d1cf992d2f60987e6447eed4f upstream.

The spi_master.setup() callback must not change configuration registers,
as that could corrupt I/O that is in progress for other SPI slaves.

The only exception is the configuration of the native chip select
polarity in SPI master mode, as a wrong chip select polarity will cause
havoc during all future transfers to any other SPI slave.

Hence stop writing to registers in sh_msiof_spi_setup(), unless it is
the first call for a controller using a native chip select, or unless
native chip select polarity has changed (note that you'll loose anyway
if I/O is in progress). Even then, only do what is strictly necessary,
instead of calling sh_msiof_spi_set_pin_regs().

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Mark Brown <broonie@...>
[PL: Manually applied the changes, dropped check for slave]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/spi/spi-sh-msiof.c | 32 +++++++++++++++++++++-----------
1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 8c25dbcaae4d..13aa354aa2e9 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -54,6 +54,8 @@ struct sh_msiof_spi_priv {
void *rx_dma_page;
dma_addr_t tx_dma_addr;
dma_addr_t rx_dma_addr;
+ bool native_cs_inited;
+ bool native_cs_high;
};

#define TMDR1 0x00 /* Transmit Mode Register 1 */
@@ -522,8 +524,7 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
{
struct device_node *np = spi->master->dev.of_node;
struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
-
- pm_runtime_get_sync(&p->pdev->dev);
+ u32 clr, set, tmp;

if (!np) {
/*
@@ -533,19 +534,28 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
spi->cs_gpio = (uintptr_t)spi->controller_data;
}

- /* Configure pins before deasserting CS */
- sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
- !!(spi->mode & SPI_CPHA),
- !!(spi->mode & SPI_3WIRE),
- !!(spi->mode & SPI_LSB_FIRST),
- !!(spi->mode & SPI_CS_HIGH));
-
- if (spi->cs_gpio >= 0)
+ if (spi->cs_gpio >= 0) {
gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
+ return 0;
+ }

+ if (p->native_cs_inited &&
+ (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
+ return 0;

+ /* Configure native chip select mode/polarity early */
+ clr = MDR1_SYNCMD_MASK;
+ set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI;
+ if (spi->mode & SPI_CS_HIGH)
+ clr |= BIT(MDR1_SYNCAC_SHIFT);
+ else
+ set |= BIT(MDR1_SYNCAC_SHIFT);
+ pm_runtime_get_sync(&p->pdev->dev);
+ tmp = sh_msiof_read(p, TMDR1) & ~clr;
+ sh_msiof_write(p, TMDR1, tmp | set);
pm_runtime_put(&p->pdev->dev);
-
+ p->native_cs_high = spi->mode & SPI_CS_HIGH;
+ p->native_cs_inited = true;
return 0;
}

--
2.17.1


[PATCH 4.4.y-cip 05/14] ARM: dts: r8a7742-iwg21m: Add SPI NOR support

Lad Prabhakar
 

commit fc7f54fb13b807c556770a69468188947981a400 upstream.

Add support for the SPI NOR device used to boot up the system
to the System on Module DT.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200825085435.8744-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 51 +++++++++++++++++++++++++++
1 file changed, 51 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
index 0f26807f92b8..5621c9ed698f 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -35,6 +35,16 @@
clock-frequency = <20000000>;
};

+&gpio0 {
+ /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */
+ qspi_en {
+ gpio-hog;
+ gpios = <18 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "QSPI_EN";
+ };
+};
+
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
@@ -70,4 +80,45 @@
groups = "mmc1_data4", "mmc1_ctrl";
function = "mmc1";
};
+
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data2";
+ function = "qspi";
+ };
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "sst,sst25vf016b", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x00000000 0x000c0000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "env";
+ reg = <0x000c0000 0x00002000>;
+ };
+ partition@c2000 {
+ label = "user";
+ reg = <0x000c2000 0x0013e000>;
+ };
+ };
+ };
};
--
2.17.1


[PATCH 4.4.y-cip 04/14] ARM: dts: r8a7742: Add QSPI support

Lad Prabhakar
 

commit afdac0bfbd49e46f7046c7f4bad6daa4a3ebf6fc upstream.

Add QSPI DT node to R8A7742 SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200812150048.27721-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[PL: changed clocks and power-domain properties, removed resets property]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index eff54f7ed812..a8ce139e9fc5 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -989,6 +989,21 @@
status = "disabled";
};

+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7742", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7742_CLK_QSPI_MOD>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7742",
"renesas,scifa";
--
2.17.1


[PATCH 4.4.y-cip 03/14] spi: renesas,rspi: Add r8a7742 to the compatible list

Lad Prabhakar
 

commit 08f9793efd3decae75e60bfec2e6068f2d4180df upstream.

Document RZ/G1H (R8A7742) SoC specific bindings. The R8A7742 qspi module
is identical to R-Car Gen2 family.

No driver change is needed due to the fallback compatible value
"renesas,qspi".

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/20200812150048.27721-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@...>
[PL: Patched text version of bindings file]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
Documentation/devicetree/bindings/spi/spi-rspi.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt
index 2f1a3dc069e7..6a30a2112b8e 100644
--- a/Documentation/devicetree/bindings/spi/spi-rspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt
@@ -11,6 +11,7 @@ Required properties:
Examples with soctypes are:
- "renesas,rspi-sh7757" (SH)
- "renesas,rspi-r7s72100" (RZ/A1H)
+ - "renesas,qspi-r8a7742" (RZ/G1H)
- "renesas,qspi-r8a7743" (RZ/G1M)
- "renesas,qspi-r8a7744" (RZ/G1N)
- "renesas,qspi-r8a7745" (RZ/G1E)
--
2.17.1


[PATCH 4.4.y-cip 02/14] ARM: dts: r8a7742-iwg21m: Add RTC support

Lad Prabhakar
 

commit c0ed2ee793f1f5c15d88c0dd458504b7b2aa9d6a upstream.

Enable BQ32000 RTC which is connected to I2C0 on the iWave RainboW-G21M-q7
SOM.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200816193316.7641-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
index 6e8df79bea94..0f26807f92b8 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -35,6 +35,21 @@
clock-frequency = <20000000>;
};

+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rtc@68 {
+ compatible = "ti,bq32000";
+ reg = <0x68>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
&mmcif1 {
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
@@ -46,6 +61,11 @@
};

&pfc {
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
mmc1_pins: mmc1 {
groups = "mmc1_data4", "mmc1_ctrl";
function = "mmc1";
--
2.17.1


[PATCH 4.4.y-cip 01/14] ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically

Lad Prabhakar
 

commit be571bec2cfdb7aaa096d547aa8a1559a0c0cc90 upstream.

Sort the DT nodes alphabetically so that its easier to maintain.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200816193316.7641-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
index 85aff429d408..6e8df79bea94 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -35,13 +35,6 @@
clock-frequency = <20000000>;
};

-&pfc {
- mmc1_pins: mmc1 {
- groups = "mmc1_data4", "mmc1_ctrl";
- function = "mmc1";
- };
-};
-
&mmcif1 {
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
@@ -51,3 +44,10 @@
non-removable;
status = "okay";
};
+
+&pfc {
+ mmc1_pins: mmc1 {
+ groups = "mmc1_data4", "mmc1_ctrl";
+ function = "mmc1";
+ };
+};
--
2.17.1


[PATCH 4.4.y-cip 00/14] Renesas RZ/G1H add support for CAN, IPMMU, QSPI, RTC

Lad Prabhakar
 

Hi All,

This patch series adds support for below peripherals (along with fixes to
msiof driver),
* CAN
* IPMMU
* QSPI
* RTC

All the patches have been cherry picked from upstream kernel.

Cheers,
Prabhakar

Geert Uytterhoeven (2):
spi: sh-msiof: Avoid writing to registers from spi_master.setup()
spi: sh-msiof: Implement cs-gpios configuration

Lad Prabhakar (12):
ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically
ARM: dts: r8a7742-iwg21m: Add RTC support
spi: renesas,rspi: Add r8a7742 to the compatible list
ARM: dts: r8a7742: Add QSPI support
ARM: dts: r8a7742-iwg21m: Add SPI NOR support
ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support
pinctrl: sh-pfc: r8a7790: Add CAN pins, groups and functions
dt-bindings: can: rcar_can: Add r8a7742 support
ARM: dts: r8a7742: Add CAN support
ARM: dts: r8a7742-iwg21d-q7: Add can1 support to carrier board
ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add can0 support to camera DB
ARM: dts: r8a7742: Add IPMMU DT nodes

.../devicetree/bindings/net/can/rcar_can.txt | 3 +-
.../devicetree/bindings/spi/spi-rspi.txt | 1 +
.../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 11 ++
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 52 ++++++++
arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 79 +++++++++++-
arch/arm/boot/dts/r8a7742.dtsi | 90 ++++++++++++++
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 112 +++++++++++++++++-
drivers/spi/spi-sh-msiof.c | 92 +++++++++++---
8 files changed, 418 insertions(+), 22 deletions(-)

--
2.17.1


ISAR Populate SDK

Rajashree Sankar <rajashree.sankar@...>
 

Hello All,
In the ISAR framework,we ran the command to generate SDK
  bitbake <image_name> -c populate_sdk
There was an sdkchroot folder generated in tmp directory.
The instructions given in the readme of this folder tells us to use rootfs of the target.
Should we specify the rootfs  folder of the generated image? If not Please give us detailed instructions.

I have attached the readme file for your reference.
Thanks and Regards,
Rajashree Sankar

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Re: ISAR Populate SDK

Jan Kiszka
 

On 09.11.20 09:56, Rajashree Sankar wrote:
Hello All,
In the ISAR framework,we ran the command to generate SDK
  *bitbake <image_name> -c populate_sdk*
There was an sdkchroot folder generated in tmp directory.
The instructions given in the readme of this folder tells us to use
rootfs of the target.
Should we specify the rootfs  folder of the generated image? If not
Please give us detailed instructions.

I have attached the readme file for your reference.
Thanks and Regards,
Rajashree Sankar
You are on the wrong list again.

Jan

--
Siemens AG, T RDA IOT
Corporate Competence Center Embedded Linux


Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Lad Prabhakar
 

Hi Nobuhiro, Pavel,

-----Original Message-----
From: nobuhiro1.iwamatsu@... <nobuhiro1.iwamatsu@...>
Sent: 09 November 2020 01:46
To: pavel@...; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>
Cc: cip-dev@...; Biju Das <biju.das.jz@...>
Subject: RE: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Hi all,

-----Original Message-----
From: Pavel Machek [mailto:pavel@...]
Sent: Saturday, November 7, 2020 4:33 PM
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Cc: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@...>; Pavel Machek <pavel@...>; Biju Das
<biju.das.jz@...>
Subject: Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Hi!

This patch series adds support for PCIe, SATA and VSP.

All the patches have been cherry-picked from Linux v5.10-rc2.
I don't see any problems with the series, and it passed basic testing,
so I can apply it if there are no other comments.
I reviewed this patch series, there was no issue.
So, I applied and pushed.
Thank you for the review and acceptance.

Cheers,
Prabhakar


Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Nobuhiro Iwamatsu
 

Hi all,

-----Original Message-----
From: Pavel Machek [mailto:pavel@...]
Sent: Saturday, November 7, 2020 4:33 PM
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Cc: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@...>; Pavel Machek <pavel@...>; Biju Das <biju.das.jz@...>
Subject: Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Hi!

This patch series adds support for PCIe, SATA and VSP.

All the patches have been cherry-picked from Linux v5.10-rc2.
I don't see any problems with the series, and it passed basic testing,
so I can apply it if there are no other comments.
I reviewed this patch series, there was no issue.
So, I applied and pushed.

Best regards,
Nobuhiro


Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Pavel Machek
 

Hi!

This patch series adds support for PCIe, SATA and VSP.

All the patches have been cherry-picked from Linux v5.10-rc2.
I don't see any problems with the series, and it passed basic testing,
so I can apply it if there are no other comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


[PATCH 4.4.y-cip 8/8] ARM: dts: r8a7742: Add VSP support

Lad Prabhakar
 

commit a937909702e00d98eac5b91b31a7f2ae112f47bf upstream.

Add VSP support to R8A7742 (RZ/G1H) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Link: https://lore.kernel.org/r/20200911080929.15058-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[PL: dropped resets property. changed clocks and power-domains properties.
added vsp device configuration]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742.dtsi | 55 ++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index ae7c8cbf9f79..eff54f7ed812 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -1617,6 +1617,61 @@
status = "disabled";
};

+ vsp@fe920000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe920000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7742_CLK_VSP1_R>;
+ power-domains = <&cpg_clocks>;
+
+ renesas,has-sru;
+ renesas,#rpf = <5>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <4>;
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7742_CLK_VSP1_S>;
+ power-domains = <&cpg_clocks>;
+
+ renesas,has-lut;
+ renesas,has-sru;
+ renesas,#rpf = <5>;
+ renesas,#uds = <3>;
+ renesas,#wpf = <4>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7742_CLK_VSP1_DU0>;
+ power-domains = <&cpg_clocks>;
+
+ renesas,has-lif;
+ renesas,has-lut;
+ renesas,#rpf = <4>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <4>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7742_CLK_VSP1_DU1>;
+ power-domains = <&cpg_clocks>;
+
+ renesas,has-lif;
+ renesas,has-lut;
+ renesas,#rpf = <4>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7742",
"renesas,cmt-48-gen2";
--
2.17.1


[PATCH 4.4.y-cip 7/8] ARM: dts: r8a7742: Add SATA nodes

Lad Prabhakar
 

commit b9884a16398161bea177f48ddc05884741a8b944 upstream.

Add the SATA device nodes to the R8A7742 device tree.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>
Reviewed-by: Wolfram Sang <wsa+renesas@...>
Link: https://lore.kernel.org/r/1589555337-5498-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[PL: changed clocks and power-domain properties, removed resets property]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm/boot/dts/r8a7742.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 0268c46d8f59..ae7c8cbf9f79 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -1557,6 +1557,26 @@
status = "disabled";
};

+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7742",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7742_CLK_SATA0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7742",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee500000 0 0x200000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7742_CLK_SATA1>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1

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