Date   

[PATCH 4.19.y-cip 08/12] arm64: dts: renesas: r8a774b1: Add INTC-EX device node

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit 04360e4112c3e0e35c08b7fd8d0b2f6e68be4935 upstream.

Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2N.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Link: https://lore.kernel.org/r/1570531132-21856-11-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 2e6bca7..46578de 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -282,6 +282,22 @@
#power-domain-cells = <1>;
};

+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
i2c4: i2c@e66d8000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.7.4


[PATCH 4.19.y-cip 07/12] arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit 133e6c78c4937ea7449cf8542b14f7b37bf470ac upstream.

The plan for the HiHope RZ/G2N board is to enable pciec0 by default,
and use pciec1 physical interface for SATA (as SATA and PCIE1 share
the same physical interface), therefore move pciec1 enabling away
from hihope-rzg2-ex.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Link: https://lore.kernel.org/r/1570178133-21532-8-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 4 ----
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts | 4 ++++
2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
index 4280b19..6870e22 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
@@ -47,10 +47,6 @@
status = "okay";
};

-&pciec1 {
- status = "okay";
-};
-
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
index 6e33a3b..c754fca 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
@@ -13,3 +13,7 @@
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
"renesas,r8a774a1";
};
+
+&pciec1 {
+ status = "okay";
+};
--
2.7.4


[PATCH 4.19.y-cip 06/12] arm64: dts: renesas: r8a774b1: Add PCIe device nodes

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit b3ddadfa28315c6417866eac35a3aee67fc06aa3 upstream.

This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Andrew Murray <andrew.murray@...>
Link: https://lore.kernel.org/r/1570178133-21532-7-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index aede2b3..2e6bca7 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -811,19 +811,57 @@
};

pciec0: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a774b1",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
- /* placeholder */
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
};

pciec1: pcie@ee800000 {
+ compatible = "renesas,pcie-r8a774b1",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xee800000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
- /* placeholder */
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
+ 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
+ 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
+ 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
};

hdmi0: hdmi@fead0000 {
--
2.7.4


[PATCH 4.19.y-cip 05/12] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream.

Add the device nodes for all MSIOF SPI controllers on the RZ/G2N
SoC (a.k.a. r8a774b1).

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Link: https://lore.kernel.org/r/1570178133-21532-6-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 62 +++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index de904426..aede2b3 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -650,6 +650,68 @@
status = "disabled";
};

+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a774b1",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>;
+ dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+ <&dmac2 0x41>, <&dmac2 0x40>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a774b1",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>;
+ dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+ <&dmac2 0x43>, <&dmac2 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a774b1",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>;
+ dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a774b1",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
rcar_sound: sound@ec500000 {
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
--
2.7.4


[PATCH 4.19.y-cip 04/12] arm64: dts: renesas: r8a774b1: Add RWDT node

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit 7213aea4afad4a0642157fce76eb88736bb9b29f upstream.

Populate the device tree node for the Watchdog Timer (RWDT)
controller on the Renesas RZ/G2N (r8a774b1) SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Link: https://lore.kernel.org/r/1570178133-21532-5-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index f42f646..de904426 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -127,8 +127,13 @@
ranges;

rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a774b1-wdt",
+ "renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
};

gpio0: gpio@e6050000 {
--
2.7.4


[PATCH 4.19.y-cip 03/12] dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit 758622581489b159286eeb9b9cc8d24382a610ec upstream.

RZ/G2N (a.k.a. R8A774B1) watchdog implementation is compatible
with R-Car Gen3, therefore add the relevant documentation.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Guenter Roeck <linux@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Rob Herring <robh@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
index 2c0b03a..71f419d 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
@@ -8,6 +8,7 @@ Required properties:
- "renesas,r8a7743-wdt" (RZ/G1M)
- "renesas,r8a7745-wdt" (RZ/G1E)
- "renesas,r8a774a1-wdt" (RZ/G2M)
+ - "renesas,r8a774b1-wdt" (RZ/G2N)
- "renesas,r8a774c0-wdt" (RZ/G2E)
- "renesas,r8a7790-wdt" (R-Car H2)
- "renesas,r8a7791-wdt" (R-Car M2-W)
--
2.7.4


[PATCH 4.19.y-cip 02/12] dt-bindings: watchdog: Rename bindings documentation file

Biju Das <biju.das@...>
 

From: Simon Horman <horms+renesas@...>

commit 3265c3d8f70f0cb98dc7a7a3865200a7b19f654b upstream.

For consistency with the naming of (most) other documentation files for DT
bindings for Renesas IP blocks rename the Renesas WDT documentation file
from renesas-wdt.txt to renesas,wdt.txt.

Signed-off-by: Simon Horman <horms+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Reviewed-by: Guenter Roeck <linux@...>
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
(dropped compatible strings which didnt exist)
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
.../devicetree/bindings/watchdog/renesas,wdt.txt | 45 ++++++++++++++++++++++
.../devicetree/bindings/watchdog/renesas-wdt.txt | 45 ----------------------
2 files changed, 45 insertions(+), 45 deletions(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
delete mode 100644 Documentation/devicetree/bindings/watchdog/renesas-wdt.txt

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
new file mode 100644
index 0000000..2c0b03a
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
@@ -0,0 +1,45 @@
+Renesas Watchdog Timer (WDT) Controller
+
+Required properties:
+ - compatible : Must be "renesas,<soctype>-wdt", followed by a generic
+ fallback compatible string when compatible with the generic
+ version.
+ Examples with soctypes are:
+ - "renesas,r8a7743-wdt" (RZ/G1M)
+ - "renesas,r8a7745-wdt" (RZ/G1E)
+ - "renesas,r8a774a1-wdt" (RZ/G2M)
+ - "renesas,r8a774c0-wdt" (RZ/G2E)
+ - "renesas,r8a7790-wdt" (R-Car H2)
+ - "renesas,r8a7791-wdt" (R-Car M2-W)
+ - "renesas,r8a7792-wdt" (R-Car V2H)
+ - "renesas,r8a7793-wdt" (R-Car M2-N)
+ - "renesas,r8a7794-wdt" (R-Car E2)
+ - "renesas,r8a7795-wdt" (R-Car H3)
+ - "renesas,r8a7796-wdt" (R-Car M3-W)
+ - "renesas,r8a77965-wdt" (R-Car M3-N)
+ - "renesas,r8a77970-wdt" (R-Car V3M)
+ - "renesas,r8a77990-wdt" (R-Car E3)
+ - "renesas,r8a77995-wdt" (R-Car D3)
+ - "renesas,r7s72100-wdt" (RZ/A1)
+ The generic compatible string must be:
+ - "renesas,rza-wdt" for RZ/A
+ - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G1
+ - "renesas,rcar-gen3-wdt" for R-Car Gen3 and RZ/G2
+
+- reg : Should contain WDT registers location and length
+- clocks : the clock feeding the watchdog timer.
+
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+- power-domains : the power domain the WDT belongs to
+- interrupts: Some WDTs have an interrupt when used in interval timer mode
+
+Examples:
+
+ wdt0: watchdog@e6020000 {
+ compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&cpg>;
+ timeout-sec = <60>;
+ };
diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
deleted file mode 100644
index 2c0b03a..0000000
--- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Renesas Watchdog Timer (WDT) Controller
-
-Required properties:
- - compatible : Must be "renesas,<soctype>-wdt", followed by a generic
- fallback compatible string when compatible with the generic
- version.
- Examples with soctypes are:
- - "renesas,r8a7743-wdt" (RZ/G1M)
- - "renesas,r8a7745-wdt" (RZ/G1E)
- - "renesas,r8a774a1-wdt" (RZ/G2M)
- - "renesas,r8a774c0-wdt" (RZ/G2E)
- - "renesas,r8a7790-wdt" (R-Car H2)
- - "renesas,r8a7791-wdt" (R-Car M2-W)
- - "renesas,r8a7792-wdt" (R-Car V2H)
- - "renesas,r8a7793-wdt" (R-Car M2-N)
- - "renesas,r8a7794-wdt" (R-Car E2)
- - "renesas,r8a7795-wdt" (R-Car H3)
- - "renesas,r8a7796-wdt" (R-Car M3-W)
- - "renesas,r8a77965-wdt" (R-Car M3-N)
- - "renesas,r8a77970-wdt" (R-Car V3M)
- - "renesas,r8a77990-wdt" (R-Car E3)
- - "renesas,r8a77995-wdt" (R-Car D3)
- - "renesas,r7s72100-wdt" (RZ/A1)
- The generic compatible string must be:
- - "renesas,rza-wdt" for RZ/A
- - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G1
- - "renesas,rcar-gen3-wdt" for R-Car Gen3 and RZ/G2
-
-- reg : Should contain WDT registers location and length
-- clocks : the clock feeding the watchdog timer.
-
-Optional properties:
-- timeout-sec : Contains the watchdog timeout in seconds
-- power-domains : the power domain the WDT belongs to
-- interrupts: Some WDTs have an interrupt when used in interval timer mode
-
-Examples:
-
- wdt0: watchdog@e6020000 {
- compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&cpg>;
- timeout-sec = <60>;
- };
--
2.7.4


[PATCH 4.19.y-cip 01/12] dt-bindings: spi: sh-msiof: Add r8a774b1 support

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit 97f41c68b83ea5216dbf3ac51fd86b0fbd399a97 upstream.

Document RZ/G2N (R8A774B1) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/1570178133-21532-3-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Mark Brown <broonie@...>
(patched text version of bindings file)
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 4dd4455..5d6360d 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible : "renesas,msiof-r8a7743" (RZ/G1M)
"renesas,msiof-r8a7745" (RZ/G1E)
"renesas,msiof-r8a774a1" (RZ/G2M)
+ "renesas,msiof-r8a774b1" (RZ/G2N)
"renesas,msiof-r8a774c0" (RZ/G2E)
"renesas,msiof-r8a7790" (R-Car H2)
"renesas,msiof-r8a7791" (R-Car M2-W)
--
2.7.4


[PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend peripheral support

Biju Das <biju.das@...>
 

This patch series adds support for following peripherals supported by RZ
G2N,
1: SDHI
2: Watchdog
3: MSIOF
4: PCIE

Please note this patch series is based on top of the series [1].

[1] https://patchwork.kernel.org/project/cip-dev/list/?series=233689&submitter=&state=*&q=&archive=both&delegate=

Biju Das (3):
mmc: renesas_sdhi_internal_dmac: Add r8a774b1 support
arm64: dts: renesas: r8a774b1: Add SDHI support
arm64: dts: renesas: r8a774b1-hihope-rzg2n: Enable HS400 mode

Fabrizio Castro (7):
dt-bindings: spi: sh-msiof: Add r8a774b1 support
dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support
arm64: dts: renesas: r8a774b1: Add RWDT node
arm64: dts: renesas: r8a774b1: Add all MSIOF nodes
arm64: dts: renesas: r8a774b1: Add PCIe device nodes
arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide
about pciec1
arm64: dts: renesas: r8a774b1: Add INTC-EX device node

Lad Prabhakar (1):
dt-bindings: mmc: renesas_sdhi: Add r8a774b1 support

Simon Horman (1):
dt-bindings: watchdog: Rename bindings documentation file

Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
.../devicetree/bindings/watchdog/renesas,wdt.txt | 46 ++++++
.../devicetree/bindings/watchdog/renesas-wdt.txt | 45 ------
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 4 -
.../boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts | 4 +
.../boot/dts/renesas/r8a774b1-hihope-rzg2n.dts | 4 +
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 163 ++++++++++++++++++++-
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
9 files changed, 213 insertions(+), 56 deletions(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
delete mode 100644 Documentation/devicetree/bindings/watchdog/renesas-wdt.txt

--
2.7.4


Re: 4.19.99: huge series, some changes in Renesas hardware, NFS, big changes in power management, AFS

Chris Paterson
 

Hello Pavel,


From: cip-dev <cip-dev-bounces@...> On Behalf Of Pavel
Machek
Sent: 28 January 2020 15:05

Hi!

4.19.99 is out, and it is... huge series. It has some some changes in
Renesas hardware and NFS, big changes in power management on PCs, AFS
support.
Thanks for the heads up.

It's already been tested in our CI:
https://gitlab.com/cip-project/cip-testing/linux-stable-rc-ci/pipelines/112610333

But it's only doing boot testing on r8a7743-iwg20d-q7, r8a7745-iwg22d-sodimm, Altera-Terasic-Deo-Nano and the x86 devices.
(RZ/G2 boards aren't natively supported in the stable v4.19 Kernel)

Kind regards, Chris


If you are familiar with areas above, you may want to look at the
series; you may also want to do some additional testing.

Best regards,
                                                                      Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


4.19.99: huge series, some changes in Renesas hardware, NFS, big changes in power management, AFS

Pavel Machek
 

Hi!

4.19.99 is out, and it is... huge series. It has some some changes in
Renesas hardware and NFS, big changes in power management on PCs, AFS
support.

If you are familiar with areas above, you may want to look at the
series; you may also want to do some additional testing.

Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


Re: [PATCH 4.19.y-cip 0/8] Renesas RZ/G2N extend peripheral support

Pavel Machek
 

Hi!

I reviewd this series, I have no objection to this.
I will apply this if there is no objection from other member.
I did a quick review, and series looks good to me.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/8] Renesas RZ/G2N extend peripheral support

Nobuhiro Iwamatsu
 

Hi Lad,

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@...]
Sent: Monday, January 27, 2020 11:26 PM
To: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 ○SW
C□OST) <nobuhiro1.iwamatsu@...>; Pavel Machek
<pavel@...>
Cc: Chris Paterson <chris.paterson2@...>
Subject: [PATCH 4.19.y-cip 0/8] Renesas RZ/G2N extend peripheral support

This patch series adds support for following peripherals supported by
RZ/G2N, along with adding support for HiHope RZ/G2N sub board
1: DMAC
2: SCIF/HSCIF
3: GPIO controller
4: Ethernet controller

Biju Das (8):
dt-bindings: dmaengine: rcar-dmac: Document R8A774B1 bindings
arm64: dts: renesas: r8a774b1: Add SYS-DMAC device nodes
arm64: dts: renesas: r8a774b1: Add SCIF and HSCIF nodes
dt-bindings: gpio: rcar: Add DT binding for r8a774b1
arm64: dts: renesas: r8a774b1: Add GPIO device nodes
dt-bindings: net: ravb: Add support for r8a774b1 SoC
arm64: dts: renesas: r8a774b1: Add Ethernet AVB node
arm64: dts: renesas: Add HiHope RZ/G2N sub board support

.../devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
.../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
.../devicetree/bindings/net/renesas,ravb.txt | 1 +
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 15 +
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 381
++++++++++++++++++++-
6 files changed, 389 insertions(+), 11 deletions(-) create mode 100644
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
I reviewd this series, I have no objection to this.
I will apply this if there is no objection from other member.

Best regards,
Nobuhio.


Re: [PATCH 4.4.y-cip 00/10] Renesas RZ/G1N extend peripherals supported by platform

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: Pavel Machek [mailto:pavel@...]
Sent: Monday, January 27, 2020 9:04 PM
To: iwamatsu nobuhiro(岩松 信洋 ○SWC□OST)
<nobuhiro1.iwamatsu@...>
Cc: prabhakar.mahadev-lad.rj@...;
cip-dev@...; pavel@...;
chris.paterson2@...
Subject: Re: [PATCH 4.4.y-cip 00/10] Renesas RZ/G1N extend peripherals
supported by platform

Hi!

Lad Prabhakar (1):
usb: host: xhci-plat: Add r8a7744 support

Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 +-
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 26 +++
arch/arm/boot/dts/r8a7744.dtsi | 219
+++++++++++++++++++++
drivers/usb/host/xhci-plat.c | 7 +-
4 files changed, 252 insertions(+), 3 deletions(-)
Looks good to me.
I will apply this series if there is no objection.
Looks good to me, too.
Thanks! I will apply this series.

Best regards,
Nobuhiro


[PATCH 4.19.y-cip 8/8] arm64: dts: renesas: Add HiHope RZ/G2N sub board support

Lad Prabhakar
 

From: Biju Das <biju.das@...>

commit 65005e6a5bb4781a6df3edd42c2e1e7a9f85a445 upstream.

The HiHope RZ/G2N sub board sits below the HiHope RZ/G2N main board.

Signed-off-by: Biju Das <biju.das@...>
Link: https://lore.kernel.org/r/1569831527-1250-6-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 15 +++++++++++++++
2 files changed, 16 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index bfdb3b6..17785e1 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
+dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
new file mode 100644
index 0000000..ab47c0b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N sub board
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2N with sub board";
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
+ "renesas,r8a774b1";
+};
--
2.7.4


[PATCH 4.19.y-cip 7/8] arm64: dts: renesas: r8a774b1: Add Ethernet AVB node

Lad Prabhakar
 

From: Biju Das <biju.das@...>

commit c722d9001ab5586bb5f29d7f79e857a2c892f817 upstream.

This patch adds the SoC specific part of the Ethernet AVB
device tree node.

Signed-off-by: Biju Das <biju.das@...>
Link: https://lore.kernel.org/r/1569831527-1250-5-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 ++++++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 641af27..f42f646 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -486,8 +486,48 @@
};

avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a774b1",
+ "renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>;
- /* placeholder */
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};

can0: can@e6c30000 {
--
2.7.4


[PATCH 4.19.y-cip 6/8] dt-bindings: net: ravb: Add support for r8a774b1 SoC

Lad Prabhakar
 

From: Biju Das <biju.das@...>

commit c1d419d00494487b8401b2ac38d7e8e2a4977d9e upstream.

Document RZ/G2N (R8A774B1) SoC bindings.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@...>
Signed-off-by: David S. Miller <davem@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index 9e3d768..886abb9 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -17,6 +17,7 @@ Required properties:
R-Car Gen2 and RZ/G1 devices.

- "renesas,etheravb-r8a774a1" for the R8A774A1 SoC.
+ - "renesas,etheravb-r8a774b1" for the R8A774B1 SoC.
- "renesas,etheravb-r8a774c0" for the R8A774C0 SoC.
- "renesas,etheravb-r8a7795" for the R8A7795 SoC.
- "renesas,etheravb-r8a7796" for the R8A7796 SoC.
--
2.7.4


[PATCH 4.19.y-cip 5/8] arm64: dts: renesas: r8a774b1: Add GPIO device nodes

Lad Prabhakar
 

From: Biju Das <biju.das@...>

commit bbbb919f3286f3bddfe9b23feaf184860d11d0ac upstream.

Add GPIO device nodes to the DT of the r8a774b1 SoC.

Signed-off-by: Biju Das <biju.das@...>
Link: https://lore.kernel.org/r/1569831527-1250-4-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 64 +++++++++++++++++++++++++++----
1 file changed, 56 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index e6c8cca..641af27 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -132,75 +132,123 @@
};

gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a774b1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 0 16>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
};

gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a774b1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 32 29>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
};

gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a774b1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 64 15>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
};

gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a774b1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 96 16>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
};

gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a774b1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 128 18>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
};

gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a774b1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 160 26>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
};

gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a774b1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 906>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 906>;
};

gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a774b1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 224 4>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
};

pfc: pin-controller@e6060000 {
--
2.7.4


[PATCH 4.19.y-cip 4/8] dt-bindings: gpio: rcar: Add DT binding for r8a774b1

Lad Prabhakar
 

From: Biju Das <biju.das@...>

commit 5ede17d61592844c6d09eaba513f9de14920965c upstream.

Document Renesas' RZ/G2N (R8A774B1) GPIO blocks compatibility within the
relevant dt-bindings.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Acked-by: Rob Herring <robh@...>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index a67a110..8551905 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -7,6 +7,7 @@ Required Properties:
- "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
- "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller.
- "renesas,gpio-r8a774a1": for R8A774A1 (RZ/G2M) compatible GPIO controller.
+ - "renesas,gpio-r8a774b1": for R8A774B1 (RZ/G2N) compatible GPIO controller.
- "renesas,gpio-r8a774c0": for R8A774C0 (RZ/G2E) compatible GPIO controller.
- "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller.
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
--
2.7.4


[PATCH 4.19.y-cip 3/8] arm64: dts: renesas: r8a774b1: Add SCIF and HSCIF nodes

Lad Prabhakar
 

From: Biju Das <biju.das@...>

commit 83e7620a0417cd2716bda35bb89549ffb8692ea0 upstream.

Add the device nodes for RZ/G2N SCIF and HSCIF serial ports,
including clocks, power domains and DMAs.

Signed-off-by: Biju Das <biju.das@...>
Link: https://lore.kernel.org/r/1569831527-1250-3-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 173 +++++++++++++++++++++++++++++-
1 file changed, 171 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index ac3c411..e6c8cca 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -237,8 +237,91 @@
};

hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a774b1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
reg = <0 0xe6540000 0 0x60>;
- /* placeholder */
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a774b1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a774b1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a774b1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ hscif4: serial@e66b0000 {
+ compatible = "renesas,hscif-r8a774b1",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66b0000 0 0x60>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 516>;
+ status = "disabled";
};

hsusb: usb@e6590000 {
@@ -374,20 +457,106 @@
/* placeholder */
};

+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a774b1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a774b1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a774b1",
"renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 64>;
+ reg = <0 0xe6e88000 0 0x40>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x13>, <&dmac1 0x12>,
+ <&dmac2 0x13>, <&dmac2 0x12>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};

+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a774b1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a774b1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6f30000 {
+ compatible = "renesas,scif-r8a774b1",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f30000 0 0x40>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
rcar_sound: sound@ec500000 {
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
--
2.7.4

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