Date   

[PATCH 4.19.y-cip repost 6/6] arm64: dts: renesas: hihope-common: Remove "label" from LEDs

Fabrizio Castro <fabrizio.castro@...>
 

commit f6130381e2a20b0503838477462a3f55f7672434 upstream.

Remove "label" properties from the LEDs device tree nodes, since
we don't have nice labels on the PCB.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 4 ----
1 file changed, 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index cc5dde5..77d183a 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -22,22 +22,18 @@

led0 {
gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
- label = "LED0";
};

led1 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
- label = "LED1";
};

led2 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
- label = "LED2";
};

led3 {
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- label = "LED3";
};
};

--
2.7.4


[PATCH 4.19.y-cip repost 5/6] arm64: dts: renesas: hihope-common: Add LEDs support

Fabrizio Castro <fabrizio.castro@...>
 

commit 1485b6353a9940c5ac5d3f90880207ac95b4e350 upstream.

This patch adds LEDs support to the HiHope RZ/G2[MN] Main Board
common device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index 9dbf1774..cc5dde5 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -17,6 +17,30 @@
stdout-path = "serial0:115200n8";
};

+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
+ label = "LED0";
+ };
+
+ led1 {
+ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+ label = "LED1";
+ };
+
+ led2 {
+ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
+ label = "LED2";
+ };
+
+ led3 {
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ label = "LED3";
+ };
+ };
+
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
--
2.7.4


[PATCH 4.19.y-cip repost 4/6] arm64: dts: renesas: hihope-common: Add uSD and eMMC

Fabrizio Castro <fabrizio.castro@...>
 

commit 015a75077d7b9d95ff882d0a6bbf0913df36a593 upstream.

This patch adds uSD and eMMC support to the HiHope RZ/G2M
board.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 77 ++++++++++++++++++++++++++
1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index 8e9e94d..9dbf1774 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -16,6 +16,37 @@
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
};

&extal_clk {
@@ -39,6 +70,24 @@
groups = "scif_clk_a";
function = "scif_clk";
};
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi3_pins: sd3 {
+ groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
};

&rwdt {
@@ -56,3 +105,31 @@
&scif_clk {
clock-frequency = <14745600>;
};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi3 {
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
+};
--
2.7.4


[PATCH 4.19.y-cip repost 3/6] mmc: renesas_sdhi: prevent overflow for max_req_size

Fabrizio Castro <fabrizio.castro@...>
 

From: Wolfram Sang <wsa+renesas@...>

commit 2a55c1eac78822321d08cb89b1ac2e06e37fd9ff upstream.

max_req_size is calculated by 'max_blk_size * max_blk_count' in the TMIO
core. So, specifying U32_MAX as max_blk_count will overflow this
calculation. It will cause no harm in practice because the immense high
number will overflow into another immense high number. However, it is
not good coding practice, so calculate max_blk_count so that
max_req_size will fit into unsigned int on ARM32/64.

Thanks to the Renesas BSP team for the bug report!

Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 8 ++++----
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 07669d3..7b0bc15 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -96,8 +96,8 @@ static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
.scc_offset = 0x1000,
.taps = rcar_gen3_scc_taps,
.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
- /* DMAC can handle 0xffffffff blk count but only 1 segment */
- .max_blk_count = 0xffffffff,
+ /* DMAC can handle 32bit blk count but only 1 segment */
+ .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
.max_segs = 1,
};

@@ -111,8 +111,8 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
.scc_offset = 0x1000,
.taps = rcar_gen3_scc_taps,
.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
- /* DMAC can handle 0xffffffff blk count but only 1 segment */
- .max_blk_count = 0xffffffff,
+ /* DMAC can handle 32bit blk count but only 1 segment */
+ .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
.max_segs = 1,
};

diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index c3d63ed..80ee745 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -68,7 +68,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
.scc_offset = 0x0300,
.taps = rcar_gen2_scc_taps,
.taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
- .max_blk_count = 0xffffffff,
+ .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
};

/* Definitions for sampling clocks */
--
2.7.4


[PATCH 4.19.y-cip repost 2/6] mmc: tmio: introduce macro for max block size

Fabrizio Castro <fabrizio.castro@...>
 

From: Wolfram Sang <wsa+renesas@...>

commit 609e5fba56fc0ad8e2a5917f64b964c2f4979bc5 upstream.

We will need it later for other calculations.

Signed-off-by: Wolfram Sang <wsa+renesas@...>
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/mmc/host/tmio_mmc.h | 2 ++
drivers/mmc/host/tmio_mmc_core.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 7c40a7e..5904ed4 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -110,6 +110,8 @@
TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
#define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)

+#define TMIO_MAX_BLK_SIZE 512
+
struct tmio_mmc_data;
struct tmio_mmc_host;

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 7d13ca9..daf4803 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -1269,7 +1269,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
mmc->caps2 |= pdata->capabilities2;
mmc->max_segs = pdata->max_segs ? : 32;
- mmc->max_blk_size = 512;
+ mmc->max_blk_size = TMIO_MAX_BLK_SIZE;
mmc->max_blk_count = pdata->max_blk_count ? :
(PAGE_SIZE / mmc->max_blk_size) * mmc->max_segs;
mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
--
2.7.4


[PATCH 4.19.y-cip repost 1/6] mmc: renesas_sdhi: Change HW adjustment register according to speed mode

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Saito <takeshi.saito.xv@...>

commit f0c8234cb9230e3fc128ab4739f65e30bb00ceb5 upstream.

SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF
according to the mode. If it is inappropriate, CRC error tends to occur.

This adds variable "tap_hs400" for HS400 mode and configures SCC_DT2FF
as needed.

Signed-off-by: Takeshi Saito <takeshi.saito.xv@...>
[wsa: rebased to upstream and updated commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund@...>
Tested-by: Marek Vasut <marek.vasut@...>
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/mmc/host/renesas_sdhi.h | 2 ++
drivers/mmc/host/renesas_sdhi_core.c | 8 ++++++++
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
3 files changed, 11 insertions(+)

diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
index f13f798..d58fcfa 100644
--- a/drivers/mmc/host/renesas_sdhi.h
+++ b/drivers/mmc/host/renesas_sdhi.h
@@ -18,6 +18,7 @@
struct renesas_sdhi_scc {
unsigned long clk_rate; /* clock rate for SDR104 */
u32 tap; /* sampling clock position for SDR104 */
+ u32 tap_hs400; /* sampling clock position for HS400 */
};

struct renesas_sdhi_of_data {
@@ -52,6 +53,7 @@ struct renesas_sdhi {
struct pinctrl_state *pins_default, *pins_uhs;
void __iomem *scc_ctl;
u32 scc_tappos;
+ u32 scc_tappos_hs400;
};

#define host_to_priv(host) \
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 45baf5d..8ed44ad 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -297,6 +297,10 @@ static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
/* Set HS400 mode */
sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
sd_ctrl_read16(host, CTL_SDIF_MODE));
+
+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
+ priv->scc_tappos_hs400);
+
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
@@ -356,6 +360,9 @@ static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
/* Reset HS400 mode */
sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
sd_ctrl_read16(host, CTL_SDIF_MODE));
+
+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
+
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
@@ -699,6 +706,7 @@ int renesas_sdhi_probe(struct platform_device *pdev,
if (taps[i].clk_rate == 0 ||
taps[i].clk_rate == host->mmc->f_max) {
priv->scc_tappos = taps->tap;
+ priv->scc_tappos_hs400 = taps->tap_hs400;
hit = true;
break;
}
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index fb7adcb..07669d3 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -81,6 +81,7 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
{
.clk_rate = 0,
.tap = 0x00000300,
+ .tap_hs400 = 0x00000704,
},
};

--
2.7.4


[PATCH 4.19.y-cip repost 0/6] Add eMMC/uSD/LEDs support to HiHope RZ/G2M

Fabrizio Castro <fabrizio.castro@...>
 

Dear All,

This series is to add eMMC/uSD/LEDs support to the HiHope RZ/G2M board,
and depends on series:
https://patchwork.kernel.org/cover/11126905/

Thanks,
Fab

Fabrizio Castro (3):
arm64: dts: renesas: hihope-common: Add uSD and eMMC
arm64: dts: renesas: hihope-common: Add LEDs support
arm64: dts: renesas: hihope-common: Remove "label" from LEDs

Takeshi Saito (1):
mmc: renesas_sdhi: Change HW adjustment register according to speed
mode

Wolfram Sang (2):
mmc: tmio: introduce macro for max block size
mmc: renesas_sdhi: prevent overflow for max_req_size

arch/arm64/boot/dts/renesas/hihope-common.dtsi | 97 ++++++++++++++++++++++++++
drivers/mmc/host/renesas_sdhi.h | 2 +
drivers/mmc/host/renesas_sdhi_core.c | 8 +++
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 9 +--
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 2 +-
drivers/mmc/host/tmio_mmc.h | 2 +
drivers/mmc/host/tmio_mmc_core.c | 2 +-
7 files changed, 116 insertions(+), 6 deletions(-)

--
2.7.4


Re: [PATCH 4.19.y-cip 0/6] Add eMMC/uSD/LEDs support to HiHope RZ/G2M

Fabrizio Castro <fabrizio.castro@...>
 

Hi Iwamatsu-san,

From: nobuhiro1.iwamatsu@... <nobuhiro1.iwamatsu@...>
Sent: 05 September 2019 04:53
Subject: RE: [cip-dev][PATCH 4.19.y-cip 0/6] Add eMMC/uSD/LEDs support to HiHope RZ/G2M

Hi Fabrizio,

-----Original Message-----
From: Fabrizio Castro [mailto:fabrizio.castro@...]
Sent: Thursday, September 5, 2019 12:04 AM
Cc: Chris Paterson <Chris.Paterson2@...>; Biju Das
<biju.das@...>; Fabrizio Castro
<fabrizio.castro@...>; pavel@...; iwamatsu nobuhiro(岩
松 信洋 ○SWC□OST) <nobuhiro1.iwamatsu@...>
Subject: [cip-dev][PATCH 4.19.y-cip 0/6] Add eMMC/uSD/LEDs support to
HiHope RZ/G2M

Dear All,

This series is to add eMMC/uSD/LEDs support to the HiHope RZ/G2M board,
and depends on series:
https://patchwork.kernel.org/cover/11126905/
Have you posted these patches to cip-dev by subject issue?
Please put Pavel and me in CC and send an email to cip-dev.
We will pick patches that came in out personal email.
Ok, I will repost.

Thanks,
Fab



Thanks,
Fab

Best regards,
Nobuhiro


Re: [PATCH resend] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

Jan Kiszka
 

On 05.09.19 03:16, nobuhiro1.iwamatsu@... wrote:
https://patchwork.kernel.org/patch/10754905/

-----Original Message-----
From: Jan Kiszka [mailto:jan.kiszka@...]
Sent: Tuesday, September 3, 2019 10:56 PM
To: iwamatsu nobuhiro(岩松 信洋 ○SWC□OST)
<nobuhiro1.iwamatsu@...>; fabrizio.castro@...;
pavel@...
Cc: cip-dev@...; biju.das@...
Subject: Re: [cip-dev] [PATCH resend] arm64: dts: Remove inconsistent
use of 'arm, armv8' compatible string

On 03.09.19 06:45, nobuhiro1.iwamatsu@... wrote:
Hi Fabrizio,

Thanks for your test.

-----Original Message-----
From: Fabrizio Castro [mailto:fabrizio.castro@...]
Sent: Monday, September 2, 2019 6:05 PM
To: Pavel Machek <pavel@...>
Cc: Chris Paterson <Chris.Paterson2@...>; Biju Das
<biju.das@...>; iwamatsu nobuhiro(岩松 信洋 ○SWC□
OS
T) <nobuhiro1.iwamatsu@...>;
cip-dev@...
Subject: RE: [PATCH resend] arm64: dts: Remove inconsistent use of
'arm,armv8' compatible string

Hi Pavel,

Thank you for the feedback!

From: Pavel Machek <pavel@...>
Sent: 02 September 2019 10:01
Subject: Re: [PATCH resend] arm64: dts: Remove inconsistent use of
'arm,armv8' compatible string

On Mon 2019-09-02 08:51:12, Fabrizio Castro wrote:
Hi Pavel,

I have put you in CC (and kept the ML as recipient this time
around), did you receive the patch with or without the space?
I got just one copy of email, and it does not have [cip-dev]
marking, so I assume it is the direct one.

No extra space.
Then it's down to the mailing list, somehow, this same email reached
the ML, with a space...
https://lists.cip-project.org/pipermail/cip-dev/2019-September/00315
8.html
https://patchwork.kernel.org/patch/11126171/
Hmmm. There may be a problem in Mailman.
Comparing the original patch
(https://lore.kernel.org/linux-amlogic/20190109202934.29304-1-robh@k
ernel.org/raw) to ours:

X-Mailman-Version: 2.1.21 (looks fine)
X-Mailman-Version: 2.1.12 (our potentially broken version)

It looks like 2.1.21 is starting the wrapped around subject line only
with a single space while our version gained a tab. The latter is likely
the core if the issue. I would not expect this difference to be a
configuration option of mailman, rather an issue in the older version
Thank you for information.

And the original patch thread is interesting.
Each subject has space issues. Please see "Thread overview" at the bottom of the page.
https://lore.kernel.org/linux-amlogic/2053cd60-479a-4219-2415-ebb6a860a8e7@kernel.org/t/
Interesting. There seem to be more mail processing tools involved that decided to wrap at the comma, although there was no space following after it.

Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux


Re: [PATCH 4.19.y-cip 0/6] Add eMMC/uSD/LEDs support to HiHope RZ/G2M

Nobuhiro Iwamatsu
 

Hi Fabrizio,

-----Original Message-----
From: Fabrizio Castro [mailto:fabrizio.castro@...]
Sent: Thursday, September 5, 2019 12:04 AM
Cc: Chris Paterson <Chris.Paterson2@...>; Biju Das
<biju.das@...>; Fabrizio Castro
<fabrizio.castro@...>; pavel@...; iwamatsu nobuhiro(岩
松 信洋 ○SWC□OST) <nobuhiro1.iwamatsu@...>
Subject: [cip-dev][PATCH 4.19.y-cip 0/6] Add eMMC/uSD/LEDs support to
HiHope RZ/G2M

Dear All,

This series is to add eMMC/uSD/LEDs support to the HiHope RZ/G2M board,
and depends on series:
https://patchwork.kernel.org/cover/11126905/
Have you posted these patches to cip-dev by subject issue?
Please put Pavel and me in CC and send an email to cip-dev.
We will pick patches that came in out personal email.


Thanks,
Fab

Best regards,
Nobuhiro


CIP IRC weekly meeting today

SZ Lin (林上智) <SZ.Lin@...>
 

Hi all,

 

Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today.

 

*Please note that IRC meeting was rescheduled to UTC (GMT) 09:00 starting from the first week of Apr. according to TSC meeting*

https://www.timeanddate.com/worldclock/meetingdetails.html?year=2019&month=9&day=5&hour=9&min=0&sec=0&p1=241&p2=137&p3=179&p4=136&p5=37&p6=248

         

US-West US-East   UK     DE     TW     JP

02:00    05:00   10:00   11:00   17:00   18:00

 

Channel:

* irc:chat.freenode.net:6667/cip

 

Agenda:

 

* Action item

1. Provide the cases to cip-testing to build up the test environment - Iwamatsu-san

 

2. Ask cip-dev which configurations need testing - patersonc

 

3. Test LTS (pre)releases directly patersonc

 

* Kernel maintenance updates

* Kernel testing

* CIP Core

* Software update

* AOB

 

The meeting will take 30 min, although it can be extended to an hour if it makes sense and those involved in the topics can stay. Otherwise, the topic will be taken offline or in the next meeting.

 

Best regards,

 

SZ Lin, Moxa.


Re: [PATCH resend] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

Nobuhiro Iwamatsu
 

-----Original Message-----
From: Jan Kiszka [mailto:jan.kiszka@...]
Sent: Tuesday, September 3, 2019 10:56 PM
To: iwamatsu nobuhiro(岩松 信洋 ○SWC□OST)
<nobuhiro1.iwamatsu@...>; fabrizio.castro@...;
pavel@...
Cc: cip-dev@...; biju.das@...
Subject: Re: [cip-dev] [PATCH resend] arm64: dts: Remove inconsistent
use of 'arm, armv8' compatible string

On 03.09.19 06:45, nobuhiro1.iwamatsu@... wrote:
Hi Fabrizio,

Thanks for your test.

-----Original Message-----
From: Fabrizio Castro [mailto:fabrizio.castro@...]
Sent: Monday, September 2, 2019 6:05 PM
To: Pavel Machek <pavel@...>
Cc: Chris Paterson <Chris.Paterson2@...>; Biju Das
<biju.das@...>; iwamatsu nobuhiro(岩松 信洋 ○SWC□
OS
T) <nobuhiro1.iwamatsu@...>;
cip-dev@...
Subject: RE: [PATCH resend] arm64: dts: Remove inconsistent use of
'arm,armv8' compatible string

Hi Pavel,

Thank you for the feedback!

From: Pavel Machek <pavel@...>
Sent: 02 September 2019 10:01
Subject: Re: [PATCH resend] arm64: dts: Remove inconsistent use of
'arm,armv8' compatible string

On Mon 2019-09-02 08:51:12, Fabrizio Castro wrote:
Hi Pavel,

I have put you in CC (and kept the ML as recipient this time
around), did you receive the patch with or without the space?
I got just one copy of email, and it does not have [cip-dev]
marking, so I assume it is the direct one.

No extra space.
Then it's down to the mailing list, somehow, this same email reached
the ML, with a space...
https://lists.cip-project.org/pipermail/cip-dev/2019-September/00315
8.html
https://patchwork.kernel.org/patch/11126171/
Hmmm. There may be a problem in Mailman.
Comparing the original patch
(https://lore.kernel.org/linux-amlogic/20190109202934.29304-1-robh@k
ernel.org/raw) to ours:

X-Mailman-Version: 2.1.21 (looks fine)
X-Mailman-Version: 2.1.12 (our potentially broken version)

It looks like 2.1.21 is starting the wrapped around subject line only
with a single space while our version gained a tab. The latter is likely
the core if the issue. I would not expect this difference to be a
configuration option of mailman, rather an issue in the older version
Thank you for information.

And the original patch thread is interesting.
Each subject has space issues. Please see "Thread overview" at the bottom of the page.
https://lore.kernel.org/linux-amlogic/2053cd60-479a-4219-2415-ebb6a860a8e7@kernel.org/t/


HTH,
Jan
Best regards,
Nobuhiro


Re: [PATCH resend] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

Jan Kiszka
 

On 03.09.19 06:45, nobuhiro1.iwamatsu@... wrote:
Hi Fabrizio,

Thanks for your test.

-----Original Message-----
From: Fabrizio Castro [mailto:fabrizio.castro@...]
Sent: Monday, September 2, 2019 6:05 PM
To: Pavel Machek <pavel@...>
Cc: Chris Paterson <Chris.Paterson2@...>; Biju Das
<biju.das@...>; iwamatsu nobuhiro(岩松 信洋 ○SWC□OS
T) <nobuhiro1.iwamatsu@...>; cip-dev@...
Subject: RE: [PATCH resend] arm64: dts: Remove inconsistent use of
'arm,armv8' compatible string

Hi Pavel,

Thank you for the feedback!

From: Pavel Machek <pavel@...>
Sent: 02 September 2019 10:01
Subject: Re: [PATCH resend] arm64: dts: Remove inconsistent use of
'arm,armv8' compatible string

On Mon 2019-09-02 08:51:12, Fabrizio Castro wrote:
Hi Pavel,

I have put you in CC (and kept the ML as recipient this time
around), did you receive the patch with or without the space?
I got just one copy of email, and it does not have [cip-dev] marking,
so I assume it is the direct one.

No extra space.
Then it's down to the mailing list, somehow, this same email reached the
ML, with a space...
https://lists.cip-project.org/pipermail/cip-dev/2019-September/00315
8.html
https://patchwork.kernel.org/patch/11126171/
Hmmm. There may be a problem in Mailman.
Comparing the original patch (https://lore.kernel.org/linux-amlogic/20190109202934.29304-1-robh@kernel.org/raw) to ours:

X-Mailman-Version: 2.1.21 (looks fine)
X-Mailman-Version: 2.1.12 (our potentially broken version)

It looks like 2.1.21 is starting the wrapped around subject line only with a single space while our version gained a tab. The latter is likely the core if the issue. I would not expect this difference to be a configuration option of mailman, rather an issue in the older version

HTH,
Jan

Who is the person responsible for looking after the ML?
Maybe Kobayashi-san. I just talked to him about this.
Please wait a minute.

Thanks,
Fab
Best regards,
Nobuhiro
_______________________________________________
cip-dev mailing list
cip-dev@...
https://lists.cip-project.org/mailman/listinfo/cip-dev
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux


[PATCH Test 2nd] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

Nobuhiro Iwamatsu
 

From: Fabrizio Castro <fabrizio.castro@...>

From: Rob Herring <robh@...>

commit 31af04cd60d3162a58213363fd740a2b0cf0a08e upstream.

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@...>
Cc: Mark Rutland <mark.rutland@...>
Cc: Will Deacon <will.deacon@...>
Acked-by: Antoine Tenart <antoine.tenart@...>
Acked-by: Nishanth Menon <nm@...>
Acked-by: Maxime Ripard <maxime.ripard@...>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@...>
Acked-by: Chanho Min <chanho.min@...>
Acked-by: Krzysztof Kozlowski <krzk@...>
Acked-by: Masahiro Yamada <yamada.masahiro@...>
Acked-by: Gregory CLEMENT <gregory.clement@...>
Acked-by: Thierry Reding <treding@...>
Acked-by: Heiko Stuebner <heiko@...>
Acked-by: Simon Horman <horms+renesas@...>
Acked-by: Tero Kristo <t-kristo@...>
Acked-by: Wei Xu <xuwei5@...>
Acked-by: Liviu Dudau <liviu.dudau@...>
Acked-by: Matthias Brugger <matthias.bgg@...>
Acked-by: Michal Simek <michal.simek@...>
Acked-by: Scott Branden <scott.branden@...>
Acked-by: Kevin Hilman <khilman@...>
Acked-by: Chunyan Zhang <zhang.lyra@...>
Acked-by: Robert Richter <rrichter@...>
Acked-by: Jisheng Zhang <Jisheng.Zhang@...>
Acked-by: Dinh Nguyen <dinguyen@...>
Signed-off-by: Rob Herring <robh@...>
Signed-off-by: Arnd Bergmann <arnd@...>
[fab: dropped changes not related to r8a774a1.dtsi]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
I have put the CIP maintainers in CC, to try and troubleshoot
where the mysterious spaces are coming from, please bear with me...

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 1969649..a77de9e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -61,7 +61,7 @@
#size-cells = <0>;

a57_0: cpu@0 {
- compatible = "arm,cortex-a57", "arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
@@ -71,7 +71,7 @@
};

a57_1: cpu@1 {
- compatible = "arm,cortex-a57", "arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
@@ -81,7 +81,7 @@
};

a53_0: cpu@100 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
@@ -91,7 +91,7 @@
};

a53_1: cpu@101 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
@@ -101,7 +101,7 @@
};

a53_2: cpu@102 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
@@ -111,7 +111,7 @@
};

a53_3: cpu@103 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;


[PATCH Test] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

Nobuhiro Iwamatsu
 

From: Fabrizio Castro <fabrizio.castro@...>

From: Rob Herring <robh@...>

commit 31af04cd60d3162a58213363fd740a2b0cf0a08e upstream.

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@...>
Cc: Mark Rutland <mark.rutland@...>
Cc: Will Deacon <will.deacon@...>
Acked-by: Antoine Tenart <antoine.tenart@...>
Acked-by: Nishanth Menon <nm@...>
Acked-by: Maxime Ripard <maxime.ripard@...>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@...>
Acked-by: Chanho Min <chanho.min@...>
Acked-by: Krzysztof Kozlowski <krzk@...>
Acked-by: Masahiro Yamada <yamada.masahiro@...>
Acked-by: Gregory CLEMENT <gregory.clement@...>
Acked-by: Thierry Reding <treding@...>
Acked-by: Heiko Stuebner <heiko@...>
Acked-by: Simon Horman <horms+renesas@...>
Acked-by: Tero Kristo <t-kristo@...>
Acked-by: Wei Xu <xuwei5@...>
Acked-by: Liviu Dudau <liviu.dudau@...>
Acked-by: Matthias Brugger <matthias.bgg@...>
Acked-by: Michal Simek <michal.simek@...>
Acked-by: Scott Branden <scott.branden@...>
Acked-by: Kevin Hilman <khilman@...>
Acked-by: Chunyan Zhang <zhang.lyra@...>
Acked-by: Robert Richter <rrichter@...>
Acked-by: Jisheng Zhang <Jisheng.Zhang@...>
Acked-by: Dinh Nguyen <dinguyen@...>
Signed-off-by: Rob Herring <robh@...>
Signed-off-by: Arnd Bergmann <arnd@...>
[fab: dropped changes not related to r8a774a1.dtsi]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
I have put the CIP maintainers in CC, to try and troubleshoot
where the mysterious spaces are coming from, please bear with me...

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 1969649..a77de9e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -61,7 +61,7 @@
#size-cells = <0>;

a57_0: cpu@0 {
- compatible = "arm,cortex-a57", "arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
@@ -71,7 +71,7 @@
};

a57_1: cpu@1 {
- compatible = "arm,cortex-a57", "arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
@@ -81,7 +81,7 @@
};

a53_0: cpu@100 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
@@ -91,7 +91,7 @@
};

a53_1: cpu@101 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
@@ -101,7 +101,7 @@
};

a53_2: cpu@102 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
@@ -111,7 +111,7 @@
};

a53_3: cpu@103 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;


[PATCH Test] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

Nobuhiro Iwamatsu
 

From: Fabrizio Castro <fabrizio.castro@...>

From: Rob Herring <robh@...>

commit 31af04cd60d3162a58213363fd740a2b0cf0a08e upstream.

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@...>
Cc: Mark Rutland <mark.rutland@...>
Cc: Will Deacon <will.deacon@...>
Acked-by: Antoine Tenart <antoine.tenart@...>
Acked-by: Nishanth Menon <nm@...>
Acked-by: Maxime Ripard <maxime.ripard@...>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@...>
Acked-by: Chanho Min <chanho.min@...>
Acked-by: Krzysztof Kozlowski <krzk@...>
Acked-by: Masahiro Yamada <yamada.masahiro@...>
Acked-by: Gregory CLEMENT <gregory.clement@...>
Acked-by: Thierry Reding <treding@...>
Acked-by: Heiko Stuebner <heiko@...>
Acked-by: Simon Horman <horms+renesas@...>
Acked-by: Tero Kristo <t-kristo@...>
Acked-by: Wei Xu <xuwei5@...>
Acked-by: Liviu Dudau <liviu.dudau@...>
Acked-by: Matthias Brugger <matthias.bgg@...>
Acked-by: Michal Simek <michal.simek@...>
Acked-by: Scott Branden <scott.branden@...>
Acked-by: Kevin Hilman <khilman@...>
Acked-by: Chunyan Zhang <zhang.lyra@...>
Acked-by: Robert Richter <rrichter@...>
Acked-by: Jisheng Zhang <Jisheng.Zhang@...>
Acked-by: Dinh Nguyen <dinguyen@...>
Signed-off-by: Rob Herring <robh@...>
Signed-off-by: Arnd Bergmann <arnd@...>
[fab: dropped changes not related to r8a774a1.dtsi]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
I have put the CIP maintainers in CC, to try and troubleshoot
where the mysterious spaces are coming from, please bear with me...

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 1969649..a77de9e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -61,7 +61,7 @@
#size-cells = <0>;

a57_0: cpu@0 {
- compatible = "arm,cortex-a57", "arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
@@ -71,7 +71,7 @@
};

a57_1: cpu@1 {
- compatible = "arm,cortex-a57", "arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
@@ -81,7 +81,7 @@
};

a53_0: cpu@100 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
@@ -91,7 +91,7 @@
};

a53_1: cpu@101 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
@@ -101,7 +101,7 @@
};

a53_2: cpu@102 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
@@ -111,7 +111,7 @@
};

a53_3: cpu@103 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;


test1,test2

Yoshitake Kobayashi
 

This is an test email to test subject line. Please ignore.

-- YOSHI


Re: [PATCH resend] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

Nobuhiro Iwamatsu
 

Hi Fabrizio,

Thanks for your test.

-----Original Message-----
From: Fabrizio Castro [mailto:fabrizio.castro@...]
Sent: Monday, September 2, 2019 6:05 PM
To: Pavel Machek <pavel@...>
Cc: Chris Paterson <Chris.Paterson2@...>; Biju Das
<biju.das@...>; iwamatsu nobuhiro(岩松 信洋 ○SWC□OS
T) <nobuhiro1.iwamatsu@...>; cip-dev@...
Subject: RE: [PATCH resend] arm64: dts: Remove inconsistent use of
'arm,armv8' compatible string

Hi Pavel,

Thank you for the feedback!

From: Pavel Machek <pavel@...>
Sent: 02 September 2019 10:01
Subject: Re: [PATCH resend] arm64: dts: Remove inconsistent use of
'arm,armv8' compatible string

On Mon 2019-09-02 08:51:12, Fabrizio Castro wrote:
Hi Pavel,

I have put you in CC (and kept the ML as recipient this time
around), did you receive the patch with or without the space?
I got just one copy of email, and it does not have [cip-dev] marking,
so I assume it is the direct one.

No extra space.
Then it's down to the mailing list, somehow, this same email reached the
ML, with a space...
https://lists.cip-project.org/pipermail/cip-dev/2019-September/00315
8.html
https://patchwork.kernel.org/patch/11126171/
Hmmm. There may be a problem in Mailman.

Who is the person responsible for looking after the ML?
Maybe Kobayashi-san. I just talked to him about this.
Please wait a minute.

Thanks,
Fab
Best regards,
Nobuhiro


[PATCH 4.19.y-cip 22/22] arm64: dts: renesas: r8a774a1: Add dynamic power coefficient

Biju Das <biju.das@...>
 

commit 9e35f49cf7037c3fe3fe4d51aec6d492741cddbe upstream.

Describe the dynamic power coefficient of A57 and A53 CPUs.

Based on work by Gaku Inami <gaku.inami.xw@...> and others.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 6f24ddd..bdf4292 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -135,6 +135,7 @@
power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -162,6 +163,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
#cooling-cells = <2>;
+ dynamic-power-coefficient = <277>;
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <560>;
--
2.7.4


[PATCH 4.19.y-cip 21/22] arm64: dts: renesas: r8a774a1: Create thermal zone to support IPA

Biju Das <biju.das@...>
 

commit 06a928fb5805d1bb80a87c557ac487b916adc50d upstream.

Setup a thermal zone driven by SoC temperature sensor. Create passive trip
points and bind them to CPUFreq cooling device that supports power
extension.

Based on work by Dien Pham <dien.pham.ry@...> for r8a7796 SoC.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 0e755b8..6f24ddd 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -138,6 +138,7 @@
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};

a57_1: cpu@1 {
@@ -150,6 +151,7 @@
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};

a53_0: cpu@100 {
@@ -159,6 +161,7 @@
power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ #cooling-cells = <2>;
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <560>;
@@ -1847,6 +1850,7 @@
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
+ sustainable-power = <3874>;

trips {
sensor1_crit: sensor1-crit {
@@ -1861,6 +1865,7 @@
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
+ sustainable-power = <3874>;

trips {
sensor2_crit: sensor2-crit {
@@ -1869,21 +1874,39 @@
type = "critical";
};
};
-
};

sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
+ sustainable-power = <3874>;

trips {
+ target: trip-point1 {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&a57_0 0 2>;
+ contribution = <1024>;
+ };
+ map1 {
+ trip = <&target>;
+ cooling-device = <&a53_0 0 2>;
+ contribution = <1024>;
+ };
+ };
};
};

--
2.7.4

6441 - 6460 of 9641