Date   

[PATCH 4.19.y-cip 20/22] arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhz

Biju Das <biju.das@...>
 

commit 5f5249497bd7ed65d90cac36c3c3dabcda2903dd upstream.

Set the capacity-dmips-mhz for RZ/G2M(r8a774a1) SoC, that is based on
dhrystone.

Based on work done by Gaku Inami <gaku.inami.xw@...> for
r8a7796 SoC.

The average dhrystone result for 5 iterations is as below:

r8a774a1 SoC (CA57x2 + CA53x4)
CPU max-freq dhrystone
---------------------------------
CA57 1500 MHz 11428571 lps/s
CA53 1200 MHz 5000000 lps/s

From this, CPU capacity-dmips-mhz for CA57 and CA53 are calculated
as follows:

r8a774a1 SoC
CA57 : 1024 / (11428571 / 1500) * (11428571 / 1500) = 1024
CA53 : 1024 / (11428571 / 1500) * ( 5000000 / 1200) = 560

Since each CPUs have different max frequencies, the final CPU
capacities of A53 scaled by the above difference is as below

$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024
1024
448
448
448
448

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 50f3f17..0e755b8 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -137,6 +137,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
+ capacity-dmips-mhz = <1024>;
};

a57_1: cpu@1 {
@@ -148,6 +149,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
+ capacity-dmips-mhz = <1024>;
};

a53_0: cpu@100 {
@@ -159,6 +161,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <560>;
};

a53_1: cpu@101 {
@@ -170,6 +173,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <560>;
};

a53_2: cpu@102 {
@@ -181,6 +185,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <560>;
};

a53_3: cpu@103 {
@@ -192,6 +197,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <560>;
};

L2_CA57: cache-controller-0 {
--
2.7.4


[PATCH 4.19.y-cip 19/22] arm64: dts: renesas: r8a774a1: Add CPU topology on r8a774a1 SoC

Biju Das <biju.das@...>
 

commit 7b996955e514bd3639419c1e725bc3b69c96bd05 upstream.

This patch adds the "cpu-map" into r8a774a1 composed of multi-cluster. This
definition is used to parse the cpu topology.

Based on work by Gaku Inami <gaku.inami.xw@...> for r8a7796 SoC.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index e44c180..50f3f17 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -102,6 +102,32 @@
#address-cells = <1>;
#size-cells = <0>;

+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a57_0>;
+ };
+ core1 {
+ cpu = <&a57_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&a53_0>;
+ };
+ core1 {
+ cpu = <&a53_1>;
+ };
+ core2 {
+ cpu = <&a53_2>;
+ };
+ core3 {
+ cpu = <&a53_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57";
reg = <0x0>;
--
2.7.4


[PATCH 4.19.y-cip 18/22] arm64: dts: renesas: r8a774a1: Add operating points

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit 800037e815b91d8c9ad67906d18129e79a2cfcba upstream.

The RZ/G2M (a.k.a. r8a774a1) comes with two clusters of
processors, similarly to the r8a7796.
The first cluster is made of A57s, the second cluster is
made of A53s.

The operating points for the cluster with the A57s are:

Frequency | Voltage
-----------|---------
500 MHz | 0.82V
1.0 GHz | 0.82V
1.5 GHz | 0.82V

The operating points for the cluster with the A53s are:

Frequency | Voltage
-----------|---------
800 MHz | 0.82V
1.0 GHz | 0.82V
1.2 GHz | 0.82V

This patch adds the definitions for the operating points
to the SoC specific DT.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Signed-off-by: Simon Horman <horms+renesas@...>
Signed-off-by: Biju Das <biju.das@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 48 +++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b6c755b..e44c180 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -56,6 +56,48 @@
clock-frequency = <0>;
};

+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -68,6 +110,7 @@
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};

a57_1: cpu@1 {
@@ -78,6 +121,7 @@
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};

a53_0: cpu@100 {
@@ -88,6 +132,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};

a53_1: cpu@101 {
@@ -98,6 +143,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};

a53_2: cpu@102 {
@@ -108,6 +154,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};

a53_3: cpu@103 {
@@ -118,6 +165,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};

L2_CA57: cache-controller-0 {
--
2.7.4


[PATCH 4.19.y-cip 17/22] thermal: rcar_gen3_thermal: Update temperature conversion method

Biju Das <biju.das@...>
 

From: Yoshihiro Kaneko <ykaneko0929@...>

commit 6a310f8f97bb8bc2e2bb9db6f49a1b8678c8d144 upstream.

Update the formula to calculate temperature:
Currently, current TEMP is calculated as
average of val1 (is calculated by formula 1)
and val2 (is calculated by formula 2). But,
as description in HWM (chapter 10A.3.1.2 Normal Mode.)

If (TEMP_CODE < THCODE2[11:0]) CTEMP value should be val1.
If (TEMP_CODE > THCODE2[11:0]) CTEMP value should be val2.

Signed-off-by: Yoshihiro Kaneko <ykaneko0929@...>
Signed-off-by: Eduardo Valentin <edubezval@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/thermal/rcar_gen3_thermal.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
index ad3908a..c67147e 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -62,6 +62,13 @@

#define TSC_MAX_NUM 3

+/* default THCODE values if FUSEs are missing */
+static const int thcode[TSC_MAX_NUM][3] = {
+ { 3397, 2800, 2221 },
+ { 3393, 2795, 2216 },
+ { 3389, 2805, 2237 },
+};
+
/* Structure for thermal temperature calculation */
struct equation_coefs {
int a1;
@@ -77,6 +84,7 @@ struct rcar_gen3_thermal_tsc {
int low;
int high;
int tj_t;
+ int id; /* thermal channel id */
};

struct rcar_gen3_thermal_priv {
@@ -126,7 +134,7 @@ static inline void rcar_gen3_thermal_write(struct rcar_gen3_thermal_tsc *tsc,
#define TJ_3 -41

static void rcar_gen3_thermal_calc_coefs(struct rcar_gen3_thermal_tsc *tsc,
- int *ptat, int *thcode,
+ int *ptat, const int *thcode,
int ths_tj_1)
{
/* TODO: Find documentation and document constant calculation formula */
@@ -160,15 +168,19 @@ static int rcar_gen3_thermal_round(int temp)
static int rcar_gen3_thermal_get_temp(void *devdata, int *temp)
{
struct rcar_gen3_thermal_tsc *tsc = devdata;
- int mcelsius, val1, val2;
+ int mcelsius, val;
u32 reg;

/* Read register and convert to mili Celsius */
reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK;

- val1 = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1, tsc->coef.a1);
- val2 = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b2, tsc->coef.a2);
- mcelsius = FIXPT_TO_MCELSIUS((val1 + val2) / 2);
+ if (reg <= thcode[tsc->id][1])
+ val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1,
+ tsc->coef.a1);
+ else
+ val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b2,
+ tsc->coef.a2);
+ mcelsius = FIXPT_TO_MCELSIUS(val);

/* Make sure we are inside specifications */
if ((mcelsius < MCELSIUS(-40)) || (mcelsius > MCELSIUS(125)))
@@ -351,11 +363,6 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
/* default values if FUSEs are missing */
/* TODO: Read values from hardware on supported platforms */
int ptat[3] = { 2631, 1509, 435 };
- int thcode[TSC_MAX_NUM][3] = {
- { 3397, 2800, 2221 },
- { 3393, 2795, 2216 },
- { 3389, 2805, 2237 },
- };

priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -410,6 +417,7 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
ret = PTR_ERR(tsc->base);
goto error_unregister;
}
+ tsc->id = i;

priv->tscs[i] = tsc;

--
2.7.4


[PATCH 4.19.y-cip 16/22] thermal: rcar_gen3_thermal: Update calculation formula of IRQTEMP

Biju Das <biju.das@...>
 

From: Yoshihiro Kaneko <ykaneko0929@...>

commit bdc4480a669d476814061b4da6bb006f7048c8e5 upstream.

Update the formula to calculate CTEMP:
Currently, the CTEMP is average of val1 (is calculated by
formula 1) and val2 (is calculated by formula 2). But,
as description in HWM (chapter 10A.3.1.1 Setting of Normal Mode)

If (STEMP < Tj_T) CTEMP value should be val1.
If (STEMP > Tj_T) CTEMP value should be val2.

Signed-off-by: Yoshihiro Kaneko <ykaneko0929@...>
Signed-off-by: Eduardo Valentin <edubezval@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/thermal/rcar_gen3_thermal.c | 33 +++++++++++++++++----------------
1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
index 0830b9e..ad3908a 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -76,6 +76,7 @@ struct rcar_gen3_thermal_tsc {
struct equation_coefs coef;
int low;
int high;
+ int tj_t;
};

struct rcar_gen3_thermal_priv {
@@ -124,28 +125,26 @@ static inline void rcar_gen3_thermal_write(struct rcar_gen3_thermal_tsc *tsc,
/* no idea where these constants come from */
#define TJ_3 -41

-static void rcar_gen3_thermal_calc_coefs(struct equation_coefs *coef,
+static void rcar_gen3_thermal_calc_coefs(struct rcar_gen3_thermal_tsc *tsc,
int *ptat, int *thcode,
int ths_tj_1)
{
- int tj_2;
-
/* TODO: Find documentation and document constant calculation formula */

/*
* Division is not scaled in BSP and if scaled it might overflow
* the dividend (4095 * 4095 << 14 > INT_MAX) so keep it unscaled
*/
- tj_2 = (FIXPT_INT((ptat[1] - ptat[2]) * 157)
- / (ptat[0] - ptat[2])) + FIXPT_INT(TJ_3);
+ tsc->tj_t = (FIXPT_INT((ptat[1] - ptat[2]) * 157)
+ / (ptat[0] - ptat[2])) + FIXPT_INT(TJ_3);

- coef->a1 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[2]),
- tj_2 - FIXPT_INT(TJ_3));
- coef->b1 = FIXPT_INT(thcode[2]) - coef->a1 * TJ_3;
+ tsc->coef.a1 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[2]),
+ tsc->tj_t - FIXPT_INT(TJ_3));
+ tsc->coef.b1 = FIXPT_INT(thcode[2]) - tsc->coef.a1 * TJ_3;

- coef->a2 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[0]),
- tj_2 - FIXPT_INT(ths_tj_1));
- coef->b2 = FIXPT_INT(thcode[0]) - coef->a2 * ths_tj_1;
+ tsc->coef.a2 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[0]),
+ tsc->tj_t - FIXPT_INT(ths_tj_1));
+ tsc->coef.b2 = FIXPT_INT(thcode[0]) - tsc->coef.a2 * ths_tj_1;
}

static int rcar_gen3_thermal_round(int temp)
@@ -184,13 +183,15 @@ static int rcar_gen3_thermal_get_temp(void *devdata, int *temp)
static int rcar_gen3_thermal_mcelsius_to_temp(struct rcar_gen3_thermal_tsc *tsc,
int mcelsius)
{
- int celsius, val1, val2;
+ int celsius, val;

celsius = DIV_ROUND_CLOSEST(mcelsius, 1000);
- val1 = celsius * tsc->coef.a1 + tsc->coef.b1;
- val2 = celsius * tsc->coef.a2 + tsc->coef.b2;
+ if (celsius <= INT_FIXPT(tsc->tj_t))
+ val = celsius * tsc->coef.a1 + tsc->coef.b1;
+ else
+ val = celsius * tsc->coef.a2 + tsc->coef.b2;

- return INT_FIXPT((val1 + val2) / 2);
+ return INT_FIXPT(val);
}

static int rcar_gen3_thermal_set_trips(void *devdata, int low, int high)
@@ -413,7 +414,7 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
priv->tscs[i] = tsc;

priv->thermal_init(tsc);
- rcar_gen3_thermal_calc_coefs(&tsc->coef, ptat, thcode[i],
+ rcar_gen3_thermal_calc_coefs(tsc, ptat, thcode[i],
*rcar_gen3_ths_tj_1);

zone = devm_thermal_zone_of_sensor_register(dev, i, tsc,
--
2.7.4


[PATCH 4.19.y-cip 15/22] thermal: rcar_gen3_thermal: Update value of Tj_1

Biju Das <biju.das@...>
 

From: Yoshihiro Kaneko <ykaneko0929@...>

commit 4eb39f79ef443fa566d36bd43f1f578d5c140305 upstream.

As evaluation of hardware team, temperature calculation formula
of M3-W is difference from all other SoCs as below:
- M3-W: Tj_1: 116 (so Tj_1 - Tj_3 = 157)
- Others: Tj_1: 126 (so Tj_1 - Tj_3 = 167)

Signed-off-by: Yoshihiro Kaneko <ykaneko0929@...>
Signed-off-by: Eduardo Valentin <edubezval@...>
[fab: backported to 4.19.y-cip]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/thermal/rcar_gen3_thermal.c | 36 ++++++++++++++++++++++++++----------
1 file changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
index c9e899a..0830b9e 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -122,11 +122,11 @@ static inline void rcar_gen3_thermal_write(struct rcar_gen3_thermal_tsc *tsc,
#define RCAR3_THERMAL_GRAN 500 /* mili Celsius */

/* no idea where these constants come from */
-#define TJ_1 116
#define TJ_3 -41

static void rcar_gen3_thermal_calc_coefs(struct equation_coefs *coef,
- int *ptat, int *thcode)
+ int *ptat, int *thcode,
+ int ths_tj_1)
{
int tj_2;

@@ -137,15 +137,15 @@ static void rcar_gen3_thermal_calc_coefs(struct equation_coefs *coef,
* the dividend (4095 * 4095 << 14 > INT_MAX) so keep it unscaled
*/
tj_2 = (FIXPT_INT((ptat[1] - ptat[2]) * 157)
- / (ptat[0] - ptat[2])) - FIXPT_INT(41);
+ / (ptat[0] - ptat[2])) + FIXPT_INT(TJ_3);

coef->a1 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[2]),
tj_2 - FIXPT_INT(TJ_3));
coef->b1 = FIXPT_INT(thcode[2]) - coef->a1 * TJ_3;

coef->a2 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[0]),
- tj_2 - FIXPT_INT(TJ_1));
- coef->b2 = FIXPT_INT(thcode[0]) - coef->a2 * TJ_1;
+ tj_2 - FIXPT_INT(ths_tj_1));
+ coef->b2 = FIXPT_INT(thcode[0]) - coef->a2 * ths_tj_1;
}

static int rcar_gen3_thermal_round(int temp)
@@ -294,11 +294,25 @@ static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
usleep_range(1000, 2000);
}

+static const int rcar_gen3_ths_tj_1 = 126;
+static const int rcar_gen3_ths_tj_1_m3_w = 116;
static const struct of_device_id rcar_gen3_thermal_dt_ids[] = {
- { .compatible = "renesas,r8a774a1-thermal", },
- { .compatible = "renesas,r8a7795-thermal", },
- { .compatible = "renesas,r8a7796-thermal", },
- { .compatible = "renesas,r8a77965-thermal", },
+ {
+ .compatible = "renesas,r8a774a1-thermal",
+ .data = &rcar_gen3_ths_tj_1_m3_w,
+ },
+ {
+ .compatible = "renesas,r8a7795-thermal",
+ .data = &rcar_gen3_ths_tj_1,
+ },
+ {
+ .compatible = "renesas,r8a7796-thermal",
+ .data = &rcar_gen3_ths_tj_1_m3_w,
+ },
+ {
+ .compatible = "renesas,r8a77965-thermal",
+ .data = &rcar_gen3_ths_tj_1,
+ },
{},
};
MODULE_DEVICE_TABLE(of, rcar_gen3_thermal_dt_ids);
@@ -327,6 +341,7 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
{
struct rcar_gen3_thermal_priv *priv;
struct device *dev = &pdev->dev;
+ const int *rcar_gen3_ths_tj_1 = of_device_get_match_data(dev);
struct resource *res;
struct thermal_zone_device *zone;
int ret, irq, i;
@@ -398,7 +413,8 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
priv->tscs[i] = tsc;

priv->thermal_init(tsc);
- rcar_gen3_thermal_calc_coefs(&tsc->coef, ptat, thcode[i]);
+ rcar_gen3_thermal_calc_coefs(&tsc->coef, ptat, thcode[i],
+ *rcar_gen3_ths_tj_1);

zone = devm_thermal_zone_of_sensor_register(dev, i, tsc,
&rcar_gen3_tz_of_ops);
--
2.7.4


[PATCH 4.19.y-cip 14/22] thermal: rcar_gen3_thermal: Fix to show correct trip points number

Biju Das <biju.das@...>
 

From: Jiada Wang <jiada_wang@...>

commit e380ea8117ce8c83c5da7063a3587a728132de0b upstream.

Currently after store trip points number in 'ret', it is overwritten
afterwards, this cause incorrect trip point number always be shown in
the debug information after register of each thermal zone.

This patch fix this issue by moving get of trip number to
end of thermal zone registration.

Fixes: 6269e9f790e8d ("thermal: rcar_gen3_thermal: Register hwmon sysfs interface")
Signed-off-by: Jiada Wang <jiada_wang@...>
Signed-off-by: Eduardo Valentin <edubezval@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/thermal/rcar_gen3_thermal.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
index 7969209..c9e899a 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -409,10 +409,6 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
}
tsc->zone = zone;

- ret = of_thermal_get_ntrips(tsc->zone);
- if (ret < 0)
- goto error_unregister;
-
tsc->zone->tzp->no_hwmon = false;
ret = thermal_add_hwmon_sysfs(tsc->zone);
if (ret)
@@ -424,6 +420,10 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
goto error_unregister;
}

+ ret = of_thermal_get_ntrips(tsc->zone);
+ if (ret < 0)
+ goto error_unregister;
+
dev_info(dev, "TSC%d: Loaded %d trip points\n", i, ret);
}

--
2.7.4


[PATCH 4.19.y-cip 13/22] thermal: rcar_gen3_thermal: fix interrupt type

Biju Das <biju.das@...>
 

From: Jiada Wang <jiada_wang@...>

commit 2c0928c9e004589dc9e7672c40a38d6c4ca12701 upstream.

Currently IRQF_SHARED type interrupt line is allocated, but it
is not appropriate, as the interrupt line isn't shared between
different devices, instead IRQF_ONESHOT is the proper type.

By changing interrupt type to IRQF_ONESHOT, now irq handler is
no longer needed, as clear of interrupt status can be done in
threaded interrupt context.

Because IRQF_ONESHOT type interrupt line is kept disabled until
the threaded handler has been run, so there is no need to protect
read/write of REG_GEN3_IRQSTR with lock.

Fixes: 7d4b269776ec6 ("enable hardware interrupts for trip points")
Signed-off-by: Jiada Wang <jiada_wang@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Tested-by: Simon Horman <horms+renesas@...>
Reviewed-by: Daniel Lezcano <daniel.lezcano@...>
Signed-off-by: Eduardo Valentin <edubezval@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/thermal/rcar_gen3_thermal.c | 38 ++++++-------------------------------
1 file changed, 6 insertions(+), 32 deletions(-)

diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
index 7bbfde4..7969209 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -14,7 +14,6 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
-#include <linux/spinlock.h>
#include <linux/sys_soc.h>
#include <linux/thermal.h>

@@ -82,7 +81,6 @@ struct rcar_gen3_thermal_tsc {
struct rcar_gen3_thermal_priv {
struct rcar_gen3_thermal_tsc *tscs[TSC_MAX_NUM];
unsigned int num_tscs;
- spinlock_t lock; /* Protect interrupts on and off */
void (*thermal_init)(struct rcar_gen3_thermal_tsc *tsc);
};

@@ -232,38 +230,16 @@ static irqreturn_t rcar_gen3_thermal_irq(int irq, void *data)
{
struct rcar_gen3_thermal_priv *priv = data;
u32 status;
- int i, ret = IRQ_HANDLED;
+ int i;

- spin_lock(&priv->lock);
for (i = 0; i < priv->num_tscs; i++) {
status = rcar_gen3_thermal_read(priv->tscs[i], REG_GEN3_IRQSTR);
rcar_gen3_thermal_write(priv->tscs[i], REG_GEN3_IRQSTR, 0);
if (status)
- ret = IRQ_WAKE_THREAD;
+ thermal_zone_device_update(priv->tscs[i]->zone,
+ THERMAL_EVENT_UNSPECIFIED);
}

- if (ret == IRQ_WAKE_THREAD)
- rcar_thermal_irq_set(priv, false);
-
- spin_unlock(&priv->lock);
-
- return ret;
-}
-
-static irqreturn_t rcar_gen3_thermal_irq_thread(int irq, void *data)
-{
- struct rcar_gen3_thermal_priv *priv = data;
- unsigned long flags;
- int i;
-
- for (i = 0; i < priv->num_tscs; i++)
- thermal_zone_device_update(priv->tscs[i]->zone,
- THERMAL_EVENT_UNSPECIFIED);
-
- spin_lock_irqsave(&priv->lock, flags);
- rcar_thermal_irq_set(priv, true);
- spin_unlock_irqrestore(&priv->lock, flags);
-
return IRQ_HANDLED;
}

@@ -373,8 +349,6 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
if (soc_device_match(r8a7795es1))
priv->thermal_init = rcar_gen3_thermal_init_r8a7795es1;

- spin_lock_init(&priv->lock);
-
platform_set_drvdata(pdev, priv);

/*
@@ -392,9 +366,9 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
if (!irqname)
return -ENOMEM;

- ret = devm_request_threaded_irq(dev, irq, rcar_gen3_thermal_irq,
- rcar_gen3_thermal_irq_thread,
- IRQF_SHARED, irqname, priv);
+ ret = devm_request_threaded_irq(dev, irq, NULL,
+ rcar_gen3_thermal_irq,
+ IRQF_ONESHOT, irqname, priv);
if (ret)
return ret;
}
--
2.7.4


[PATCH 4.19.y-cip 12/22] thermal: rcar_gen3_thermal: Fix init value of IRQCTL register

Biju Das <biju.das@...>
 

From: Hoan Nguyen An <na-hoan@...>

commit ed1b1ac1425b3d4399553411f305ce12fb3a6c54 upstream.

Fix setting value for IRQCTL register. We are setting the last 6 bits
of (IRQCTL) to be 1 (0x3f), this is only suitable for H3ES1.*, according
to Hardware manual values 1 are "setting prohibited" for Gen3.

Signed-off-by: Hoan Nguyen An <na-hoan@...>
Acked-by: Wolfram Sang <wsa+renesas@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Eduardo Valentin <edubezval@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/thermal/rcar_gen3_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
index 40a442e..7bbfde4 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -307,7 +307,7 @@ static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc)

usleep_range(1000, 2000);

- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0);
rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2);

--
2.7.4


[PATCH 4.19.y-cip 11/22] thermal: rcar_gen3_thermal: Register hwmon sysfs interface

Biju Das <biju.das@...>
 

From: Marek Vasut <marek.vasut+renesas@...>

commit 6269e9f790e8d442b3e1529bf3b3de452dd4ac92 upstream.

Register the hwmon sysfs interface on R-Car Gen3 thermal driver to
align it with Gen2 driver. Use devm_add_action() to unregister the
hwmon interface automatically.

Cc: Eduardo Valentin <edubezval@...>
Cc: Wolfram Sang <wsa+renesas@...>
Cc: linux-renesas-soc@...
To: linux-pm@...
From: Marek Vasut <marek.vasut+renesas@...>
Signed-off-by: Marek Vasut <marek.vasut+renesas@...>
Signed-off-by: Eduardo Valentin <edubezval@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/thermal/rcar_gen3_thermal.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
index 393ed96..40a442e 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -19,6 +19,7 @@
#include <linux/thermal.h>

#include "thermal_core.h"
+#include "thermal_hwmon.h"

/* Register offsets */
#define REG_GEN3_IRQSTR 0x04
@@ -339,6 +340,13 @@ static int rcar_gen3_thermal_remove(struct platform_device *pdev)
return 0;
}

+static void rcar_gen3_hwmon_action(void *data)
+{
+ struct thermal_zone_device *zone = data;
+
+ thermal_remove_hwmon_sysfs(zone);
+}
+
static int rcar_gen3_thermal_probe(struct platform_device *pdev)
{
struct rcar_gen3_thermal_priv *priv;
@@ -431,6 +439,17 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev)
if (ret < 0)
goto error_unregister;

+ tsc->zone->tzp->no_hwmon = false;
+ ret = thermal_add_hwmon_sysfs(tsc->zone);
+ if (ret)
+ goto error_unregister;
+
+ ret = devm_add_action(dev, rcar_gen3_hwmon_action, zone);
+ if (ret) {
+ rcar_gen3_hwmon_action(zone);
+ goto error_unregister;
+ }
+
dev_info(dev, "TSC%d: Loaded %d trip points\n", i, ret);
}

--
2.7.4


[PATCH 4.19.y-cip 10/22] arm64: dts: renesas: r8a774a1: Add TMU device nodes

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit 67e291362a759be998c43cbd35b20ac3fa9add4b upstream.

This patch adds TMU[01234] device tree nodes to the r8a774a1
SoC specific DT.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
Signed-off-by: Biju Das <biju.das@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 65 +++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index f9f40ed..b6c755b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -447,6 +447,71 @@
resets = <&cpg 407>;
};

+ tmu0: timer@e61e0000 {
+ compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
+ reg = <0 0xe61e0000 0 0x30>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc0000 {
+ compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
+ reg = <0 0xe6fc0000 0 0x30>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd0000 {
+ compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
+ reg = <0 0xe6fd0000 0 0x30>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 123>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 123>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe0000 {
+ compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
+ reg = <0 0xe6fe0000 0 0x30>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 122>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 122>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc00000 {
+ compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
+ reg = <0 0xffc00000 0 0x30>;
+ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 121>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 121>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.7.4


[PATCH 4.19.y-cip 09/22] clk: renesas: r8a774a1: Add TMU clock

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit c1324171a9d1771d3610cd13c952b981d52317df upstream.

This patch adds the TMU clocks to the R8A774A1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das@...>
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 76ed7d1..e05bfa2 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -113,6 +113,11 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
};

static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
+ DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
+ DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
+ DEF_MOD("tmu1", 124, R8A774A1_CLK_S3D2),
+ DEF_MOD("tmu0", 125, R8A774A1_CLK_CP),
DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4),
DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4),
--
2.7.4


[PATCH 4.19.y-cip 08/22] arm64: dts: renesas: r8a774a1: Add CMT device nodes

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit aa85b3cac7d87cb28f27c8bf8f1737290879ad57 upstream.

This patch adds the CMT[0123] device tree nodes to the
r8a774a1 SoC specific DT.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
Signed-off-by: Biju Das <biju.das@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 70 +++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 12f28aa..f9f40ed 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -326,6 +326,76 @@
reg = <0 0xe6060000 0 0x50c>;
};

+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a774a1-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a774a1-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a774a1-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a774a1-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a774a1-cpg-mssr";
reg = <0 0xe6150000 0 0x0bb0>;
--
2.7.4


[PATCH 4.19.y-cip 07/22] arm64: dts: renesas: hihope-common: Add RWDT support

Biju Das <biju.das@...>
 

commit 736a291d4f665340dbc9af7cc31f7e9ab2ff9943 upstream.

Enable RWDT and use 60 seconds as default timeout.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index 4cc924d..8e9e94d 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -41,6 +41,11 @@
};
};

+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
--
2.7.4


[PATCH 4.19.y-cip 06/22] watchdog: renesas_wdt: Add a few cycles delay

Biju Das <biju.das@...>
 

From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>

commit b836005b4f95cccdc1f53849a31cac2dc375f4b7 upstream.

According to the hardware manual of R-Car Gen2 and Gen3,
software should wait a few RLCK cycles as following:
- Delay 2 cycles before setting watchdog counter.
- Delay 3 cycles before disabling module clock.

So, this patch adds such delays.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Wolfram Sang <wsa+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Reviewed-by: Guenter Roeck <linux@...>
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/watchdog/renesas_wdt.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index 450e517..2496397 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -10,6 +10,7 @@
*/
#include <linux/bitops.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
@@ -73,6 +74,15 @@ static int rwdt_init_timeout(struct watchdog_device *wdev)
return 0;
}

+static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
+{
+ unsigned int delay;
+
+ delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
+
+ usleep_range(delay, 2 * delay);
+}
+
static int rwdt_start(struct watchdog_device *wdev)
{
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
@@ -83,6 +93,8 @@ static int rwdt_start(struct watchdog_device *wdev)
/* Stop the timer before we modify any register */
val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
rwdt_write(priv, val, RWTCSRA);
+ /* Delay 2 cycles before setting watchdog counter */
+ rwdt_wait_cycles(priv, 2);

rwdt_init_timeout(wdev);
rwdt_write(priv, priv->cks, RWTCSRA);
@@ -101,6 +113,8 @@ static int rwdt_stop(struct watchdog_device *wdev)
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

rwdt_write(priv, priv->cks, RWTCSRA);
+ /* Delay 3 cycles before disabling module clock */
+ rwdt_wait_cycles(priv, 3);
pm_runtime_put(wdev->parent);

return 0;
--
2.7.4


[PATCH 4.19.y-cip 05/22] watchdog: renesas_wdt: Use 'dev' instead of dereferencing it repeatedly

Biju Das <biju.das@...>
 

From: Hoan Nguyen An <na-hoan@...>

commit b7fbd3e55c0f842551445d6dbe3dd92ab155b2e8 upstream.

Add helper variable dev = &pdev->dev

Signed-off-by: Hoan Nguyen An <na-hoan@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Reviewed-by: Guenter Roeck <linux@...>
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
[fab: backported to 4.19.y-cip]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/watchdog/renesas_wdt.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index c6ce244..450e517 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -178,16 +178,17 @@ static inline bool rwdt_blacklisted(struct device *dev) { return false; }

static int rwdt_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
struct rwdt_priv *priv;
struct resource *res;
struct clk *clk;
unsigned long clks_per_sec;
int ret, i;

- if (rwdt_blacklisted(&pdev->dev))
+ if (rwdt_blacklisted(dev))
return -ENODEV;

- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;

@@ -196,16 +197,16 @@ static int rwdt_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);

- clk = devm_clk_get(&pdev->dev, NULL);
+ clk = devm_clk_get(dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);

- pm_runtime_enable(&pdev->dev);
- pm_runtime_get_sync(&pdev->dev);
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
priv->clk_rate = clk_get_rate(clk);
priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) &
RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0;
- pm_runtime_put(&pdev->dev);
+ pm_runtime_put(dev);

if (!priv->clk_rate) {
ret = -ENOENT;
@@ -221,14 +222,14 @@ static int rwdt_probe(struct platform_device *pdev)
}

if (i < 0) {
- dev_err(&pdev->dev, "Can't find suitable clock divider\n");
+ dev_err(dev, "Can't find suitable clock divider\n");
ret = -ERANGE;
goto out_pm_disable;
}

priv->wdev.info = &rwdt_ident;
priv->wdev.ops = &rwdt_ops;
- priv->wdev.parent = &pdev->dev;
+ priv->wdev.parent = dev;
priv->wdev.min_timeout = 1;
priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
@@ -240,9 +241,9 @@ static int rwdt_probe(struct platform_device *pdev)
watchdog_stop_on_unregister(&priv->wdev);

/* This overrides the default timeout only if DT configuration was found */
- ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
+ ret = watchdog_init_timeout(&priv->wdev, 0, dev);
if (ret)
- dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");
+ dev_warn(dev, "Specified timeout value invalid, using default\n");

ret = watchdog_register_device(&priv->wdev);
if (ret < 0)
@@ -251,7 +252,7 @@ static int rwdt_probe(struct platform_device *pdev)
return 0;

out_pm_disable:
- pm_runtime_disable(&pdev->dev);
+ pm_runtime_disable(dev);
return ret;
}

--
2.7.4


[PATCH 4.19.y-cip 04/22] watchdog: renesas_wdt: drop superfluous glob pattern

Biju Das <biju.das@...>
 

From: Wolfram Sang <wsa+renesas@...>

commit e18431264954247f76a8e7aeac3b68421e35e65a upstream.

If we want to match all revisions, it is enough to leave the field
empty.

Signed-off-by: Wolfram Sang <wsa+renesas@...>
Reviewed-by: Guenter Roeck <linux@...>
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/watchdog/renesas_wdt.c | 1 -
1 file changed, 1 deletion(-)

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index a579a23..c6ce244 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -154,7 +154,6 @@ static const struct soc_device_attribute rwdt_quirks_match[] = {
.data = (void *)1, /* needs single CPU */
}, {
.soc_id = "r8a7792",
- .revision = "*",
.data = (void *)0, /* needs SMP disabled */
},
{ /* sentinel */ }
--
2.7.4


[PATCH 4.19.y-cip 03/22] watchdog: renesas_wdt: don't keep timer value during suspend/resume

Biju Das <biju.das@...>
 

From: Wolfram Sang <wsa+renesas@...>

commit 9077123c68074619177c9a8d3adce2527bd94179 upstream.

After discussing this mail thread [1] again, we concluded that giving
userspace enough time to prepare is our favourite option. So, do not
keep the time value when suspended but reset it when resuming.

[1] https://patchwork.kernel.org/patch/10252209/

Signed-off-by: Wolfram Sang <wsa+renesas@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Guenter Roeck <linux@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/watchdog/renesas_wdt.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index 777c5a1..a579a23 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -51,7 +51,6 @@ struct rwdt_priv {
void __iomem *base;
struct watchdog_device wdev;
unsigned long clk_rate;
- u16 time_left;
u8 cks;
};

@@ -271,10 +270,9 @@ static int __maybe_unused rwdt_suspend(struct device *dev)
{
struct rwdt_priv *priv = dev_get_drvdata(dev);

- if (watchdog_active(&priv->wdev)) {
- priv->time_left = readw(priv->base + RWTCNT);
+ if (watchdog_active(&priv->wdev))
rwdt_stop(&priv->wdev);
- }
+
return 0;
}

@@ -282,10 +280,9 @@ static int __maybe_unused rwdt_resume(struct device *dev)
{
struct rwdt_priv *priv = dev_get_drvdata(dev);

- if (watchdog_active(&priv->wdev)) {
+ if (watchdog_active(&priv->wdev))
rwdt_start(&priv->wdev);
- rwdt_write(priv, priv->time_left, RWTCNT);
- }
+
return 0;
}

--
2.7.4


[PATCH 4.19.y-cip 02/22] watchdog: renesas_wdt: Fix typos

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

commit f8cde726739c60109cc4a30b6b5475b5bd5e1d97 upstream.

Do not use "," but ";" to separate instructions.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Guenter Roeck <linux@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
---
drivers/watchdog/renesas_wdt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index 62d9d3e..777c5a1 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -228,8 +228,8 @@ static int rwdt_probe(struct platform_device *pdev)
goto out_pm_disable;
}

- priv->wdev.info = &rwdt_ident,
- priv->wdev.ops = &rwdt_ops,
+ priv->wdev.info = &rwdt_ident;
+ priv->wdev.ops = &rwdt_ops;
priv->wdev.parent = &pdev->dev;
priv->wdev.min_timeout = 1;
priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
--
2.7.4


[PATCH 4.19.y-cip 01/22] watchdog: renesas_wdt: stop when unregistering

Biju Das <biju.das@...>
 

From: Wolfram Sang <wsa+renesas@...>

commit 14de99b44b34dbb9d0f64845b1cbb675e047767e upstream.

We want to go into a sane state when unregistering. Currently, it
happens that the watchdog stops when unbinding because of RuntimePM
stopping the core clock. When rebinding, the core clock gets reactivated
and the watchdog fires even though it hasn't been opened by userspace
yet. Strange scenario, yes, but sane state is much preferred anyhow.

Signed-off-by: Wolfram Sang <wsa+renesas@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Guenter Roeck <linux@...>
Signed-off-by: Guenter Roeck <linux@...>
Signed-off-by: Wim Van Sebroeck <wim@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/watchdog/renesas_wdt.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index d01efd3..62d9d3e 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -239,6 +239,7 @@ static int rwdt_probe(struct platform_device *pdev)
watchdog_set_drvdata(&priv->wdev, priv);
watchdog_set_nowayout(&priv->wdev, nowayout);
watchdog_set_restart_priority(&priv->wdev, 0);
+ watchdog_stop_on_unregister(&priv->wdev);

/* This overrides the default timeout only if DT configuration was found */
ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
--
2.7.4

6461 - 6480 of 9641