Date   

[PATCH 4.19.y-cip 4/5] arm64: dts: renesas: hihope-common: Add pincontrol support to scif2/scif clock

Biju Das <biju.das@...>
 

commit 871c13a443de63c18c26f5ad725da58fc8e19f13 upstream.

This patch adds pincontrol support to scif2/scif clock.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index 5baf532..de206b7 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -24,7 +24,25 @@
clock-frequency = <32768>;
};

+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_a";
+ function = "scif_clk";
+ };
+};
+
&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};

--
2.7.4


[PATCH 4.19.y-cip 3/5] arm64: dts: renesas: Add HiHope RZ/G2M main board support

Biju Das <biju.das@...>
 

commit 438419ebd3f86221390e481f84db61fd7c5aa2b9 upstream.

Basic support for the HiHope RZ/G2M main board:
- Memory,
- Main crystal,
- Serial console

This patch also includes a dtsi common to both HiHope RZ/G2M
and RZ/G2N main boards.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 33 ++++++++++++++++++++++
.../boot/dts/renesas/r8a774a1-hihope-rzg2m.dts | 26 +++++++++++++++++
3 files changed, 60 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/hihope-common.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 1b98e6b..cd986fa 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
new file mode 100644
index 0000000..5baf532
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2[MN] main board common parts
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+/ {
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&scif2 {
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts
new file mode 100644
index 0000000..93ca973
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2M main board
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774a1.dtsi"
+#include "hihope-common.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2M main board based on r8a774a1";
+ compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x80000000>;
+ };
+};
--
2.7.4


[PATCH 4.19.y-cip 2/5] dt-bindings: Add vendor prefix for HopeRun

Biju Das <biju.das@...>
 

commit 9d79b2f1aed4909988ecd8b370c7919856639699 upstream.

Add "Jiangsu HopeRun Software Co., Ltd." to the list of devicetree
vendor prefixes as "hoperun".

Website: http://www.hoperun.com/en

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Reviewed-by: Rob Herring <robh@...>
Signed-off-by: Simon Horman <horms+renesas@...>
Signed-off-by: Biju Das <biju.das@...>
[ Backported to 4.19 ]
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index b77f359..4ec999c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -162,6 +162,7 @@ hit Hitachi Ltd.
hitex Hitex Development Tools
holt Holt Integrated Circuits, Inc.
honeywell Honeywell
+hoperun Jiangsu HopeRun Software Co., Ltd.
hp Hewlett Packard
holtek Holtek Semiconductor, Inc.
hwacom HwaCom Systems Inc.
--
2.7.4


[PATCH 4.19.y-cip 1/5] dt-bindings: arm: renesas: Add HopeRun RZ/G2[M] boards

Biju Das <biju.das@...>
 

commit 70ac79f5d1ef95e61b174e95192b3555a4caef2f upstream.

This patch adds board HiHope RZ/G2M (the main board, powered by
the R8A774A1) and board HiHope RZ/G2 EX (the expansion board
that sits on top of the HiHope RZ/G2M). Both boards are made
by Jiangsu HopeRun Software Co., Ltd. (a.k.a. HopeRun).

Useful links:
http://hihope.org/product/detail/rzg2
https://item.taobao.com/item.htm?spm=a2oq0.12575281.0.0.6bcf1debQpzkRS&ft=t&id=592177498472
http://www.hoperun.com/Cn/news/id/379

We already know that the HiHope RZ/G2 EX will also sit on the
HiHope RZ/G2N, even though the HiHope RZ/G2N doesn't exist just
yet.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Chris Paterson <Chris.Paterson2@...>
Reviewed-by: Rob Herring <robh@...>
Signed-off-by: Simon Horman <horms+renesas@...>
Signed-off-by: Biju Das <biju.das@...>
[ Backported to 4.19 ]
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 1556460..b847173 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -89,6 +89,11 @@ Boards:
compatible = "renesas,h3ulcb", "renesas,r8a7795"
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
+ - HopeRun expansion board for HiHope RZ/G2 platforms
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
+ "renesas,r8a774a1"
+ - HopeRun HiHope RZ/G2M platform
+ compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"
- iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
compatible = "iwave,g23s", "renesas,r8a77470"
- iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
--
2.7.4


[PATCH 4.19.y-cip 0/5] Add HopeRun RZ/G2[M] main/sub boards

Biju Das <biju.das@...>
 

This patch series add support for HopeRun RZ/G2[M] main/sub boards.

This patch series is based on linux-4.19.y-cip and all the patches
in this series are cherry-picked from linux rc tree.

This patch series depend upon
https://patchwork.kernel.org/project/cip-dev/list/?series=166545


Biju Das (5):
dt-bindings: arm: renesas: Add HopeRun RZ/G2[M] boards
dt-bindings: Add vendor prefix for HopeRun
arm64: dts: renesas: Add HiHope RZ/G2M main board support
arm64: dts: renesas: hihope-common: Add pincontrol support to
scif2/scif clock
arm64: dts: renesas: Add HiHope RZ/G2M sub board support

Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 53 +++++++++++++++++++++
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 55 ++++++++++++++++++++++
.../boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts | 15 ++++++
.../boot/dts/renesas/r8a774a1-hihope-rzg2m.dts | 26 ++++++++++
7 files changed, 157 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/hihope-common.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts

--
2.7.4


Re: [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc

Chris Paterson
 

Hello Pavel,

From: Pavel Machek <pavel@...>
Sent: 29 August 2019 23:35

Hi!

Since nothing nasty was spotted during code review and it works ok, I
believe
merging this series could really help us with future development, so
yes
please, go ahead and merge.
Ok, merged, and pushed out.
Our CI is hitting some build errors with the latest v4.19-cip (commit
b11ac993) with the renesas shmobile_defconfig configurations:
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/283063646
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/283063654
Thanks for report. Applying two patches Ben identified did not do the
trick; compelete series did.

Let me know if something is still broken.
Looks okay to me.

Thanks, Chris


Best regards,
                                                              Pavel
--
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

Nobuhiro Iwamatsu
 

Hi,

arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string
It's not that important, but why is there a space between 'arm,' and 'armv8'
in subject?

Original subject does not have space.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=31af04cd60d3162a58213363fd740a2b0cf0a08e

The following patch have similar problem.

soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down, up}() helpers

Best regards,
Nobuhiro

-----Original Message-----
From: cip-dev-bounces@...
[mailto:cip-dev-bounces@...] On Behalf Of Fabrizio
Castro
Sent: Wednesday, August 28, 2019 10:33 PM
To: cip-dev@...
Cc: Biju Das <biju.das@...>
Subject: [cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove
inconsistent use of 'arm, armv8' compatible string

From: Rob Herring <robh@...>

commit 31af04cd60d3162a58213363fd740a2b0cf0a08e upstream.

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@...>
Cc: Mark Rutland <mark.rutland@...>
Cc: Will Deacon <will.deacon@...>
Acked-by: Antoine Tenart <antoine.tenart@...>
Acked-by: Nishanth Menon <nm@...>
Acked-by: Maxime Ripard <maxime.ripard@...>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@...>
Acked-by: Chanho Min <chanho.min@...>
Acked-by: Krzysztof Kozlowski <krzk@...>
Acked-by: Masahiro Yamada <yamada.masahiro@...>
Acked-by: Gregory CLEMENT <gregory.clement@...>
Acked-by: Thierry Reding <treding@...>
Acked-by: Heiko Stuebner <heiko@...>
Acked-by: Simon Horman <horms+renesas@...>
Acked-by: Tero Kristo <t-kristo@...>
Acked-by: Wei Xu <xuwei5@...>
Acked-by: Liviu Dudau <liviu.dudau@...>
Acked-by: Matthias Brugger <matthias.bgg@...>
Acked-by: Michal Simek <michal.simek@...>
Acked-by: Scott Branden <scott.branden@...>
Acked-by: Kevin Hilman <khilman@...>
Acked-by: Chunyan Zhang <zhang.lyra@...>
Acked-by: Robert Richter <rrichter@...>
Acked-by: Jisheng Zhang <Jisheng.Zhang@...>
Acked-by: Dinh Nguyen <dinguyen@...>
Signed-off-by: Rob Herring <robh@...>
Signed-off-by: Arnd Bergmann <arnd@...>
[fab: dropped changes not related to r8a774a1.dtsi]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 1969649..a77de9e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -61,7 +61,7 @@
#size-cells = <0>;

a57_0: cpu@0 {
- compatible = "arm,cortex-a57", "arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
@@ -71,7 +71,7 @@
};

a57_1: cpu@1 {
- compatible = "arm,cortex-a57", "arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
@@ -81,7 +81,7 @@
};

a53_0: cpu@100 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
@@ -91,7 +91,7 @@
};

a53_1: cpu@101 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
@@ -101,7 +101,7 @@
};

a53_2: cpu@102 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
@@ -111,7 +111,7 @@
};

a53_3: cpu@103 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
--
2.7.4

_______________________________________________
cip-dev mailing list
cip-dev@...
https://lists.cip-project.org/mailman/listinfo/cip-dev


Re: [PATCH 4.19.y-cip v2 52/57] arm64: dts: renesas: r8a774a1: Replace power magic numbers

Nobuhiro Iwamatsu
 

Hi,

Fix for VIN (and others?) has been removed from original commit.
Please add this to the commit message.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aeee3d9cb776542f5700425f703fa78c70a1dcd0

Best regards,
Nobuhiro

-----Original Message-----
From: cip-dev-bounces@...
[mailto:cip-dev-bounces@...] On Behalf Of Fabrizio
Castro
Sent: Wednesday, August 28, 2019 10:33 PM
To: cip-dev@...
Cc: Biju Das <biju.das@...>
Subject: [cip-dev] [PATCH 4.19.y-cip v2 52/57] arm64: dts: renesas:
r8a774a1: Replace power magic numbers

commit aeee3d9cb776542f5700425f703fa78c70a1dcd0 upstream.

Now that include/dt-bindings/power/r8a774a1-sysc.h is in Linus'
master branch we can replace power related magic numbers with the
corresponding labels.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 181
+++++++++++++++---------------
1 file changed, 91 insertions(+), 90 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index a4817a0..000b280 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/power/r8a774a1-sysc.h>

/ {
compatible = "renesas,r8a774a1";
@@ -63,7 +64,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
- power-domains = <&sysc 0>;
+ power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE 0>;
@@ -73,7 +74,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>;
device_type = "cpu";
- power-domains = <&sysc 1>;
+ power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE 0>;
@@ -83,7 +84,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x100>;
device_type = "cpu";
- power-domains = <&sysc 5>;
+ power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE 1>;
@@ -93,7 +94,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x101>;
device_type = "cpu";
- power-domains = <&sysc 6>;
+ power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE 1>;
@@ -103,7 +104,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x102>;
device_type = "cpu";
- power-domains = <&sysc 7>;
+ power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE 1>;
@@ -113,7 +114,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x103>;
device_type = "cpu";
- power-domains = <&sysc 8>;
+ power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE 1>;
@@ -121,14 +122,14 @@

L2_CA57: cache-controller-0 {
compatible = "cache";
- power-domains = <&sysc 12>;
+ power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};

L2_CA53: cache-controller-1 {
compatible = "cache";
- power-domains = <&sysc 21>;
+ power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
@@ -195,7 +196,7 @@
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
@@ -211,7 +212,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};

@@ -226,7 +227,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};

@@ -241,7 +242,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};

@@ -256,7 +257,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};

@@ -271,7 +272,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};

@@ -286,7 +287,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};

@@ -301,7 +302,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 906>;
};

@@ -316,7 +317,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 905>;
};

@@ -355,7 +356,7 @@
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <1>;
};
@@ -372,7 +373,7 @@
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161
IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};

@@ -384,7 +385,7 @@
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 931>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>; @@ -401,7
+402,7 @@
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 930>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>; @@ -418,7
+419,7 @@
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 929>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>; @@ -435,7
+436,7 @@
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 928>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
@@ -451,7 +452,7 @@
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 927>;
dmas = <&dmac0 0x99>, <&dmac0 0x98>;
dma-names = "tx", "rx";
@@ -467,7 +468,7 @@
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 919>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
dma-names = "tx", "rx";
@@ -483,7 +484,7 @@
reg = <0 0xe66e8000 0 0x40>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 918>;
dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
dma-names = "tx", "rx";
@@ -500,7 +501,7 @@
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
@@ -520,7 +521,7 @@
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 520>;
status = "disabled";
};
@@ -538,7 +539,7 @@
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
<&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 519>;
status = "disabled";
};
@@ -556,7 +557,7 @@
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 518>;
status = "disabled";
};
@@ -573,7 +574,7 @@
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x37>, <&dmac0 0x36>;
dma-names = "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 517>;
status = "disabled";
};
@@ -590,7 +591,7 @@
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x39>, <&dmac0 0x38>;
dma-names = "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 516>;
status = "disabled";
};
@@ -607,7 +608,7 @@
renesas,buswait = <11>;
phys = <&usb2_phy0>;
phy-names = "usb";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
};
@@ -620,7 +621,7 @@
GIC_SPI 109
IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 330>;
#dma-cells = <1>;
dma-channels = <2>;
@@ -634,7 +635,7 @@
GIC_SPI 110
IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 331>;
#dma-cells = <1>;
dma-channels = <2>;
@@ -647,7 +648,7 @@
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
<&usb_extal_clk>;
clock-names = "usb3-if", "usb3s_clk",
"usb_extal";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 328>;
#phy-cells = <0>;
status = "disabled";
@@ -681,7 +682,7 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
@@ -715,7 +716,7 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
@@ -749,7 +750,7 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
@@ -759,7 +760,7 @@
compatible = "renesas,ipmmu-r8a774a1";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

@@ -767,7 +768,7 @@
compatible = "renesas,ipmmu-r8a774a1";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

@@ -775,7 +776,7 @@
compatible = "renesas,ipmmu-r8a774a1";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

@@ -784,7 +785,7 @@
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197
IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

@@ -792,7 +793,7 @@
compatible = "renesas,ipmmu-r8a774a1";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

@@ -800,7 +801,7 @@
compatible = "renesas,ipmmu-r8a774a1";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

@@ -808,7 +809,7 @@
compatible = "renesas,ipmmu-r8a774a1";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

@@ -816,7 +817,7 @@
compatible = "renesas,ipmmu-r8a774a1";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
- power-domains = <&sysc 14>;
+ power-domains = <&sysc R8A774A1_PD_A3VC>;
#iommu-cells = <1>;
};

@@ -824,7 +825,7 @@
compatible = "renesas,ipmmu-r8a774a1";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

@@ -865,7 +866,7 @@
"ch20", "ch21", "ch22",
"ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
#address-cells = <1>;
@@ -880,7 +881,7 @@
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>, <&can_clk>;
clock-names = "clkp1", "can_clk";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
@@ -892,7 +893,7 @@
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>, <&can_clk>;
clock-names = "clkp1", "can_clk";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
@@ -903,7 +904,7 @@
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
status = "disabled";
};

@@ -913,7 +914,7 @@
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
status = "disabled";
};

@@ -923,7 +924,7 @@
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
status = "disabled";
};

@@ -933,7 +934,7 @@
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
status = "disabled";
};

@@ -943,7 +944,7 @@
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
status = "disabled";
};

@@ -953,7 +954,7 @@
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
status = "disabled";
};

@@ -963,7 +964,7 @@
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
status = "disabled";
};

@@ -979,7 +980,7 @@
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
};
@@ -996,7 +997,7 @@
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
@@ -1010,7 +1011,7 @@
<&cpg CPG_CORE 19>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
@@ -1026,7 +1027,7 @@
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
dma-names = "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
@@ -1042,7 +1043,7 @@
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
dma-names = "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
@@ -1059,7 +1060,7 @@
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
<&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
};
@@ -1073,7 +1074,7 @@
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1089,7 +1090,7 @@
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1104,7 +1105,7 @@
clocks = <&cpg CPG_MOD 209>;
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 209>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1119,7 +1120,7 @@
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
dma-names = "tx", "rx";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 208>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1175,7 +1176,7 @@
"ctu.1", "ctu.0",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c",
"clk_i";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 1005>,
<&cpg 1006>, <&cpg 1007>,
<&cpg 1008>, <&cpg 1009>,
@@ -1361,7 +1362,7 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
@@ -1395,7 +1396,7 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 501>;
clock-names = "fck";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <16>;
@@ -1407,7 +1408,7 @@
reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
@@ -1418,7 +1419,7 @@
reg = <0 0xee020000 0 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
@@ -1430,7 +1431,7 @@
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
@@ -1442,7 +1443,7 @@
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
@@ -1455,7 +1456,7 @@
phys = <&usb2_phy0>;
phy-names = "usb";
companion = <&ohci0>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
@@ -1468,7 +1469,7 @@
phys = <&usb2_phy1>;
phy-names = "usb";
companion = <&ohci1>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
@@ -1479,7 +1480,7 @@
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled";
@@ -1490,7 +1491,7 @@
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>;
clocks = <&cpg CPG_MOD 702>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 702>;
#phy-cells = <0>;
status = "disabled";
@@ -1503,7 +1504,7 @@
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
max-frequency = <200000000>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
@@ -1515,7 +1516,7 @@
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
status = "disabled";
};
@@ -1527,7 +1528,7 @@
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
};
@@ -1539,7 +1540,7 @@
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 311>;
status = "disabled";
};
@@ -1557,7 +1558,7 @@
(GIC_CPU_MASK_SIMPLE(6) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};

@@ -1565,7 +1566,7 @@
compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>;
clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc 14>;
+ power-domains = <&sysc R8A774A1_PD_A3VC>;
resets = <&cpg 615>;
};

@@ -1573,7 +1574,7 @@
compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>;
clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc 14>;
+ power-domains = <&sysc R8A774A1_PD_A3VC>;
resets = <&cpg 607>;
};

@@ -1581,7 +1582,7 @@
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
@@ -1590,7 +1591,7 @@
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
@@ -1599,7 +1600,7 @@
compatible = "renesas,fcpv";
reg = <0 0xfea37000 0 0x200>;
clocks = <&cpg CPG_MOD 601>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 601>;
iommus = <&ipmmu_vi0 10>;
};
@@ -1608,7 +1609,7 @@
compatible = "renesas,fcpv";
reg = <0 0xfe9af000 0 0x200>;
clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc 14>;
+ power-domains = <&sysc R8A774A1_PD_A3VC>;
resets = <&cpg 611>;
iommus = <&ipmmu_vc0 19>;
};
--
2.7.4

_______________________________________________
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Re: [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc

Pavel Machek
 

Hi!

Since nothing nasty was spotted during code review and it works ok, I
believe
merging this series could really help us with future development, so yes
please, go ahead and merge.
Ok, merged, and pushed out.
Our CI is hitting some build errors with the latest v4.19-cip (commit b11ac993) with the renesas shmobile_defconfig configurations:
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/283063646
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/283063654
Thanks for report. Applying two patches Ben identified did not do the
trick; compelete series did.

Let me know if something is still broken.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH/RFC 4.19.y-cip v2 00/51] Fast forward sh-pfc

Pavel Machek
 

Hi!

v1 had build time issues on ARM with shmobile_defconfig, this series
includes the patches to fix those issues (and some cosmetic improvements
while at it).
The troublesome SoC specific pinctrl drivers are not related to the
SoCs looked after by CIP, therefore we would not be testing those
fixes on real HW.
I am not sure this series is worth applying due to the amount of untested
changes, and yet on the other hand it would facilitate future development.
I would like to hear your thoughts about this, Pavel? Chris? Biju?
Ben?
Ok, so 1-41 is already applied. I applied 43 and 44, as that should
fix the build. ...it did not.

I reviewed the rest of patches, and do not see anything obviously
wrong. They would affect dts, and I see value in keeping that
compatible between 4.19 and mainline.

And ... it is "just" 8 patches now, and they won't do damage outside
of shmobile. I applied them, and it fixed the build problem on the
gitlab.

Please take a look and let me know if something is still broken. (We
can still revert whole series).

Best regards,

Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


Re: [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc

Pavel Machek
 

Hi!

Since nothing nasty was spotted during code review and it works ok, I
believe
merging this series could really help us with future development, so yes
please, go ahead and merge.
Ok, merged, and pushed out.
Our CI is hitting some build errors with the latest v4.19-cip (commit b11ac993) with the renesas shmobile_defconfig configurations:
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/283063646
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/283063654

In file included from ./include/linux/kernel.h:15,
from ./include/asm-generic/bug.h:18,
from ./arch/arm/include/asm/bug.h:60,
from ./include/linux/bug.h:5,
from ./include/linux/io.h:23,
from drivers/pinctrl/sh-pfc/pfc-r8a7740.c:21:
./include/linux/build_bug.h:29:45: error: negative width in bit-field '<anonymous>'
#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); }))
^
drivers/pinctrl/sh-pfc/sh_pfc.h:52:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO'
BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
^~~~~~~~~~~~~~~~~
drivers/pinctrl/sh-pfc/sh_pfc.h:54:29: note: in expansion of macro 'SH_PFC_PIN_GROUP_ALIAS'
#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
^~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/sh-pfc/pfc-r8a7740.c:2806:2: note: in expansion of macro 'SH_PFC_PIN_GROUP'
SH_PFC_PIN_GROUP(gether_gmii),
^~~~~~~~~~~~~~~~
[...]
Thank you for reporting this, and I am so glad we have CI in place to spot this things early on now.

I think the safest thing to do here is dropping this series after seeing the build log,
there is clearly more effort needed to keep arm32 and arm64 in check, and backporting
more patches to the sh-pfc driver would still be a pain.

Pavel, do you think you can drop this series?
The failing assertions were added by "pinctrl: sh-pfc: Validate
pins/marks in pin groups at build time". We could revert that one
patch, but it seems to be detecting actual bugs in r8a7740.c, so I
think we should take the fixes for those:

commit 1ebc589a7786f17f97b9e87b44e0fb4d0290d8f8
Author: Geert Uytterhoeven <geert+renesas@...>
Date: Wed Dec 12 10:57:27 2018 +0100

pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii group

commit 96bb2a6ab4eca10e5b6490b3f0738e9f7ec22c2b
Author: Geert Uytterhoeven <geert+renesas@...>
Date: Wed Dec 12 11:00:27 2018 +0100

pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 group
I'd rather apply these two patches than revert the series. If they are
in the new series, I can pick them easily... and we should have the
tree building again.

Ok... I tried that. I pushed the tree now, and will take a look at the
lava.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc

Fabrizio Castro <fabrizio.castro@...>
 

Hi Ben,

Thank you for the feedback!

From: Ben Hutchings <ben.hutchings@...>
Sent: 29 August 2019 14:51
Subject: Re: [cip-dev] [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc

On Thu, 2019-08-29 at 11:04 +0000, Fabrizio Castro wrote:
Hello Chris,

Thank you for your feedback!

From: Chris Paterson <Chris.Paterson2@...>
Sent: 29 August 2019 11:23
Subject: RE: [cip-dev] [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc

Hello Pavel, Fab,

From: cip-dev-bounces@... <cip-dev-bounces@...
project.org> On Behalf Of Fabrizio Castro
Sent: 29 August 2019 10:50

Hi Pavel,

From: Pavel Machek <pavel@...>
Sent: 29 August 2019 10:48
Subject: Re: [cip-dev] [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc

Hi!

they have made good progress upstream with the development of
sh-pfc,
and although the functionality of the drivers hasn't changed much,
the code looks fairly different. This means that backporting patches
to SoC specific driver files will be increasingly hard and error
prone, unless we fast-forward the code base for 4.19.y-cip, hence
this series.
What do you gus think? Comments welcome!
I reviewed the patches... and it is interesting how much magic can be
done with preprocessor.
I thought the same thing!
I do not see anything preventing the merge, but they were marked
[rfc]
so I'm not doing that yet. Let me know if I should.
Since nothing nasty was spotted during code review and it works ok, I
believe
merging this series could really help us with future development, so yes
please, go ahead and merge.
Ok, merged, and pushed out.
Our CI is hitting some build errors with the latest v4.19-cip (commit b11ac993) with the renesas shmobile_defconfig configurations:
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/283063646
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/283063654

In file included from ./include/linux/kernel.h:15,
from ./include/asm-generic/bug.h:18,
from ./arch/arm/include/asm/bug.h:60,
from ./include/linux/bug.h:5,
from ./include/linux/io.h:23,
from drivers/pinctrl/sh-pfc/pfc-r8a7740.c:21:
./include/linux/build_bug.h:29:45: error: negative width in bit-field '<anonymous>'
#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); }))
^
drivers/pinctrl/sh-pfc/sh_pfc.h:52:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO'
BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
^~~~~~~~~~~~~~~~~
drivers/pinctrl/sh-pfc/sh_pfc.h:54:29: note: in expansion of macro 'SH_PFC_PIN_GROUP_ALIAS'
#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
^~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/sh-pfc/pfc-r8a7740.c:2806:2: note: in expansion of macro 'SH_PFC_PIN_GROUP'
SH_PFC_PIN_GROUP(gether_gmii),
^~~~~~~~~~~~~~~~
[...]
Thank you for reporting this, and I am so glad we have CI in place to spot this things early on now.

I think the safest thing to do here is dropping this series after seeing the build log,
there is clearly more effort needed to keep arm32 and arm64 in check, and backporting
more patches to the sh-pfc driver would still be a pain.

Pavel, do you think you can drop this series?
The failing assertions were added by "pinctrl: sh-pfc: Validate
pins/marks in pin groups at build time". We could revert that one
patch, but it seems to be detecting actual bugs in r8a7740.c, so I
think we should take the fixes for those:

commit 1ebc589a7786f17f97b9e87b44e0fb4d0290d8f8
Author: Geert Uytterhoeven <geert+renesas@...>
Date: Wed Dec 12 10:57:27 2018 +0100

pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii group

commit 96bb2a6ab4eca10e5b6490b3f0738e9f7ec22c2b
Author: Geert Uytterhoeven <geert+renesas@...>
Date: Wed Dec 12 11:00:27 2018 +0100

pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 group

Ben.
Thank you for this, I have found problems with 3 SoC specific pinctrl drivers,
I have sent out a v2 for reference, I am not convinced that applying the
series is worth the risk, but I would appreciate your opinion.

Thanks,
Fab


--
Ben Hutchings, Software Developer Codethink Ltd
https://www.codethink.co.uk/ Dale House, 35 Dale Street
Manchester, M1 2HF, United Kingdom


[PATCH/RFC 4.19.y-cip v2 51/51] pinctrl: sh-pfc: sh73a0: Use new macros for non-GPIO pins

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 25491559322e435c47731fd65f0dd9fb88a0b213 upstream.

Update the SH-Mobile AG5 pin control driver to use the new macros for
describing pins without GPIO functionality. This replaces the use of
physical pin numbers on the SH-Mobile AG5 SoC (in 34x34 BGA package) by
symbolic enum values, referring to signal names.

Note that the user-visible names of these pins are still based on pin
numbers instead of signal names, to preserve DT backwards compatibility.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 1adb234..a748af3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -56,6 +56,9 @@
PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)

+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP(A11, "F26", fn)
+
enum {
PINMUX_RESERVED = 0,

@@ -1171,11 +1174,13 @@ static const u16 pinmux_data[] = {
#define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)

-/* Pin numbers for pins without a corresponding GPIO port number are computed
- * from the row and column numbers with a 1000 offset to avoid collisions with
- * GPIO port numbers.
+/*
+ * Pins not associated with a GPIO port.
*/
-#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
+enum {
+ PORT_ASSIGN_LAST(),
+ NOGP_ALL(),
+};

static const struct sh_pfc_pin pinmux_pins[] = {
/* Table 25-1 (I/O and Pull U/D) */
@@ -1450,7 +1455,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
SH73A0_PIN_O(309),

/* Pins not associated with a GPIO port */
- SH_PFC_PIN_NAMED(6, 26, F26),
+ PINMUX_NOGP_ALL(),
};

/* - BSC -------------------------------------------------------------------- */
@@ -1876,7 +1881,7 @@ static const unsigned int keysc_out7_2_mux[] = {
};
static const unsigned int keysc_out8_0_pins[] = {
/* KEYOUT8 */
- PIN_NUMBER(6, 26),
+ PIN_A11,
};
static const unsigned int keysc_out8_0_mux[] = {
KEYOUT8_MARK,
@@ -3086,7 +3091,7 @@ static const unsigned int tpu4_to2_mux[] = {
};
static const unsigned int tpu4_to3_pins[] = {
/* TO */
- PIN_NUMBER(6, 26),
+ PIN_A11,
};
static const unsigned int tpu4_to3_mux[] = {
TPU4TO3_MARK,
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 50/51] pinctrl: sh-pfc: sh73a0: Add missing TO pin to tpu4_to3 group

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 124cde98f856b6206b804acbdec3b7c80f8c3427 upstream.

The tpu4_to3_mux[] array contains the TPU4TO3 pin mark, but the
tpu4_to3_pins[] array lacks the corresponding pin number.

Add the missing pin number, for non-GPIO pin F26.

Fixes: 5da4eb049de803c7 ("sh-pfc: sh73a0: Add TPU pin groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 454825f..1adb234 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3086,6 +3086,7 @@ static const unsigned int tpu4_to2_mux[] = {
};
static const unsigned int tpu4_to3_pins[] = {
/* TO */
+ PIN_NUMBER(6, 26),
};
static const unsigned int tpu4_to3_mux[] = {
TPU4TO3_MARK,
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 49/51] pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 0e6e448bdcf896d001a289a6112a704542d51516 upstream.

There are two pin groups for the FSIC SPDIF signal, but the FSIC pin
group array lists only one, and it refers to a nonexistent group.

Fixes: 2ecd4154c906b7d6 ("sh-pfc: sh73a0: Add FSI pin groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 39b86da..454825f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3366,7 +3366,8 @@ static const char * const fsic_groups[] = {
"fsic_sclk_out",
"fsic_data_in",
"fsic_data_out",
- "fsic_spdif",
+ "fsic_spdif_0",
+ "fsic_spdif_1",
};

static const char * const fsid_groups[] = {
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 48/51] pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit a4b0350047f1b10207e25e72d7cd3f7826e93769 upstream.

The entry for "scifb2_data_c" in the SCIFB2 pin group array contains a
typo, thus the group cannot be selected.

Fixes: 5088451962389924 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 74f8b77..359d055 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -5240,7 +5240,7 @@ static const char * const scifb2_groups[] = {
"scifb2_data_b",
"scifb2_clk_b",
"scifb2_ctrl_b",
- "scifb0_data_c",
+ "scifb2_data_c",
"scifb2_clk_c",
"scifb2_data_d",
};
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 47/51] pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit b8ba194ca5f4ca238b05e1d1579404d4ff3de522 upstream.

The naming of the "b" versions of the VIN1 pin groups is a bit odd, in
that the "_b" appears in the middle of the names, instead of as a
suffix.

Increase consistency with other SoCs by making R-Car M2-W and M2-N, and
RZ/G1M and RZ/G1N, use the recently added optional "version" argument of
the VIN_DATA_PIN_GROUP() macro.

Note that this breaks backwards compatibility with existing DTBs, but
there are no upstream users of the "vin1_b_*" names.

Fixes: 8e32c9671f84acd8 ("pinctrl: sh-pfc: r8a7791: Add VIN pins")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 68 ++++++++++++++++++------------------
1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index f9de61c..74f8b77 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -4321,7 +4321,7 @@ static const unsigned int vin1_clk_pins[] = {
static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
-static const union vin_data vin1_b_data_pins = {
+static const union vin_data vin1_data_b_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
@@ -4340,7 +4340,7 @@ static const union vin_data vin1_b_data_pins = {
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
},
};
-static const union vin_data vin1_b_data_mux = {
+static const union vin_data vin1_data_b_mux = {
.data24 = {
/* B */
VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
@@ -4359,7 +4359,7 @@ static const union vin_data vin1_b_data_mux = {
VI1_R6_B_MARK, VI1_R7_B_MARK,
},
};
-static const unsigned int vin1_b_data18_pins[] = {
+static const unsigned int vin1_data18_b_pins[] = {
/* B */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
@@ -4373,7 +4373,7 @@ static const unsigned int vin1_b_data18_pins[] = {
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
};
-static const unsigned int vin1_b_data18_mux[] = {
+static const unsigned int vin1_data18_b_mux[] = {
/* B */
VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
@@ -4387,30 +4387,30 @@ static const unsigned int vin1_b_data18_mux[] = {
VI1_R4_B_MARK, VI1_R5_B_MARK,
VI1_R6_B_MARK, VI1_R7_B_MARK,
};
-static const unsigned int vin1_b_sync_pins[] = {
+static const unsigned int vin1_sync_b_pins[] = {
RCAR_GP_PIN(3, 17), /* HSYNC */
RCAR_GP_PIN(3, 18), /* VSYNC */
};
-static const unsigned int vin1_b_sync_mux[] = {
+static const unsigned int vin1_sync_b_mux[] = {
VI1_HSYNC_N_B_MARK,
VI1_VSYNC_N_B_MARK,
};
-static const unsigned int vin1_b_field_pins[] = {
+static const unsigned int vin1_field_b_pins[] = {
RCAR_GP_PIN(3, 20),
};
-static const unsigned int vin1_b_field_mux[] = {
+static const unsigned int vin1_field_b_mux[] = {
VI1_FIELD_B_MARK,
};
-static const unsigned int vin1_b_clkenb_pins[] = {
+static const unsigned int vin1_clkenb_b_pins[] = {
RCAR_GP_PIN(3, 19),
};
-static const unsigned int vin1_b_clkenb_mux[] = {
+static const unsigned int vin1_clkenb_b_mux[] = {
VI1_CLKENB_B_MARK,
};
-static const unsigned int vin1_b_clk_pins[] = {
+static const unsigned int vin1_clk_b_pins[] = {
RCAR_GP_PIN(3, 16),
};
-static const unsigned int vin1_b_clk_mux[] = {
+static const unsigned int vin1_clk_b_mux[] = {
VI1_CLK_B_MARK,
};
/* - VIN2 ----------------------------------------------------------------- */
@@ -4788,17 +4788,17 @@ static const struct {
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
SH_PFC_PIN_GROUP(vin1_clk),
- VIN_DATA_PIN_GROUP(vin1_b_data, 24),
- VIN_DATA_PIN_GROUP(vin1_b_data, 20),
- SH_PFC_PIN_GROUP(vin1_b_data18),
- VIN_DATA_PIN_GROUP(vin1_b_data, 16),
- VIN_DATA_PIN_GROUP(vin1_b_data, 12),
- VIN_DATA_PIN_GROUP(vin1_b_data, 10),
- VIN_DATA_PIN_GROUP(vin1_b_data, 8),
- SH_PFC_PIN_GROUP(vin1_b_sync),
- SH_PFC_PIN_GROUP(vin1_b_field),
- SH_PFC_PIN_GROUP(vin1_b_clkenb),
- SH_PFC_PIN_GROUP(vin1_b_clk),
+ VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
+ SH_PFC_PIN_GROUP(vin1_data18_b),
+ VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
+ SH_PFC_PIN_GROUP(vin1_sync_b),
+ SH_PFC_PIN_GROUP(vin1_field_b),
+ SH_PFC_PIN_GROUP(vin1_clkenb_b),
+ SH_PFC_PIN_GROUP(vin1_clk_b),
SH_PFC_PIN_GROUP(vin2_data8),
SH_PFC_PIN_GROUP(vin2_sync),
SH_PFC_PIN_GROUP(vin2_field),
@@ -5339,17 +5339,17 @@ static const char * const vin1_groups[] = {
"vin1_field",
"vin1_clkenb",
"vin1_clk",
- "vin1_b_data24",
- "vin1_b_data20",
- "vin1_b_data18",
- "vin1_b_data16",
- "vin1_b_data12",
- "vin1_b_data10",
- "vin1_b_data8",
- "vin1_b_sync",
- "vin1_b_field",
- "vin1_b_clkenb",
- "vin1_b_clk",
+ "vin1_data24_b",
+ "vin1_data20_b",
+ "vin1_data18_b",
+ "vin1_data16_b",
+ "vin1_data12_b",
+ "vin1_data10_b",
+ "vin1_data8_b",
+ "vin1_sync_b",
+ "vin1_field_b",
+ "vin1_clkenb_b",
+ "vin1_clk_b",
};

static const char * const vin2_groups[] = {
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 46/51] pinctrl: sh-pfc: r8a7791: Remove bogus marks from vin1_b_data18 group

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 0d6256cb880166a4111bebce35790019e56b6e1b upstream.

The vin1_b_data18_mux[] arrays contains pin marks for the 2 LSB bits of
the color components. The vin1_b_data18_pins[] array rightfully does
not include the corresponding pin numbers, as RGB18 is subset of RGB24,
containing only the 6 MSB bits of each component.

Fixes: 8e32c9671f84acd8 ("pinctrl: sh-pfc: r8a7791: Add VIN pins")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 3 ---
1 file changed, 3 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index dea3dda..f9de61c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -4375,17 +4375,14 @@ static const unsigned int vin1_b_data18_pins[] = {
};
static const unsigned int vin1_b_data18_mux[] = {
/* B */
- VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
/* G */
- VI1_G0_B_MARK, VI1_G1_B_MARK,
VI1_G2_B_MARK, VI1_G3_B_MARK,
VI1_G4_B_MARK, VI1_G5_B_MARK,
VI1_G6_B_MARK, VI1_G7_B_MARK,
/* R */
- VI1_R0_B_MARK, VI1_R1_B_MARK,
VI1_R2_B_MARK, VI1_R3_B_MARK,
VI1_R4_B_MARK, VI1_R5_B_MARK,
VI1_R6_B_MARK, VI1_R7_B_MARK,
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 45/51] pinctrl: sh-pfc: r8a7791: Remove bogus ctrl marks from qspi_data4_b group

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 884fa25fb6e5e63ab970d612a628313bb68f37cc upstream.

The qspi_data4_b_mux[] array contains pin marks for the clock and chip
select pins. The qspi_data4_b_pins[] array rightfully does not contain
the corresponding pin numbers, as the control pins are provided by a
separate group (qspi_ctrl_b).

Fixes: 2d0c386f135e4186 ("pinctrl: sh-pfc: r8a7791: Add QSPI pin groups")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index c4ffb40..dea3dda 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -3221,8 +3221,7 @@ static const unsigned int qspi_data4_b_pins[] = {
RCAR_GP_PIN(6, 4),
};
static const unsigned int qspi_data4_b_mux[] = {
- SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
- IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
+ MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 44/51] pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 group

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 96bb2a6ab4eca10e5b6490b3f0738e9f7ec22c2b upstream.

The lcd0_data24_1_pins[] array contains the LCD0 D1[2-5] pin numbers,
but the lcd0_data24_1_mux[] array lacks the corresponding pin marks.

Fixes: 06c7dd866da70f6c ("sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 5903686..111f06d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2154,6 +2154,7 @@ static const unsigned int lcd0_data24_1_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
--
2.7.4

6501 - 6520 of 9641