Date   

[PATCH/RFC 4.19.y-cip v2 43/51] pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii group

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 1ebc589a7786f17f97b9e87b44e0fb4d0290d8f8 upstream.

The gether_gmii_mux[] array contains the REF125CK pin mark, but the
gether_gmii_pins[] array lacks the corresponding pin number.

Fixes: bae11d30d0cafdc5 ("sh-pfc: r8a7740: Add GETHER pin groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index c07fdad..5903686 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1982,7 +1982,7 @@ static const unsigned int gether_gmii_pins[] = {
*/
185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
- 205, 163, 206, 207,
+ 205, 163, 206, 207, 158,
};
static const unsigned int gether_gmii_mux[] = {
ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 42/51] pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2, PHYS}()

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 341fe38975211e73c4b1e9b44d5ccbdf7960466b upstream.

The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and
will conflict with generic macros that are to be added.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 6 ------
1 file changed, 6 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index b3e65dd..621f50f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -472,12 +472,6 @@ enum {
#undef FM
};

-#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
- PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
-
-#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
- PINMUX_DATA(fn##_MARK, FN_##msel)
-
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),

--
2.7.4


[PATCH/RFC 4.19.y-cip v2 41/51] pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data

Fabrizio Castro <fabrizio.castro@...>
 

From: Ulrich Hecht <uli+renesas@...>

commit f05603fa6aa30430f444620344a2f75adeeddbd2 upstream.

Pin data for I2C controllers 0, 3 and 5 is properly defined already.

Signed-off-by: Ulrich Hecht <uli+renesas@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 5 -----
1 file changed, 5 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 797f919..9d2c963 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1545,11 +1545,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),

- /* I2C */
- PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
-
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 40/51] pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pins

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 168e18fd6cac03279ab728d78b1b2d04c8262973 upstream.

Update the R-Car M3-W pin control driver to use the new macros for
describing pins without GPIO functionality. This replaces the use of
physical pin numbers on the R-Car M3-W SiP (in 39x39 BGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 307 +++++++++++++++++------------------
1 file changed, 151 insertions(+), 156 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 169d8c0..797f919 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -35,6 +35,51 @@
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
+
+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@@ -1518,66 +1563,16 @@ static const u16 pinmux_data[] = {
};

/*
- * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
- * Physical layout rows: A - AW, cols: 1 - 39.
+ * Pins not associated with a GPIO port.
*/
-#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
-#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
-#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+enum {
+ GP_ASSIGN_LAST(),
+ NOGP_ALL(),
+};

static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
-
- /*
- * Pins not associated with a GPIO port.
- *
- * The pin positions are different between different r8a7796
- * packages, all that is needed for the pfc driver is a unique
- * number for each pin. To this end use the pin layout from
- * R-Car M3SiP to calculate a unique number for each pin.
- */
- SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
+ PINMUX_NOGP_ALL(),
};

/* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -1726,7 +1721,7 @@ static const unsigned int avb_phy_int_mux[] = {
};
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
- RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
+ RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
@@ -1739,11 +1734,11 @@ static const unsigned int avb_mii_pins[] = {
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
- PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
- PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
- PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
- PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
- PIN_NUMBER('A', 12),
+ PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
+ PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
+ PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
+ PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
+ PIN_AVB_TXCREFCLK,

};
static const unsigned int avb_mii_mux[] = {
@@ -5637,44 +5632,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {

static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
- { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
- { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
- { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
- { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
- { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
- { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
- { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
- { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
+ { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
+ { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
+ { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
+ { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
+ { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
+ { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
+ { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
+ { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
- { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
- { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
- { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
- { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
- { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
- { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
- { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
- { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
+ { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
+ { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
+ { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
+ { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
+ { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
+ { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
+ { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
+ { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
- { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
- { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
- { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
- { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
- { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
- { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
- { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
- { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
+ { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
+ { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
+ { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
+ { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
+ { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
+ { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
+ { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
+ { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
- { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
- { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
- { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
- { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
- { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
- { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
- { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
- { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
+ { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
+ { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
+ { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
+ { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
+ { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
+ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
+ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
+ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@@ -5728,7 +5723,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
- { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
+ { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@@ -5747,29 +5742,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
- { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
- { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
- { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
- { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
- { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
- { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
- { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
+ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
+ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
+ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
+ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
+ { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
+ { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
- { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
- { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
- { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
+ { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
+ { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
+ { PIN_TMS, 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
- { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
- { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
- { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
- { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
- { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
- { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
- { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
- { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
+ { PIN_TDO, 28, 2 }, /* TDO */
+ { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
+ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
+ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
+ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
+ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
+ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
+ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@@ -5838,7 +5833,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
- { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
+ { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@@ -5911,35 +5906,35 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc

static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
- [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
- [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
- [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
- [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
- [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
- [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
- [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
- [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
- [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
- [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
- [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
- [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
- [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
- [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
- [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
- [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
- [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
- [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
- [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
- [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
- [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
- [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
- [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
- [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
- [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
- [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
- [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
- [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
- [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
+ [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
+ [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
+ [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
+ [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
+ [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
+ [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
+ [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
+ [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
+ [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
+ [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
+ [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
+ [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
+ [12] = PIN_RPC_INT_N, /* RPC_INT# */
+ [13] = PIN_RPC_WP_N, /* RPC_WP# */
+ [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
+ [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
+ [16] = PIN_AVB_RXC, /* AVB_RXC */
+ [17] = PIN_AVB_RD0, /* AVB_RD0 */
+ [18] = PIN_AVB_RD1, /* AVB_RD1 */
+ [19] = PIN_AVB_RD2, /* AVB_RD2 */
+ [20] = PIN_AVB_RD3, /* AVB_RD3 */
+ [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
+ [22] = PIN_AVB_TXC, /* AVB_TXC */
+ [23] = PIN_AVB_TD0, /* AVB_TD0 */
+ [24] = PIN_AVB_TD1, /* AVB_TD1 */
+ [25] = PIN_AVB_TD2, /* AVB_TD2 */
+ [26] = PIN_AVB_TD3, /* AVB_TD3 */
+ [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
+ [28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@@ -5988,7 +5983,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
- [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
+ [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
@@ -6009,20 +6004,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
- [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
- [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
+ [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
+ [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
- [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
+ [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
[ 1] = SH_PFC_PIN_NONE,
- [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
- [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
- [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
- [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
- [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
- [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
+ [ 2] = PIN_FSCLKST, /* FSCLKST */
+ [ 3] = PIN_EXTALR, /* EXTALR*/
+ [ 4] = PIN_TRST_N, /* TRST# */
+ [ 5] = PIN_TCK, /* TCK */
+ [ 6] = PIN_TMS, /* TMS */
+ [ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
- [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
+ [ 9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@@ -6087,7 +6082,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
- [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
+ [ 6] = PIN_MLB_REF, /* MLB_REF */
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 39/51] pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functions

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 32ba9f222edb92278ec8eadfc6100c7922dc2ad7 upstream.

Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-W and RZ/G2M SoCs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 46 ++++++++++++++++++++++++++++++++++--
1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 93e6bb4..169d8c0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -3896,6 +3896,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};

+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -4115,7 +4145,7 @@ static const unsigned int vin5_clk_mux[] = {
};

static const struct {
- struct sh_pfc_pin_group common[312];
+ struct sh_pfc_pin_group common[316];
struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
@@ -4402,6 +4432,10 @@ static const struct {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
@@ -4923,6 +4957,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk2_b",
};

+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
static const char * const usb0_groups[] = {
"usb0",
};
@@ -4968,7 +5009,7 @@ static const char * const vin5_groups[] = {
};

static const struct {
- struct sh_pfc_function common[49];
+ struct sh_pfc_function common[50];
struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
@@ -5016,6 +5057,7 @@ static const struct {
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
+ SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 38/51] pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pins

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 7ad549ffcbd78f838441ee35fefe713b8a35daa7 upstream.

Update the R-Car E3 pin control driver to use the new macros for
describing pins without GPIO functionality. This replaces the use of
physical pin numbers on the R-Car E3 SoC (in 25x25 FCBGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 87 +++++++++++++++++------------------
1 file changed, 41 insertions(+), 46 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 1055ab9..2dfb8d9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -40,6 +40,25 @@
PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
+
+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
+
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@@ -1276,40 +1295,16 @@ static const u16 pinmux_data[] = {
};

/*
- * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
- * Physical layout rows: A - AE, cols: 1 - 25.
+ * Pins not associated with a GPIO port.
*/
-#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
-#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
-#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+enum {
+ GP_ASSIGN_LAST(),
+ NOGP_ALL(),
+};

static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
-
- /*
- * Pins not associated with a GPIO port.
- *
- * The pin positions are different between different R8A77990
- * packages, all that is needed for the pfc driver is a unique
- * number for each pin. To this end use the pin layout from
- * R8A77990 to calculate a unique number for each pin.
- */
- SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
+ PINMUX_NOGP_ALL(),
};

/* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -5024,15 +5019,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[0] = RCAR_GP_PIN(2, 23), /* RD# */
[1] = RCAR_GP_PIN(2, 22), /* BS# */
[2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
- [3] = PIN_NUMBER('P', 5), /* AVB_MDC */
- [4] = PIN_NUMBER('P', 4), /* AVB_MDIO */
+ [3] = PIN_AVB_MDC, /* AVB_MDC */
+ [4] = PIN_AVB_MDIO, /* AVB_MDIO */
[5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
- [6] = PIN_NUMBER('N', 6), /* AVB_TD3 */
- [7] = PIN_NUMBER('N', 5), /* AVB_TD2 */
- [8] = PIN_NUMBER('N', 3), /* AVB_TD1 */
- [9] = PIN_NUMBER('N', 2), /* AVB_TD0 */
- [10] = PIN_NUMBER('N', 1), /* AVB_TXC */
- [11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */
+ [6] = PIN_AVB_TD3, /* AVB_TD3 */
+ [7] = PIN_AVB_TD2, /* AVB_TD2 */
+ [8] = PIN_AVB_TD1, /* AVB_TD1 */
+ [9] = PIN_AVB_TD0, /* AVB_TD0 */
+ [10] = PIN_AVB_TXC, /* AVB_TXC */
+ [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
[13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
[14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
@@ -5091,12 +5086,12 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
- [2] = PIN_NUMBER('H', 1), /* ASEBRK */
+ [2] = PIN_ASEBRK, /* ASEBRK */
[3] = SH_PFC_PIN_NONE,
- [4] = PIN_NUMBER('G', 2), /* TDI */
- [5] = PIN_NUMBER('F', 3), /* TMS */
- [6] = PIN_NUMBER('F', 4), /* TCK */
- [7] = PIN_NUMBER('F', 1), /* TRST# */
+ [4] = PIN_TDI, /* TDI */
+ [5] = PIN_TMS, /* TMS */
+ [6] = PIN_TCK, /* TCK */
+ [7] = PIN_TRST_N, /* TRST# */
[8] = SH_PFC_PIN_NONE,
[9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
@@ -5104,12 +5099,12 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
- [15] = PIN_NUMBER('G', 3), /* FSCLKST# */
+ [15] = PIN_FSCLKST_N, /* FSCLKST# */
[16] = RCAR_GP_PIN(0, 17), /* SDA4 */
[17] = RCAR_GP_PIN(0, 16), /* SCL4 */
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
- [20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */
+ [20] = PIN_PRESETOUT_N, /* PRESETOUT# */
[21] = RCAR_GP_PIN(0, 15), /* D15 */
[22] = RCAR_GP_PIN(0, 14), /* D14 */
[23] = RCAR_GP_PIN(0, 13), /* D13 */
@@ -5173,7 +5168,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
[14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
- [16] = PIN_NUMBER('T', 21), /* MLB_REF */
+ [16] = PIN_MLB_REF, /* MLB_REF */
[17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
[18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
[19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 37/51] pinctrl: sh-pfc: Move PIN_NONE to shared header file

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 4d1816cd6724dccc8e918f7181d2bd6a6ffb31b5 upstream.

Several drivers have identical definitions for PIN_NONE.
Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h,
and convert all drivers over to use it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 76 +++++++++++++--------------
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 53 ++++++++++---------
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 53 ++++++++++---------
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 55 ++++++++++----------
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 55 ++++++++++----------
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 89 ++++++++++++++++----------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +
7 files changed, 189 insertions(+), 194 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 22700cd..82647d3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -2929,8 +2929,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};

-#define PIN_NONE U16_MAX
-
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 6), /* A0 */
@@ -2977,28 +2975,28 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */
[ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */
[ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */
- [10] = PIN_NONE,
- [11] = PIN_NONE,
- [12] = PIN_NONE,
- [13] = PIN_NONE,
- [14] = PIN_NONE,
- [15] = PIN_NONE,
- [16] = PIN_NONE,
- [17] = PIN_NONE,
- [18] = PIN_NONE,
- [19] = PIN_NONE,
- [20] = PIN_NONE,
- [21] = PIN_NONE,
- [22] = PIN_NONE,
- [23] = PIN_NONE,
- [24] = PIN_NONE,
- [25] = PIN_NONE,
- [26] = PIN_NONE,
- [27] = PIN_NONE,
- [28] = PIN_NONE,
- [29] = PIN_NONE,
- [30] = PIN_NONE,
- [31] = PIN_NONE,
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
+ [15] = SH_PFC_PIN_NONE,
+ [16] = SH_PFC_PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */
@@ -3120,21 +3118,21 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */
[15] = RCAR_GP_PIN(4, 25), /* AVS1 */
[16] = RCAR_GP_PIN(4, 26), /* AVS2 */
- [17] = PIN_NONE,
- [18] = PIN_NONE,
- [19] = PIN_NONE,
- [20] = PIN_NONE,
- [21] = PIN_NONE,
- [22] = PIN_NONE,
- [23] = PIN_NONE,
- [24] = PIN_NONE,
- [25] = PIN_NONE,
- [26] = PIN_NONE,
- [27] = PIN_NONE,
- [28] = PIN_NONE,
- [29] = PIN_NONE,
- [30] = PIN_NONE,
- [31] = PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index c77db750..d8404ca 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -1447,7 +1447,6 @@ static const u16 pinmux_data[] = {
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
-#define PIN_NONE U16_MAX

static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
@@ -5604,7 +5603,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
- [ 8] = PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
@@ -5705,31 +5704,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
[ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
- [ 7] = PIN_NONE,
- [ 8] = PIN_NONE,
- [ 9] = PIN_NONE,
- [10] = PIN_NONE,
- [11] = PIN_NONE,
- [12] = PIN_NONE,
- [13] = PIN_NONE,
- [14] = PIN_NONE,
- [15] = PIN_NONE,
- [16] = PIN_NONE,
- [17] = PIN_NONE,
- [18] = PIN_NONE,
- [19] = PIN_NONE,
- [20] = PIN_NONE,
- [21] = PIN_NONE,
- [22] = PIN_NONE,
- [23] = PIN_NONE,
- [24] = PIN_NONE,
- [25] = PIN_NONE,
- [26] = PIN_NONE,
- [27] = PIN_NONE,
- [28] = PIN_NONE,
- [29] = PIN_NONE,
- [30] = PIN_NONE,
- [31] = PIN_NONE,
+ [ 7] = SH_PFC_PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
+ [ 9] = SH_PFC_PIN_NONE,
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
+ [15] = SH_PFC_PIN_NONE,
+ [16] = SH_PFC_PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 0da9083..68c55ec 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1508,7 +1508,6 @@ static const u16 pinmux_data[] = {
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
-#define PIN_NONE U16_MAX

static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
@@ -5992,7 +5991,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
- [ 8] = PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
@@ -6093,31 +6092,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
[ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
- [ 7] = PIN_NONE,
- [ 8] = PIN_NONE,
- [ 9] = PIN_NONE,
- [10] = PIN_NONE,
- [11] = PIN_NONE,
- [12] = PIN_NONE,
- [13] = PIN_NONE,
- [14] = PIN_NONE,
- [15] = PIN_NONE,
- [16] = PIN_NONE,
- [17] = PIN_NONE,
- [18] = PIN_NONE,
- [19] = PIN_NONE,
- [20] = PIN_NONE,
- [21] = PIN_NONE,
- [22] = PIN_NONE,
- [23] = PIN_NONE,
- [24] = PIN_NONE,
- [25] = PIN_NONE,
- [26] = PIN_NONE,
- [27] = PIN_NONE,
- [28] = PIN_NONE,
- [29] = PIN_NONE,
- [30] = PIN_NONE,
- [31] = PIN_NONE,
+ [ 7] = SH_PFC_PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
+ [ 9] = SH_PFC_PIN_NONE,
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
+ [15] = SH_PFC_PIN_NONE,
+ [16] = SH_PFC_PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 50af7a1..93e6bb4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1524,7 +1524,6 @@ static const u16 pinmux_data[] = {
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
-#define PIN_NONE U16_MAX

static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
@@ -5973,14 +5972,14 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
- [ 1] = PIN_NONE,
+ [ 1] = SH_PFC_PIN_NONE,
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
- [ 8] = PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
@@ -6081,31 +6080,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
- [ 7] = PIN_NONE,
- [ 8] = PIN_NONE,
- [ 9] = PIN_NONE,
- [10] = PIN_NONE,
- [11] = PIN_NONE,
- [12] = PIN_NONE,
- [13] = PIN_NONE,
- [14] = PIN_NONE,
- [15] = PIN_NONE,
- [16] = PIN_NONE,
- [17] = PIN_NONE,
- [18] = PIN_NONE,
- [19] = PIN_NONE,
- [20] = PIN_NONE,
- [21] = PIN_NONE,
- [22] = PIN_NONE,
- [23] = PIN_NONE,
- [24] = PIN_NONE,
- [25] = PIN_NONE,
- [26] = PIN_NONE,
- [27] = PIN_NONE,
- [28] = PIN_NONE,
- [29] = PIN_NONE,
- [30] = PIN_NONE,
- [31] = PIN_NONE,
+ [ 7] = SH_PFC_PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
+ [ 9] = SH_PFC_PIN_NONE,
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
+ [15] = SH_PFC_PIN_NONE,
+ [16] = SH_PFC_PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index b05a21a..96d45cb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1516,7 +1516,6 @@ static const u16 pinmux_data[] = {
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
-#define PIN_NONE U16_MAX

static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
@@ -4953,14 +4952,14 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
- [ 1] = PIN_NONE,
+ [ 1] = SH_PFC_PIN_NONE,
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
- [ 8] = PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
@@ -5061,31 +5060,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
- [ 7] = PIN_NONE,
- [ 8] = PIN_NONE,
- [ 9] = PIN_NONE,
- [10] = PIN_NONE,
- [11] = PIN_NONE,
- [12] = PIN_NONE,
- [13] = PIN_NONE,
- [14] = PIN_NONE,
- [15] = PIN_NONE,
- [16] = PIN_NONE,
- [17] = PIN_NONE,
- [18] = PIN_NONE,
- [19] = PIN_NONE,
- [20] = PIN_NONE,
- [21] = PIN_NONE,
- [22] = PIN_NONE,
- [23] = PIN_NONE,
- [24] = PIN_NONE,
- [25] = PIN_NONE,
- [26] = PIN_NONE,
- [27] = PIN_NONE,
- [28] = PIN_NONE,
- [29] = PIN_NONE,
- [30] = PIN_NONE,
- [31] = PIN_NONE,
+ [ 7] = SH_PFC_PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
+ [ 9] = SH_PFC_PIN_NONE,
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
+ [15] = SH_PFC_PIN_NONE,
+ [16] = SH_PFC_PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 4db337a..1055ab9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1282,7 +1282,6 @@ static const u16 pinmux_data[] = {
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
-#define PIN_NONE U16_MAX

static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
@@ -5084,8 +5083,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(1, 2), /* A2 */
[26] = RCAR_GP_PIN(1, 1), /* A1 */
[27] = RCAR_GP_PIN(1, 0), /* A0 */
- [28] = PIN_NONE,
- [29] = PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
[30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
[31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
} },
@@ -5093,23 +5092,23 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[2] = PIN_NUMBER('H', 1), /* ASEBRK */
- [3] = PIN_NONE,
+ [3] = SH_PFC_PIN_NONE,
[4] = PIN_NUMBER('G', 2), /* TDI */
[5] = PIN_NUMBER('F', 3), /* TMS */
[6] = PIN_NUMBER('F', 4), /* TCK */
[7] = PIN_NUMBER('F', 1), /* TRST# */
- [8] = PIN_NONE,
- [9] = PIN_NONE,
- [10] = PIN_NONE,
- [11] = PIN_NONE,
- [12] = PIN_NONE,
- [13] = PIN_NONE,
- [14] = PIN_NONE,
+ [8] = SH_PFC_PIN_NONE,
+ [9] = SH_PFC_PIN_NONE,
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
[15] = PIN_NUMBER('G', 3), /* FSCLKST# */
[16] = RCAR_GP_PIN(0, 17), /* SDA4 */
[17] = RCAR_GP_PIN(0, 16), /* SCL4 */
- [18] = PIN_NONE,
- [19] = PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
[20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */
[21] = RCAR_GP_PIN(0, 15), /* D15 */
[22] = RCAR_GP_PIN(0, 14), /* D14 */
@@ -5129,8 +5128,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
[3] = RCAR_GP_PIN(5, 2), /* TX0_A */
[4] = RCAR_GP_PIN(5, 1), /* RX0_A */
- [5] = PIN_NONE,
- [6] = PIN_NONE,
+ [5] = SH_PFC_PIN_NONE,
+ [6] = SH_PFC_PIN_NONE,
[7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
[8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
[9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
@@ -5192,36 +5191,36 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[31] = RCAR_GP_PIN(5, 5), /* RX1 */
} },
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
- [0] = PIN_NONE,
- [1] = PIN_NONE,
- [2] = PIN_NONE,
- [3] = PIN_NONE,
- [4] = PIN_NONE,
- [5] = PIN_NONE,
- [6] = PIN_NONE,
- [7] = PIN_NONE,
- [8] = PIN_NONE,
- [9] = PIN_NONE,
- [10] = PIN_NONE,
- [11] = PIN_NONE,
- [12] = PIN_NONE,
- [13] = PIN_NONE,
- [14] = PIN_NONE,
- [15] = PIN_NONE,
- [16] = PIN_NONE,
- [17] = PIN_NONE,
- [18] = PIN_NONE,
- [19] = PIN_NONE,
- [20] = PIN_NONE,
- [21] = PIN_NONE,
- [22] = PIN_NONE,
- [23] = PIN_NONE,
- [24] = PIN_NONE,
- [25] = PIN_NONE,
- [26] = PIN_NONE,
- [27] = PIN_NONE,
- [28] = PIN_NONE,
- [29] = PIN_NONE,
+ [0] = SH_PFC_PIN_NONE,
+ [1] = SH_PFC_PIN_NONE,
+ [2] = SH_PFC_PIN_NONE,
+ [3] = SH_PFC_PIN_NONE,
+ [4] = SH_PFC_PIN_NONE,
+ [5] = SH_PFC_PIN_NONE,
+ [6] = SH_PFC_PIN_NONE,
+ [7] = SH_PFC_PIN_NONE,
+ [8] = SH_PFC_PIN_NONE,
+ [9] = SH_PFC_PIN_NONE,
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
+ [15] = SH_PFC_PIN_NONE,
+ [16] = SH_PFC_PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
[30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
[31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
} },
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 0b33108..c5bcb5e 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -24,6 +24,8 @@ enum {
PINMUX_TYPE_INPUT,
};

+#define SH_PFC_PIN_NONE U16_MAX
+
#define SH_PFC_PIN_CFG_INPUT (1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 36/51] pinctrl: sh-pfc: Add PORT_GP_27 helper macro

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit fbc5108d93fff92e76c41a59fe07062be84dc720 upstream.

This follows the style of the existing PORT_GP_X macros, and will be
used by a follow-up patch for the r8a7778 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 3c4b2ac..0b33108 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -546,9 +546,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)

-#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
+#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
- PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
+#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_27(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)

--
2.7.4


[PATCH/RFC 4.19.y-cip v2 35/51] pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit e551122cdb7fcb9a0fef3c22cf3dfbb34626bafc upstream.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb
12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf.

Update the pin control drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
[geert: Update R-Car E3]
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 22 +++++++++++-----------
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 22 +++++++++++-----------
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 26 +++++++++++++-------------
3 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 6dc8380e..50af7a1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -501,7 +501,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
@@ -1023,35 +1023,35 @@ static const u16 pinmux_data[] = {

PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),

PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),

PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),

PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),

PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),

@@ -1117,21 +1117,21 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),

PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
- PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),

PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
- PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),

PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),

PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),

@@ -1276,7 +1276,7 @@ static const u16 pinmux_data[] = {
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 97e3938..b05a21a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -499,7 +499,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
@@ -1015,35 +1015,35 @@ static const u16 pinmux_data[] = {

PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),

PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),

PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),

PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),

PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),

@@ -1110,20 +1110,20 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),

PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
- PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),

PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
- PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),

PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
- PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),

PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
- PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),

PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
@@ -1267,7 +1267,7 @@ static const u16 pinmux_data[] = {
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index df43e37..4db337a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -414,7 +414,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
-#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
@@ -981,23 +981,23 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),

PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),

PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),

PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
- PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),

/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
- PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),

PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
- PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),

PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
- PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),

PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
@@ -1034,7 +1034,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),

PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
- PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
@@ -1043,7 +1043,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),

PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
- PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
@@ -1053,13 +1053,13 @@ static const u16 pinmux_data[] = {

/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
- PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),

PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
- PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
@@ -1077,14 +1077,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),

PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
- PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),

PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
- PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 34/51] pinctrl: sh-pfc: rcar-gen3: Rename RTS{0, 1, 3, 4}# pin function definitions

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit 624a7a12cc0cc776c9c82347ffe5ddce7218eeca upstream.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of
Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and
IPSR registers are renamed to RTS{0,1,3,4}_#.
This patch updates the pin control drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
[geert: Update R-Car H3 ES1.x, V3M, V3H, and D3]
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
[fab: dropped changes not related to the r8a77990]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 36 +++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 4557070..df43e37 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -2,7 +2,7 @@
/*
* R8A77990 processor support - PFC hardware block.
*
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
@@ -165,7 +165,7 @@
#define GPSR5_7 F_(SCK2_A, IP12_7_4)
#define GPSR5_6 F_(TX1, IP12_3_0)
#define GPSR5_5 F_(RX1, IP11_31_28)
-#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
+#define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
#define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
#define GPSR5_2 F_(TX0_A, IP11_15_12)
#define GPSR5_1 F_(RX0_A, IP11_11_8)
@@ -219,7 +219,7 @@
#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -240,10 +240,10 @@
#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -289,8 +289,8 @@
#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
@@ -668,7 +668,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),

PINMUX_IPSR_GPSR(IP3_15_12, A4),
- PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
@@ -818,7 +818,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
- PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),

PINMUX_IPSR_GPSR(IP5_31_28, D2),
@@ -842,7 +842,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
- PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),

@@ -1083,7 +1083,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),

- PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
@@ -1093,7 +1093,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
- PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
@@ -2836,7 +2836,7 @@ static const unsigned int scif0_ctrl_a_pins[] = {
};

static const unsigned int scif0_ctrl_a_mux[] = {
- RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
+ RTS0_N_A_MARK, CTS0_N_A_MARK,
};

static const unsigned int scif0_data_b_pins[] = {
@@ -2882,7 +2882,7 @@ static const unsigned int scif1_ctrl_pins[] = {
};

static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_TANS_MARK, CTS1_N_MARK,
+ RTS1_N_MARK, CTS1_N_MARK,
};

/* - SCIF2 ------------------------------------------------------------------ */
@@ -2938,7 +2938,7 @@ static const unsigned int scif3_ctrl_a_pins[] = {
};

static const unsigned int scif3_ctrl_a_mux[] = {
- RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
+ RTS3_N_A_MARK, CTS3_N_A_MARK,
};

static const unsigned int scif3_data_b_pins[] = {
@@ -2993,7 +2993,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
};

static const unsigned int scif4_ctrl_a_mux[] = {
- RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
+ RTS4_N_A_MARK, CTS4_N_A_MARK,
};

static const unsigned int scif4_data_b_pins[] = {
@@ -3029,7 +3029,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
};

static const unsigned int scif4_ctrl_c_mux[] = {
- RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
+ RTS4_N_C_MARK, CTS4_N_C_MARK,
};

/* - SCIF5 ------------------------------------------------------------------ */
@@ -5125,7 +5125,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
- [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */
+ [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
[2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
[3] = RCAR_GP_PIN(5, 2), /* TX0_A */
[4] = RCAR_GP_PIN(5, 1), /* RX0_A */
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 33/51] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit e87882eb9be10b2b9e28156922c2a47d877f5db4 upstream.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug
24, 2018, there is no need to configure MOD_SEL1 bit30 when the
SSI_SCK2_{A,B} or SSI_WS2_{A,B} pin functions are selected.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
[geert: Remove now unused definitions, mark MOD_SEL1 bit30 reserved]
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 8a95cb5..4557070 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -429,7 +429,6 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))

/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
-#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
@@ -450,7 +449,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM

#define PINMUX_MOD_SELS \
\
-MOD_SEL0_30_29 MOD_SEL1_30 \
+MOD_SEL0_30_29 \
MOD_SEL1_29 \
MOD_SEL0_28 MOD_SEL1_28 \
MOD_SEL0_27_26 \
@@ -1040,7 +1039,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
- PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
+ PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),

PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
@@ -1049,7 +1048,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
- PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
+ PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),

/* IPSR11 */
@@ -1067,13 +1066,13 @@ static const u16 pinmux_data[] = {

PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
- PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
+ PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),

PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
- PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
+ PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),

@@ -4964,12 +4963,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
- 1, 2, 2, 2, 1, 1, 2, 1, 4),
+ GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
+ 2, 2, 2, 1, 1, 2, 1, 4),
GROUP(
- /* RESERVED 31 */
- 0, 0,
- MOD_SEL1_30
+ /* RESERVED 31, 30 */
+ 0, 0, 0, 0,
MOD_SEL1_29
MOD_SEL1_28
/* RESERVED 27 */
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 32/51] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit e167d723e1a472d252e5c4baf823b77ce5543b05 upstream.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
Aug 24, 2018, there is no need to configure MOD_SEL1 bit31 when the
SIM0_D_{A,B} pin function is selected.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
[geert: Remove now unused definitions, mark MOD_SEL1 bit31 reserved]
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index fba0c22..8a95cb5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -429,7 +429,6 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))

/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
-#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
@@ -451,7 +450,6 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM

#define PINMUX_MOD_SELS \
\
- MOD_SEL1_31 \
MOD_SEL0_30_29 MOD_SEL1_30 \
MOD_SEL1_29 \
MOD_SEL0_28 MOD_SEL1_28 \
@@ -1180,7 +1178,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
- PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
+ PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),

PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
@@ -1248,7 +1246,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
- PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),

PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
@@ -4969,7 +4967,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
1, 2, 2, 2, 1, 1, 2, 1, 4),
GROUP(
- MOD_SEL1_31
+ /* RESERVED 31 */
+ 0, 0,
MOD_SEL1_30
MOD_SEL1_29
MOD_SEL1_28
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 31/51] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit 943ff71281c6ce44ca48ea1b08c55f1e63648d00 upstream.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug
24, 2018, the MOD_SEL0 bit16 must be set to 0 when the NFALE_A and
NFRB_N_A pin functions are selected.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index a3f22ff..fba0c22 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1037,7 +1037,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),

PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
- PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
+ PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDFC_0),
PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
@@ -1046,7 +1046,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),

PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
- PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
+ PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDFC_0),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 30/51] pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A, B, C} to SEL_ADG{A, B, C}

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit a040f3dec8eb7b11c2fd28762bd4f838da4d166b upstream.

According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of Dec
22, 2017, and the Errata for Rev 1.50 of Dec 25, 2018, MOD_SEL0 register
bits 3, 4, 17, and 18 are renamed from SEL_ADG_{A,B,C} to
SEL_ADG{A,B,C}. Update the pin control drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 22 +++++++++++-----------
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 22 +++++++++++-----------
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 22 +++++++++++-----------
3 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 527ace0..0da9083 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1,7 +1,7 @@
/*
* R8A7795 ES2.0+ processor support - PFC hardware block.
*
- * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ * Copyright (C) 2015-2019 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -463,7 +463,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)

/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -499,8 +499,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)

#define PINMUX_MOD_SELS \
@@ -1124,7 +1124,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1157,7 +1157,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1216,7 +1216,7 @@ static const u16 pinmux_data[] = {

PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1263,7 +1263,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1272,7 +1272,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1403,9 +1403,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),

/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),

- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index ba52b5b..6dc8380e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1,7 +1,7 @@
/*
* R8A7796 processor support - PFC hardware block.
*
- * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
*
@@ -468,7 +468,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)

/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -505,8 +505,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)

#define PINMUX_MOD_SELS \
@@ -1138,7 +1138,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1171,7 +1171,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1230,7 +1230,7 @@ static const u16 pinmux_data[] = {

PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1277,7 +1277,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1286,7 +1286,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1414,9 +1414,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),

/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),

- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 97361c3..97e3938 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -3,7 +3,7 @@
* R8A77965 processor support - PFC hardware block.
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@...>
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
@@ -466,7 +466,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)

/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -503,8 +503,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)

#define PINMUX_MOD_SELS \
@@ -1129,7 +1129,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1162,7 +1162,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1221,7 +1221,7 @@ static const u16 pinmux_data[] = {

PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1268,7 +1268,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1277,7 +1277,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1406,9 +1406,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),

/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),

- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 29/51] pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit 662dc924a05e9dffd62f602c7111d6b7ada8fa88 upstream.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
Jun 4, 2018, the CC5_OSCOUT pin is removed. Update the pin control
drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
[geert: Update R-Car V3M, V3H]
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-r8a77980.c | 3 +--
6 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 157a8e9..c77db750 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -341,7 +341,7 @@
#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -1353,7 +1353,6 @@ static const u16 pinmux_data[] = {

/* IPSR16 */
PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
- PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),

PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 5e6df51..527ace0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -352,7 +352,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -1404,7 +1404,6 @@ static const u16 pinmux_data[] = {

/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),

PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e3da9ba..ba52b5b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -357,7 +357,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -1415,7 +1415,6 @@ static const u16 pinmux_data[] = {

/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),

PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 6f800de..97361c3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -355,7 +355,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -1407,7 +1407,6 @@ static const u16 pinmux_data[] = {

/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),

PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
index 5582f41..5785928 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -175,7 +175,7 @@
#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -474,7 +474,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),

PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
- PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),

PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
index 04d51b1..27c4392 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
@@ -205,7 +205,7 @@
#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -555,7 +555,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),

PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
- PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),

PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 28/51] pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions

Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit 5671f8e0270ad5e33e3088e5f0fa71af67129630 upstream.

The HDMI CEC function is not supported by the R-Car Gen3 Hardware Manual
Rev 1.00. Therefore, delete the corresponding pin groups and functions,
and rename the HDMI[01]_CEC definitions to match their GPIO
functionality.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
[geert: Squashed several commits]
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 44 ++++++--------------------------
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 44 ++++++--------------------------
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 27 +++++---------------
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 8 +++---
4 files changed, 26 insertions(+), 97 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index ab5a94e..157a8e9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -200,8 +200,8 @@
#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)

/* GPSR7 */
-#define GPSR7_3 FM(HDMI1_CEC)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_3 FM(GP7_03)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)

@@ -574,8 +574,8 @@ static const u16 pinmux_data[] = {

PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
- PINMUX_SINGLE(HDMI0_CEC),
- PINMUX_SINGLE(HDMI1_CEC),
+ PINMUX_SINGLE(GP7_02),
+ PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(I2C_SEL_0_1),
PINMUX_SINGLE(I2C_SEL_3_1),
PINMUX_SINGLE(I2C_SEL_5_1),
@@ -2066,22 +2066,6 @@ static const unsigned int du_disp_pins[] = {
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
-/* - HDMI ------------------------------------------------------------------- */
-static const unsigned int hdmi0_cec_pins[] = {
- /* HDMI0_CEC */
- RCAR_GP_PIN(7, 2),
-};
-static const unsigned int hdmi0_cec_mux[] = {
- HDMI0_CEC_MARK,
-};
-static const unsigned int hdmi1_cec_pins[] = {
- /* HDMI1_CEC */
- RCAR_GP_PIN(7, 3),
-};
-static const unsigned int hdmi1_cec_mux[] = {
- HDMI1_CEC_MARK,
-};
-
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -3911,8 +3895,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(hdmi0_cec),
- SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4263,14 +4245,6 @@ static const char * const du_groups[] = {
"du_disp",
};

-static const char * const hdmi0_groups[] = {
- "hdmi0_cec",
-};
-
-static const char * const hdmi1_groups[] = {
- "hdmi1_cec",
-};
-
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4646,8 +4620,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(hdmi0),
- SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -5363,8 +5335,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
- { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
} },
@@ -5619,8 +5591,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
- [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
+ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
} },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index b1aa5c1..5e6df51 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -202,8 +202,8 @@
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)

/* GPSR7 */
-#define GPSR7_3 FM(HDMI1_CEC)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_3 FM(GP7_03)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)

@@ -588,8 +588,8 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
- PINMUX_SINGLE(HDMI0_CEC),
- PINMUX_SINGLE(HDMI1_CEC),
+ PINMUX_SINGLE(GP7_02),
+ PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(I2C_SEL_0_1),
PINMUX_SINGLE(I2C_SEL_3_1),
PINMUX_SINGLE(I2C_SEL_5_1),
@@ -2126,22 +2126,6 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};

-/* - HDMI ------------------------------------------------------------------- */
-static const unsigned int hdmi0_cec_pins[] = {
- /* HDMI0_CEC */
- RCAR_GP_PIN(7, 2),
-};
-static const unsigned int hdmi0_cec_mux[] = {
- HDMI0_CEC_MARK,
-};
-static const unsigned int hdmi1_cec_pins[] = {
- /* HDMI1_CEC */
- RCAR_GP_PIN(7, 3),
-};
-static const unsigned int hdmi1_cec_mux[] = {
- HDMI1_CEC_MARK,
-};
-
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -4230,8 +4214,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(hdmi0_cec),
- SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4613,14 +4595,6 @@ static const char * const du_groups[] = {
"du_disp",
};

-static const char * const hdmi0_groups[] = {
- "hdmi0_cec",
-};
-
-static const char * const hdmi1_groups[] = {
- "hdmi1_cec",
-};
-
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -5027,8 +5001,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(hdmi0),
- SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -5752,8 +5724,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
- { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
} },
@@ -6007,8 +5979,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
- [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
+ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
} },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index aedb431..e3da9ba 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -208,7 +208,7 @@

/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)

@@ -599,7 +599,7 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
- PINMUX_SINGLE(HDMI0_CEC),
+ PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -2142,15 +2142,6 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};

-/* - HDMI ------------------------------------------------------------------- */
-static const unsigned int hdmi0_cec_pins[] = {
- /* HDMI0_CEC */
- RCAR_GP_PIN(7, 2),
-};
-static const unsigned int hdmi0_cec_mux[] = {
- HDMI0_CEC_MARK,
-};
-
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -4126,7 +4117,7 @@ static const unsigned int vin5_clk_mux[] = {
};

static const struct {
- struct sh_pfc_pin_group common[313];
+ struct sh_pfc_pin_group common[312];
struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
@@ -4173,7 +4164,6 @@ static const struct {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4587,10 +4577,6 @@ static const char * const du_groups[] = {
"du_disp",
};

-static const char * const hdmi0_groups[] = {
- "hdmi0_cec",
-};
-
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4984,7 +4970,7 @@ static const char * const vin5_groups[] = {
};

static const struct {
- struct sh_pfc_function common[50];
+ struct sh_pfc_function common[49];
struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
@@ -4996,7 +4982,6 @@ static const struct {
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -5726,7 +5711,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
@@ -5982,7 +5967,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 3ebfd85..6f800de 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -206,7 +206,7 @@

/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)

@@ -593,7 +593,7 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
- PINMUX_SINGLE(HDMI0_CEC),
+ PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -4693,7 +4693,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
@@ -4947,7 +4947,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 27/51] pinctrl: sh-pfc: Add missing #include <linux/errno.h> #include

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 2f9f5094f8b7a1da8852c4a50b205232e62d72dc upstream.

Source files using -Exxx error codes should include <linux/errno.h>.
On ARM, this header file is included indirectly; on SuperH, it is not,
leading to "error: ‘EINVAL’ undeclared" failures when enabling
compile-testing later.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a77980.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 1 +
12 files changed, 12 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index cb4c907..f548ccf 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -5,6 +5,7 @@
* Copyright (C) 2018 Renesas Electronics Corp.
*/

+#include <linux/errno.h>
#include <linux/kernel.h>

#include "sh_pfc.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index d2fd6e87..7b4c11b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -21,6 +21,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

+#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 332cb96..c4ffb40 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -9,6 +9,7 @@
* as published by the Free Software Foundation.
*/

+#include <linux/errno.h>
#include <linux/kernel.h>

#include "sh_pfc.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index 7b8dfee..985d5ae 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -10,6 +10,7 @@
* as published by the Free Software Foundation.
*/

+#include <linux/errno.h>
#include <linux/kernel.h>

#include "core.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index c75d48f..ab5a94e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -8,6 +8,7 @@
* the Free Software Foundation; version 2 of the License.
*/

+#include <linux/errno.h>
#include <linux/kernel.h>

#include "core.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index d27a9c7..b1aa5c1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -8,6 +8,7 @@
* the Free Software Foundation; version 2 of the License.
*/

+#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 7fe0f9f..aedb431 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -14,6 +14,7 @@
* the Free Software Foundation; version 2 of the License.
*/

+#include <linux/errno.h>
#include <linux/kernel.h>

#include "core.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 77661cb..3ebfd85 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -12,6 +12,7 @@
* Copyright (C) 2015 Renesas Electronics Corporation
*/

+#include <linux/errno.h>
#include <linux/kernel.h>

#include "core.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
index ed08cce..5582f41 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -15,6 +15,7 @@
* the Free Software Foundation; version 2 of the License.
*/

+#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
index 246ab41..04d51b1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
@@ -12,6 +12,7 @@
* Copyright (C) 2015 Renesas Electronics Corporation
*/

+#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 7e7d70f..a3f22ff 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -11,6 +11,7 @@
* Copyright (C) 2016-2017 Renesas Electronics Corp.
*/

+#include <linux/errno.h>
#include <linux/kernel.h>

#include "core.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index a4d7f20..b3e65dd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -14,6 +14,7 @@
* the Free Software Foundation; version 2 of the License.
*/

+#include <linux/errno.h>
#include <linux/kernel.h>

#include "core.h"
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 26/51] pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume

Fabrizio Castro <fabrizio.castro@...>
 

From: Marek Vasut <marek.vasut+renesas@...>

commit d92ee9cf8ec8d7fe1d7dbc4b3ee459419b1e5533 upstream.

The TDSELCTRL register is responsible for configuring the SDHI/MMC clock
return path delay and may be adjusted by the bootloader. Retain the value
across suspend/resume to prevent hardware instability after resume.

Signed-off-by: Marek Vasut <marek.vasut+renesas@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[fab: dropped changes not related to either r8a7796 or r8a77990]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 ++
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 2 ++
2 files changed, 4 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 3a178d89..7fe0f9f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -5859,10 +5859,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {

enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};

static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 9ade895..7e7d70f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -4997,10 +4997,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {

enum ioctrl_regs {
POCCTRL0,
+ TDSELCTRL,
};

static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL0] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};

--
2.7.4


[PATCH/RFC 4.19.y-cip v2 25/51] pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions

Fabrizio Castro <fabrizio.castro@...>
 

commit 2cee6cb290ab30f2f3a69866d24ca6cb64b1d7e8 upstream.

CANFD is found also on the R8A774C0, therefore move CANFD pin
groups and functions to "common".

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index b8c49f0..9ade895 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -3765,8 +3765,8 @@ static const unsigned int vin5_clk_b_mux[] = {
};

static const struct {
- struct sh_pfc_pin_group common[245];
- struct sh_pfc_pin_group automotive[23];
+ struct sh_pfc_pin_group common[247];
+ struct sh_pfc_pin_group automotive[21];
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@@ -3797,6 +3797,8 @@ static const struct {
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(canfd0_data),
+ SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_in_0),
@@ -4016,8 +4018,6 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clk_b),
},
.automotive = {
- SH_PFC_PIN_GROUP(canfd0_data),
- SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
@@ -4464,8 +4464,8 @@ static const char * const vin5_groups[] = {
};

static const struct {
- struct sh_pfc_function common[45];
- struct sh_pfc_function automotive[6];
+ struct sh_pfc_function common[47];
+ struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -4473,6 +4473,8 @@ static const struct {
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
@@ -4515,8 +4517,6 @@ static const struct {
SH_PFC_FUNCTION(vin5),
},
.automotive = {
- SH_PFC_FUNCTION(canfd0),
- SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
--
2.7.4


[PATCH/RFC 4.19.y-cip v2 24/51] pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 3df892fdbfe6919270a65a25c7982e2701c44f2b upstream.

The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018)
renamed the various miscellaneous I/O control registers (IOCTRLx) on
R-Car E3, to reflect better their actual purposes, and matching other
SoCs.

Update the code to match this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Ulrich Hecht <uli+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index b654e06..b8c49f0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -4996,11 +4996,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
};

enum ioctrl_regs {
- IOCTRL30,
+ POCCTRL0,
};

static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
- [IOCTRL30] = { 0xe6060380, },
+ [POCCTRL0] = { 0xe6060380, },
{ /* sentinel */ },
};

@@ -5009,7 +5009,7 @@ static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
{
int bit = -EINVAL;

- *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;

if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
bit = pin & 0x1f;
--
2.7.4

6521 - 6540 of 9641