Date   

[PATCH 58/86] ARM: shmobile: Add pm support for r8a7745

Fabrizio Castro <fabrizio.castro@...>
 

This patch adds pm support for r8a7745 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/mach-shmobile/pm-rcar-gen2.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index 94a2759..f1bee67 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -85,6 +85,9 @@ void __init rcar_gen2_pm_init(void)
} else if (of_machine_is_compatible("renesas,r8a7743")) {
boot_vector_addr = RAM;
syscier = 0x00101003;
+ } else if (of_machine_is_compatible("renesas,r8a7745")) {
+ boot_vector_addr = RAM;
+ syscier = 0x00300060;
}

/* RAM for jump stub, because BAR requires 256KB aligned address */
--
2.7.4


[PATCH 57/86] ARM: shmobile: Move shmobile_smp_{mpidr, fn, arg}[] from .text to .bss

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

If CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend:

Freezing user space processes ... (elapsed 0.004 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.002 seconds)
done.
PM: suspend of devices complete after 111.948 msecs
PM: late suspend of devices complete after 1.086 msecs
PM: noirq suspend of devices complete after 11.576 msecs
Disabling non-boot CPUs ...
Kernel panic - not syncing: Attempted to kill the idle task!
1014ec ---[ end Kernel panic - not syncing: Attempted to kill the idle task!
CPU0: stopping

This happens because the .text section is marked read-only, while the
arrays shmobile_smp_mpidr[], shmobile_smp_fn[], and shmobile_smp_arg[]
are being written to.

Fix this by moving these arrays from the .text to the .bss section.
This requires accessing them through PC-relative offsets.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Kees Cook <keescook@...>
Reviewed-by: Nicolas Pitre <nico@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 4e960f52fce16a3bf3261fa92c34cf2306059ba2)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/mach-shmobile/headsmp.S | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 330c1fc..94d86ed 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -50,9 +50,11 @@ ENTRY(shmobile_smp_boot)
mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
and r0, r1, r0 @ r0 = cpu_logical_map() value
mov r1, #0 @ r1 = CPU index
- adr r5, 1f @ array of per-cpu mpidr values
- adr r6, 2f @ array of per-cpu functions
- adr r7, 3f @ array of per-cpu arguments
+ adr r2, 1f
+ ldmia r2, {r5, r6, r7}
+ add r5, r5, r2 @ array of per-cpu mpidr values
+ add r6, r6, r2 @ array of per-cpu functions
+ add r7, r7, r2 @ array of per-cpu arguments

shmobile_smp_boot_find_mpidr:
ldr r8, [r5, r1, lsl #2]
@@ -80,12 +82,18 @@ ENTRY(shmobile_smp_sleep)
b shmobile_smp_boot
ENDPROC(shmobile_smp_sleep)

+ .align 2
+1: .long shmobile_smp_mpidr - .
+ .long shmobile_smp_fn - 1b
+ .long shmobile_smp_arg - 1b
+
+ .bss
.globl shmobile_smp_mpidr
shmobile_smp_mpidr:
-1: .space NR_CPUS * 4
+ .space NR_CPUS * 4
.globl shmobile_smp_fn
shmobile_smp_fn:
-2: .space NR_CPUS * 4
+ .space NR_CPUS * 4
.globl shmobile_smp_arg
shmobile_smp_arg:
-3: .space NR_CPUS * 4
+ .space NR_CPUS * 4
--
2.7.4


[PATCH 56/86] ARM: shmobile: rcar-gen2: Make rcar_gen2_dma_contiguous static

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

make C=1:

arch/arm/mach-shmobile/setup-rcar-gen2.c:186:12: warning: symbol 'rcar_gen2_dma_contiguous' was not declared. Should it be static?

Make it static, and move it inside the function to avoid a "defined but
not used" warning if CONFIG_DMA_CMA=n.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 0c1690705417ac1b33f01125552349e3cfc9766d)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/mach-shmobile/setup-rcar-gen2.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 828ce09..50d7438 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -168,8 +168,6 @@ static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
return 0;
}

-struct cma *rcar_gen2_dma_contiguous;
-
void __init rcar_gen2_reserve(void)
{
struct memory_reserve_config mrc;
@@ -180,9 +178,12 @@ void __init rcar_gen2_reserve(void)

of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
#ifdef CONFIG_DMA_CMA
- if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size))
+ if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) {
+ static struct cma *rcar_gen2_dma_contiguous;
+
dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
&rcar_gen2_dma_contiguous, true);
+ }
#endif
}

--
2.7.4


[PATCH 55/86] ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

On Cortex-A7, the arch timer CNTVOFF register is uninitialized.
Ideally it should be initialized by the boot loader, but it isn't.

For the boot CPU, CNTVOFF is initialized by Linux since commit
9ce3fa6816c2fb59 ("ARM: shmobile: rcar-gen2: Add CA7 arch_timer
initialization for r8a7794").
For secondary CPU cores, no such initialization is done.

Hence when enabling SMP on r8a7794, the kernel log is spammed with:

WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored.
Please report this, consider using a different clocksource, if possible.
Your kernel is probably still fine.

As Marc Zyngier pointed out that Cortex-A15 and Cortex-A7 are similar with
respect to CNTVOFF, we have been very lucky this just worked on R-Car
Gen2 SoCs with Cortex-A15 cores.

To fix this:
- Move the existing inline asm code to initialize CNTVOFF to an
assembler source file (adding comments and replacing hardcoded
constants by definitions in the process), so it can be reused,
- Perform the initialization of CNTVOFF on the boot CPU (Cortex-A15 or
Cortex-A7) on all R-Car Gen2 and RZ/G1 parts,
- Wrap the standard secondary_startup() routine inside a routine which
initializes CNTVOFF.

Based on patches by Hisashi Nakamura in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Tested-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 3fd45a136ff61bb54deab70fb2d534a85e40481f)
(move back to virt_to_phys to keep the code consistent)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/mach-shmobile/Makefile | 1 +
arch/arm/mach-shmobile/common.h | 2 ++
arch/arm/mach-shmobile/headsmp-apmu.S | 37 ++++++++++++++++++++++++++++++++
arch/arm/mach-shmobile/platsmp-apmu.c | 2 +-
arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
5 files changed, 43 insertions(+), 19 deletions(-)
create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S

diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 4620202..13a4b38 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -22,6 +22,7 @@ cpu-y := platsmp.o headsmp.o
# Shared SoC family objects
obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
CFLAGS_setup-rcar-gen2.o += -march=armv7-a
+obj-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o
obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 9cb1121..7b20b1b 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -1,6 +1,7 @@
#ifndef __ARCH_MACH_COMMON_H
#define __ARCH_MACH_COMMON_H

+extern void shmobile_init_cntvoff(void);
extern void shmobile_init_delay(void);
extern void shmobile_boot_vector(void);
extern unsigned long shmobile_boot_fn;
@@ -11,6 +12,7 @@ extern void shmobile_smp_sleep(void);
extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
unsigned long arg);
extern bool shmobile_smp_cpu_can_disable(unsigned int cpu);
+extern void shmobile_boot_apmu(void);
extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
new file mode 100644
index 0000000..db4743d
--- /dev/null
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -0,0 +1,37 @@
+/*
+ * SMP support for APMU based systems with Cortex A7/A15
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(shmobile_init_cntvoff)
+ /*
+ * CNTVOFF has to be initialized either from non-secure Hypervisor
+ * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+ * then it should be handled by the secure code
+ */
+ cps #MON_MODE
+ mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
+ orr r0, r1, #1
+ mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
+ instr_sync
+ mov r0, #0
+ mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+ instr_sync
+ mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
+ instr_sync
+ cps #SVC_MODE
+ ret lr
+ENDPROC(shmobile_init_cntvoff)
+
+ENTRY(shmobile_boot_apmu)
+ bl shmobile_init_cntvoff
+ b secondary_startup
+ENDPROC(shmobile_boot_apmu)
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 331409a..ffae187 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -204,7 +204,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/* For this particular CPU register boot vector */
- shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
+ shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_apmu), 0);

return apmu_wrap(cpu, apmu_power_on);
}
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 549a66f..828ce09 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -58,27 +58,11 @@ void __init rcar_gen2_timer_init(void)
int extal_mhz = 0;
u32 freq;

+ shmobile_init_cntvoff();
+
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7794")) {
freq = 260000000 / 8; /* ZS / 8 */
- /* CNTVOFF has to be initialized either from non-secure
- * Hypervisor mode or secure Monitor mode with SCR.NS==1.
- * If TrustZone is enabled then it should be handled by the
- * secure code.
- */
- asm volatile(
- " cps 0x16\n"
- " mrc p15, 0, r1, c1, c1, 0\n"
- " orr r0, r1, #1\n"
- " mcr p15, 0, r0, c1, c1, 0\n"
- " isb\n"
- " mov r0, #0\n"
- " mcrr p15, 4, r0, r0, c14\n"
- " isb\n"
- " mcr p15, 0, r1, c1, c1, 0\n"
- " isb\n"
- " cps 0x13\n"
- : : : "r0", "r1");
} else {
/* At Linux boot time the r8a7790 arch timer comes up
* with the counter disabled. Moreover, it may also report
--
2.7.4


[PATCH 54/86] ARM: Add definition for monitor mode

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

<asm/ptrace.h> provides *_MODE definitions for the various processor
modes, but monitor mode was missing.

Add MON_MODE to avoid code using the hardcoded value.

Suggested-by: Marc Zyngier <marc.zyngier@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Tested-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit c5d43be52e0c7380f985585ef72dac1a6a89b59d)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/include/uapi/asm/ptrace.h | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h
index 5af0ed1..70ff6bf 100644
--- a/arch/arm/include/uapi/asm/ptrace.h
+++ b/arch/arm/include/uapi/asm/ptrace.h
@@ -53,6 +53,7 @@
#endif
#define FIQ_MODE 0x00000011
#define IRQ_MODE 0x00000012
+#define MON_MODE 0x00000016
#define ABT_MODE 0x00000017
#define HYP_MODE 0x0000001a
#define UND_MODE 0x0000001b
--
2.7.4


[PATCH 53/86] ARM: debug-ll: Add support for r8a7745

Fabrizio Castro <fabrizio.castro@...>
 

Enable low-level debugging support for RZ/G1E (r8a7745). RZ/G1E uses
SCIF4 for the debug console.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 8e5f2d651f5b8ebf4b462aac02f51fe6075f88c0)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/Kconfig.debug | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9b2b59c..c84f87b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -831,6 +831,13 @@ choice
Say Y here if you want kernel low-level debugging support
via SCIF2 on Renesas R-Car E2 (R8A7794).

+ config DEBUG_RCAR_GEN2_SCIF4
+ bool "Kernel low-level debugging messages via SCIF4 on R8A7745"
+ depends on ARCH_R8A7745
+ help
+ Say Y here if you want kernel low-level debugging support
+ via SCIF4 on Renesas RZ/G1E (R8A7745).
+
config DEBUG_RMOBILE_SCIFA0
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
depends on ARCH_R8A73A4
@@ -1334,6 +1341,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
+ default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
@@ -1434,6 +1442,7 @@ config DEBUG_UART_PHYS
default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
+ default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
default 0xe8008000 if DEBUG_R7S72100_SCIF2
default 0xf0000be0 if ARCH_EBSA110
default 0xf040ab00 if DEBUG_BRCMSTB_UART
@@ -1467,6 +1476,7 @@ config DEBUG_UART_PHYS
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
+ DEBUG_RCAR_GEN2_SCIF4 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
--
2.7.4


[PATCH 52/86] ARM: dts: iwg22m: Add eMMC support

Fabrizio Castro <fabrizio.castro@...>
 

Add eMMC support for iW-RainboW-G22M-SM.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 3350ed907182049b806992f228021e7997183dda)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index 9dbd854..afb1148 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
@@ -17,8 +17,34 @@
device_type = "memory";
reg = <0 0x40000000 0 0x20000000>;
};
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};

&extal_clk {
clock-frequency = <20000000>;
};
+
+&pfc {
+ mmcif0_pins: mmc {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ };
+};
+
+&mmcif0 {
+ pinctrl-0 = <&mmcif0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&reg_3p3v>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
--
2.7.4


[PATCH 51/86] ARM: dts: r8a7745: Add MMC interface support

Fabrizio Castro <fabrizio.castro@...>
 

Add MMC interface support for r8a7745 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 933b16efb7be16e98a6bcd04ed59c5e91371afef)
(moved DT node to different location to allow for better sorting.
removed resets property. modified clocks and power-domains
properties.)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index a8ecbc3..4b93ea3 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -514,6 +514,21 @@
status = "disabled";
};

+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7745",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7745_CLK_MMCIF0>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ reg-io-width = <4>;
+ max-frequency = <97500000>;
+ status = "disabled";
+ };
+
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7745";
reg = <0 0xee700000 0 0x400>;
--
2.7.4


[PATCH 50/86] dt-bindings: mmc: sh_mmcif: Document r8a7745 DT bindings

Fabrizio Castro <fabrizio.castro@...>
 

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Acked-by: Simon Horman <horms+renesas@...>
Acked-by: Rob Herring <robh@...>
Signed-off-by: Ulf Hansson <ulf.hansson@...>
(cherry picked from commit b773b3bf1916a368c29a19916abf0f5eca8b3c33)
(dropped interrupt information)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
Documentation/devicetree/bindings/mmc/renesas,mmcif.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
index 0c9ac54..aa33691 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
+++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
@@ -10,6 +10,7 @@ Required properties:
fallback. Examples with <soctype> are:
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
- "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
+ - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
- "renesas,mmcif-r8a7794" for the MMCIF found in r8a7794 SoCs
--
2.7.4


[PATCH 49/86] ARM: dts: iwg22d: Use /dev/ttySC3 as debug console

Fabrizio Castro <fabrizio.castro@...>
 

The BSP release from iWave uses /dev/ttySC3 as debug console, this patch
renames the alias accordingly for compatibility.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 4c1d14ce4a03af24c2bac21c4a19f17d20b4a763)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index aac84c6..1f761a4 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -16,13 +16,13 @@
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";

aliases {
- serial0 = &scif4;
+ serial3 = &scif4;
ethernet0 = &avb;
};

chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial3:115200n8";
};
};

--
2.7.4


[PATCH 48/86] ARM: dts: iwg22d-sodimm: Add Ethernet AVB support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Define the iWave RainboW-G22D board dependent part of the Ethernet
AVB device node.

On some older versions of the platform (before R4.0) the phy address
may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which
will be the first mainstream release), hence using 3 in the dts.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit d6ee805325b1d082fa33be3024163e5f7931ed54)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 442a5cb..aac84c6 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -17,9 +17,11 @@

aliases {
serial0 = &scif4;
+ ethernet0 = &avb;
};

chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
};
@@ -29,6 +31,11 @@
groups = "scif4_data_b";
function = "scif4";
};
+
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_gmii";
+ function = "avb";
+ };
};

&scif4 {
@@ -37,3 +44,22 @@

status = "okay";
};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy3>;
+ phy-mode = "gmii";
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ /*
+ * On some older versions of the platform (before R4.0) the phy address
+ * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
+ */
+ reg = <3>;
+ micrel,led-mode = <1>;
+ };
+};
--
2.7.4


[PATCH 47/86] ARM: dts: r8a7745: Add Ethernet AVB support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Add Ethernet AVB support for r8a7745 SoC.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 372b01369fed699c417789ad94344847e09b7a43)
(moved the node to a better location to allow for better sorting.
removed resets property. modified clocks and power-domains
properties.)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 112a612..a8ecbc3 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -259,6 +259,18 @@
dma-channels = <15>;
};

+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7745",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7745_CLK_ETHERAVB>;
+ power-domains = <&cpg_clocks>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7745", "renesas,scifa";
reg = <0 0xe6c40000 0 0x40>;
--
2.7.4


[PATCH 46/86] dt-bindings: net: ravb : Add support for r8a7745 SoC

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Add a new compatible string for the RZ/G1E (R8A7745) SoC.

Signed-off-by: Biju Das <biju.das@...>
Acked-by: Sergei Shtylyov <sergei.shtylyov@...>
Signed-off-by: David S. Miller <davem@...>
(cherry picked from commit 22cb7a3ac380ecaab6837670963813599b123a53)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index 715b8ce..9a22b1e 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -6,6 +6,7 @@ interface contains.
Required properties:
- compatible: Must contain one or more of the following:
- "renesas,etheravb-r8a7743" for the R8A7743 SoC.
+ - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
- "renesas,etheravb-r8a7790" for the R8A7790 SoC.
- "renesas,etheravb-r8a7794" for the R8A7794 SoC.
- "renesas,etheravb-rcar-gen2" as a fallback for the above
--
2.7.4


[PATCH 45/86] ARM: dts: r8a7743: Use R-Car GPIO Gen2 fallback compat string

Fabrizio Castro <fabrizio.castro@...>
 

From: Simon Horman <horms+renesas@...>

Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7743 SoC.

This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.

Signed-off-by: Simon Horman <horms+renesas@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
(cherry picked from commit 936e7d7472547294fa305f60546afad232896fdc)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 64d8462..d94fbce 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -108,7 +108,7 @@

gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7743",
- "renesas,gpio-rcar";
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@@ -122,7 +122,7 @@

gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7743",
- "renesas,gpio-rcar";
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@@ -136,7 +136,7 @@

gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7743",
- "renesas,gpio-rcar";
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@@ -150,7 +150,7 @@

gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7743",
- "renesas,gpio-rcar";
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@@ -164,7 +164,7 @@

gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7743",
- "renesas,gpio-rcar";
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@@ -178,7 +178,7 @@

gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7743",
- "renesas,gpio-rcar";
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@@ -192,7 +192,7 @@

gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7743",
- "renesas,gpio-rcar";
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@@ -206,7 +206,7 @@

gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7743",
- "renesas,gpio-rcar";
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
--
2.7.4


[PATCH 44/86] ARM: dts: r8a7745: Add GPIO support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Describe GPIO blocks in the R8A7745 device tree.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 3163c03ec37aef502474122b857452fb948c7596)
(moved DT nodes to the top of soc node. removed resets properties.
modified power-domains and clocks properties)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 98 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 0b1b5b4..112a612 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -45,6 +45,104 @@
#size-cells = <2>;
ranges;

+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7745",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7745_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7745",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7745_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7745",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7745_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7745",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7745_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7745",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7745_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7745",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 28>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7745_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7745",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7745_CLK_GPIO6>;
+ power-domains = <&cpg_clocks>;
+ };
+
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7745";
reg = <0 0xe6060000 0 0x11c>;
--
2.7.4


[PATCH 43/86] gpio: rcar: add gen[123] fallback compatibility strings

Fabrizio Castro <fabrizio.castro@...>
 

From: Simon Horman <horms+renesas@...>

Add fallback compatibility string for R-Car Gen 1, 2 and 3.

In the case of Renesas R-Car hardware we know that there are generations of
SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship
between IP blocks might be. For example, I believe that r8a7790 is older
than r8a7791 but that doesn't imply that the latter is a descendant of the
former or vice versa.

We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.

For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme being adopted for
drivers for Renesas SoCs.

Also deprecate renesas,gpio-rcar as its name is more generic than its
implementation.

Signed-off-by: Simon Horman <horms+renesas@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Linus Walleij <linus.walleij@...>
(cherry picked from commit dbd1dad2ab8ffca57e0aa386df0d7ec621c26ca8)
(taken out R-Car Gen3 support)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
.../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 14 ++++++++++----
drivers/gpio/gpio-rcar.c | 6 ++++++
2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index 046fef9..68eb3a8 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -2,7 +2,7 @@

Required Properties:

- - compatible: should contain one of the following.
+ - compatible: should contain one or more of the following:
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
- "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
- "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
@@ -12,7 +12,13 @@ Required Properties:
- "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller.
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
- - "renesas,gpio-rcar": for generic R-Car GPIO controller.
+ - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
+ - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
+ - "renesas,gpio-rcar": deprecated.
+
+ When compatible with the generic version nodes must list the
+ SoC-specific version corresponding to the platform first followed by
+ the generic version.

- reg: Base address and length of each memory resource used by the GPIO
controller hardware module.
@@ -42,7 +48,7 @@ interrupt-controller/interrupts.txt.
Example: R8A7779 (R-Car H1) GPIO controller nodes

gpio0: gpio@ffc40000 {
- compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+ compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc40000 0x2c>;
interrupt-parent = <&gic>;
interrupts = <0 141 0x4>;
@@ -54,7 +60,7 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes
};
...
gpio6: gpio@ffc46000 {
- compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+ compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc46000 0x2c>;
interrupt-parent = <&gic>;
interrupts = <0 147 0x4>;
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 9555cd8..c0fd5a5 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -392,6 +392,12 @@ static const struct of_device_id gpio_rcar_of_table[] = {
/* Gen3 GPIO is identical to Gen2. */
.data = &gpio_rcar_info_gen2,
}, {
+ .compatible = "renesas,rcar-gen1-gpio",
+ .data = &gpio_rcar_info_gen1,
+ }, {
+ .compatible = "renesas,rcar-gen2-gpio",
+ .data = &gpio_rcar_info_gen2,
+ }, {
.compatible = "renesas,gpio-rcar",
.data = &gpio_rcar_info_gen1,
}, {
--
2.7.4


[PATCH 42/86] gpio: rcar: Add r8a7745 (RZ/G1E) support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Renesas RZ/G1E (R8A7745) SoC GPIO blocks are identical to the R-Car Gen2
family. Add support for its GPIO controllers.

Signed-off-by: Biju Das <biju.das@...>
Acked-by: Simon Horman <horms+renesas@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Acked-by: Rob Herring <robh@...>
Signed-off-by: Linus Walleij <linus.walleij@...>
(cherry picked from commit 33f5dc84680878fb077bd4bcab587e4a5ce228f7)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index 036fdb2..046fef9 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -4,6 +4,7 @@ Required Properties:

- compatible: should contain one of the following.
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
+ - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
- "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
--
2.7.4


[PATCH 41/86] ARM: dts: iwg22d-sodimm: Add pinctl support for scif4

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Adding pinctrl support for scif4 interface.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 67dbb081815e013e1e7911305b43b44537a78ed2)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index cbc19fe..442a5cb 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -24,6 +24,16 @@
};
};

+&pfc {
+ scif4_pins: scif4 {
+ groups = "scif4_data_b";
+ function = "scif4";
+ };
+};
+
&scif4 {
+ pinctrl-0 = <&scif4_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
--
2.7.4


[PATCH 40/86] ARM: dts: r8a7745: add PFC support

Fabrizio Castro <fabrizio.castro@...>
 

From: Sergei Shtylyov <sergei.shtylyov@...>

Define the generic R8A7745 part of the PFC device node.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 95b94ed9abb58d2f5372a980a0af037e76c0beaf)
(moved pfc node to improve DT nodes sorting)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index e5dcbca..0b1b5b4 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the r8a7745 SoC
*
- * Copyright (C) 2016 Cogent Embedded Inc.
+ * Copyright (C) 2016-2017 Cogent Embedded Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -45,6 +45,11 @@
#size-cells = <2>;
ranges;

+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7745";
+ reg = <0 0xe6060000 0 0x11c>;
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4


[PATCH 39/86] pinctrl: sh-pfc: r8a7794: Add i2c5 pin groups and function

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Add i2c5 pin groups and function to r8a7745 PFC driver.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
(cherry picked from commit 0d68d46035a196c91ee70df2ba204ed708bba315)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 41 ++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index fb4ae85..1b8cb3b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -2245,6 +2245,35 @@ static const unsigned int i2c4_e_pins[] = {
static const unsigned int i2c4_e_mux[] = {
I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
};
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+};
+static const unsigned int i2c5_mux[] = {
+ I2C5_SCL_MARK, I2C5_SDA_MARK,
+};
+static const unsigned int i2c5_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int i2c5_b_mux[] = {
+ I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
+};
+static const unsigned int i2c5_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int i2c5_c_mux[] = {
+ I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
+};
+static const unsigned int i2c5_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int i2c5_d_mux[] = {
+ I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
+};
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ0 */
@@ -3838,6 +3867,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c4_c),
SH_PFC_PIN_GROUP(i2c4_d),
SH_PFC_PIN_GROUP(i2c4_e),
+ SH_PFC_PIN_GROUP(i2c5),
+ SH_PFC_PIN_GROUP(i2c5_b),
+ SH_PFC_PIN_GROUP(i2c5_c),
+ SH_PFC_PIN_GROUP(i2c5_d),
SH_PFC_PIN_GROUP(intc_irq0),
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2),
@@ -4213,6 +4246,13 @@ static const char * const i2c4_groups[] = {
"i2c4_e",
};

+static const char * const i2c5_groups[] = {
+ "i2c5",
+ "i2c5_b",
+ "i2c5_c",
+ "i2c5_d",
+};
+
static const char * const intc_groups[] = {
"intc_irq0",
"intc_irq1",
@@ -4554,6 +4594,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(msiof0),
--
2.7.4

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