Date   

[PATCH 18/86] ARM: DTS: Fix register map for virt-capable GIC

Fabrizio Castro <fabrizio.castro@...>
 

From: Marc Zyngier <marc.zyngier@...>

Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.

Acked-by: Shawn Guo <shawnguo@...>
Acked-by: Tony Lindgren <tony@...>
Acked-by: Santosh Shilimkar <ssantosh@...>
Acked-by: Krzysztof Kozlowski <krzk@...>
Acked-by: Maxime Ripard <maxime.ripard@...>
Acked-by: Antoine Tenart <antoine.tenart@...>
Acked-by: Arnd Bergmann <arnd@...>
Acked-by: Matthias Brugger <matthias.bgg@...>
Acked-by: Heiko Stuebner <heiko@...>
Reviewed-by: Javier Martinez Canillas <javier@...>
Signed-off-by: Marc Zyngier <marc.zyngier@...>
Signed-off-by: Arnd Bergmann <arnd@...>
(cherry picked from commit 387720c93812f1e702c20c667cb003a356e24a6c)
(Backported only for r8a7745)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 62dd97e..8cfc644 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -52,7 +52,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
--
2.7.4


[PATCH 17/86] ARM: dts: r8a7745: Link ARM GIC to clock and clock domain

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Link the ARM GIC to the INTC-SYS module clock, and add it to the SYSC
"always-on" PM Domain, so it can be power managed using that clock.

Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit db017f399639f68827edc954205803272ef20b24)
(updated clocks and power-domains properties)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index ff7ebb2..62dd97e 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -57,6 +57,9 @@
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&mstp4_clks R8A7745_CLK_INTC_SYS>;
+ clock-names = "clk";
+ power-domains = <&cpg_clocks>;
};

irqc: interrupt-controller@e61c0000 {
--
2.7.4


[PATCH 16/86] ARM: dts: r8a7745: add IRQC support

Fabrizio Castro <fabrizio.castro@...>
 

From: Sergei Shtylyov <sergei.shtylyov@...>

Describe the IRQC interrupt controller in the R8A7745 device tree.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@...>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 28c43fbb3ca0a9a8f547aece94dac8d791358444)
(updated clocks and power-domains properties)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 83fba9a..ff7ebb2 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -59,6 +59,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};

+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7745", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A7745_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
--
2.7.4


[PATCH 15/86] ARM: dts: r8a7745: add Ether support

Fabrizio Castro <fabrizio.castro@...>
 

From: Sergei Shtylyov <sergei.shtylyov@...>

Define the generic R8A7745 part of the Ether device node.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@...>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit bed98a59b62d3e121da2d8372425fd4e424b0aa6)
(updated clocks and power-domains properties)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index f9bfa40..83fba9a 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -378,6 +378,18 @@
status = "disabled";
};

+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7745";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7745_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
--
2.7.4


[PATCH 14/86] ARM: dts: r8a7745: add [H]SCIF{|A|B} support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Describe [H]SCIF{|A|B} ports in the R8A7745 device tree.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@...>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
[simon: consistently use tabs for indentation]
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit e0d2da54c4d01ba27a4f50c9da94f7a011c6056b)
(updated clocks, clock-names and power-domains properties)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 243 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 243 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 0b6d5e7..f9bfa40 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -135,6 +135,249 @@
dma-channels = <15>;
};

+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7745", "renesas,scifa";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7745_CLK_SCIFA0>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7745", "renesas,scifa";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7745_CLK_SCIFA1>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7745", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7745_CLK_SCIFA2>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7745", "renesas,scifa";
+ reg = <0 0xe6c70000 0 0x40>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7745_CLK_SCIFA3>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7745", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7745_CLK_SCIFA4>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7745", "renesas,scifa";
+ reg = <0 0xe6c80000 0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7745_CLK_SCIFA5>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7745", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7745_CLK_SCIFB0>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7745", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7745_CLK_SCIFB1>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7745", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7745_CLK_SCIFB2>;
+ clock-names = "sci_ick";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7745", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_SCIF0>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7745", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_SCIF1>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7745", "renesas,scif";
+ reg = <0 0xe6e58000 0 0x40>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_SCIF2>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7745", "renesas,scif";
+ reg = <0 0xe6ea8000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_SCIF3>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7745", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_SCIF4>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7745", "renesas,scif";
+ reg = <0 0xe6ee8000 0 0x40>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_SCIF5>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7745", "renesas,hscif";
+ reg = <0 0xe62c0000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_HSCIF0>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7745", "renesas,hscif";
+ reg = <0 0xe62c8000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_HSCIF1>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7745", "renesas,hscif";
+ reg = <0 0xe62d0000 0 0x60>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7745_CLK_HSCIF2>,
+ <&zs_clk>, <&scif_clk>;
+ clock-names = "sci_ick", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
--
2.7.4


[PATCH 13/86] ARM: dts: r8a7745: add SYS-DMAC support

Fabrizio Castro <fabrizio.castro@...>
 

From: Sergei Shtylyov <sergei.shtylyov@...>

Describe SYS-DMAC0/1 in the R8A7745 device tree.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@...>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 06a80bad04291b6e305ef521550581d62b4656a3)
(updated clocks and power-domains property)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 5c50fd3..0b6d5e7 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -71,6 +71,70 @@
IRQ_TYPE_LEVEL_LOW)>;
};

+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&mstp2_clks R8A7745_CLK_SYS_DMAC0>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&mstp2_clks R8A7745_CLK_SYS_DMAC1>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
--
2.7.4


[PATCH 12/86] ARM: dts: r8a7745: Add clocks

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Declare all core clocks and DIV6 clocks, as well as all MSTP clocks.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 432 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 432 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 281ab59..5c50fd3 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -10,6 +10,7 @@

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7745-clock.h>

/ {
compatible = "renesas,r8a7745";
@@ -25,6 +26,7 @@
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
+ clocks = <&z2_clk>;
next-level-cache = <&L2_CA7>;
};

@@ -68,6 +70,436 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>;
};
+
+ clocks {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Special CPG clocks */
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7745-cpg-clocks",
+ "renesas,rcar-gen2-cpg-clocks";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk &usb_extal_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "main", "pll0", "pll1",
+ "pll3", "lb", "qspi",
+ "sdh", "sd0", "rcan";
+ #power-domain-cells = <0>;
+ };
+
+ /* Variable factor clocks */
+ sd2_clk: sd2_clk@e6150078 {
+ compatible = "renesas,r8a7745-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe6150078 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sd2";
+ };
+ sd3_clk: sd3_clk@e615026c {
+ compatible = "renesas,r8a7745-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe615026c 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sd3";
+ };
+ mmc0_clk: mmc0_clk@e6150240 {
+ compatible = "renesas,r8a7745-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe6150240 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "mmc0";
+ };
+
+ /* Fixed factor clocks */
+ pll1_div2_clk: pll1_div2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "pll1_div2";
+ };
+ z2_clk: z2 {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL0>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "z2";
+ };
+ zg_clk: zg_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <6>;
+ clock-mult = <1>;
+ clock-output-names = "zg";
+ };
+ zx_clk: zx_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <3>;
+ clock-mult = <1>;
+ clock-output-names = "zx";
+ };
+ zs_clk: zs_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <6>;
+ clock-mult = <1>;
+ clock-output-names = "zs";
+ };
+ hp_clk: hp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ clock-output-names = "hp";
+ };
+ b_clk: b_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ clock-output-names = "b";
+ };
+ p_clk: p_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <24>;
+ clock-mult = <1>;
+ clock-output-names = "p";
+ };
+ cl_clk: cl_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <48>;
+ clock-mult = <1>;
+ clock-output-names = "cl";
+ };
+ cp_clk: cp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <48>;
+ clock-mult = <1>;
+ clock-output-names = "cp";
+ };
+ m2_clk: m2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "m2";
+ };
+ zb3_clk: zb3_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "zb3";
+ };
+ zb3d2_clk: zb3d2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "zb3d2";
+ };
+ ddr_clk: ddr_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "ddr";
+ };
+ mp_clk: mp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-div = <15>;
+ clock-mult = <1>;
+ clock-output-names = "mp";
+ };
+ cpex_clk: cpex_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&extal_clk>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "cpex";
+ };
+ rclk_clk: rclk_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <(48 * 1024)>;
+ clock-mult = <1>;
+ clock-output-names = "rclk";
+ };
+ oscclk_clk: oscclk_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7745_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <(12 * 1024)>;
+ clock-mult = <1>;
+ clock-output-names = "oscclk";
+ };
+
+ /* Gate clocks */
+ mstp0_clks: mstp0_clks@e6150130 {
+ compatible = "renesas,r8a7745-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+ clocks = <&mp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7745_CLK_MSIOF0>;
+ clock-output-names = "msiof0";
+ };
+ mstp1_clks: mstp1_clks@e6150134 {
+ compatible = "renesas,r8a7745-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+ clocks = <&zs_clk>, <&zs_clk>, <&p_clk>,
+ <&zg_clk>, <&zs_clk>, <&zs_clk>,
+ <&p_clk>, <&p_clk>, <&rclk_clk>,
+ <&cp_clk>, <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_VCP0 R8A7745_CLK_VPC0
+ R8A7745_CLK_TMU1 R8A7745_CLK_3DG
+ R8A7745_CLK_2DDMAC R8A7745_CLK_FDP1_0
+ R8A7745_CLK_TMU3 R8A7745_CLK_TMU2
+ R8A7745_CLK_CMT0 R8A7745_CLK_TMU0
+ R8A7745_CLK_VSP1DU0 R8A7745_CLK_VSP1_SY
+ >;
+ clock-output-names =
+ "vcp0", "vpc0", "tmu1", "3dg",
+ "2ddmac", "fdp1-0", "tmu3",
+ "tmu2", "cmt0", "tmu0",
+ "vsp1-du0", "vsp1-sy";
+ };
+ mstp2_clks: mstp2_clks@e6150138 {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+ clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>,
+ <&mp_clk>, <&mp_clk>, <&mp_clk>,
+ <&mp_clk>, <&mp_clk>, <&zs_clk>,
+ <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_SCIFA2 R8A7745_CLK_SCIFA1
+ R8A7745_CLK_SCIFA0 R8A7745_CLK_MSIOF2
+ R8A7745_CLK_SCIFB0 R8A7745_CLK_SCIFB1
+ R8A7745_CLK_MSIOF1 R8A7745_CLK_SCIFB2
+ R8A7745_CLK_SYS_DMAC1
+ R8A7745_CLK_SYS_DMAC0
+ >;
+ clock-output-names =
+ "scifa2", "scifa1", "scifa0", "msiof2",
+ "scifb0", "scifb1", "msiof1", "scifb2",
+ "sys-dmac1", "sys-dmac0";
+ };
+ mstp3_clks: mstp3_clks@e615013c {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+ clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
+ <&cpg_clocks R8A7745_CLK_SD0>,
+ <&mmc0_clk>, <&hp_clk>, <&hp_clk>,
+ <&rclk_clk>, <&hp_clk>, <&hp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_TPU0 R8A7745_CLK_SDHI2
+ R8A7745_CLK_SDHI1 R8A7745_CLK_SDHI0
+ R8A7745_CLK_MMCIF0 R8A7745_CLK_IIC0
+ R8A7745_CLK_IIC1 R8A7745_CLK_CMT1
+ R8A7745_CLK_USBHS_DMAC0
+ R8A7745_CLK_USBHS_DMAC1
+ >;
+ clock-output-names =
+ "tpu0", "sdhi3", "sdhi2", "sdhi0",
+ "mmcif0", "i2c6", "i2c7", "cmt1",
+ "usbdmac0", "usbdmac1";
+ };
+ mstp4_clks: mstp4_clks@e6150140 {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+ clocks = <&cp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_IRQC
+ >;
+ clock-output-names = "irqc";
+ };
+ mstp5_clks: mstp5_clks@e6150144 {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+ clocks = <&hp_clk>, <&p_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_AUDIO_DMAC0
+ R8A7745_CLK_PWM
+ >;
+ clock-output-names = "audmac0", "pwm";
+ };
+ mstp7_clks: mstp7_clks@e615014c {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+ clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>,
+ <&p_clk>, <&p_clk>, <&zs_clk>,
+ <&zs_clk>, <&p_clk>, <&p_clk>,
+ <&p_clk>, <&p_clk>, <&zx_clk>,
+ <&zx_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_USB_EHCI R8A7745_CLK_USBHS
+ R8A7745_CLK_HSCIF2 R8A7745_CLK_SCIF5
+ R8A7745_CLK_SCIF4 R8A7745_CLK_HSCIF1
+ R8A7745_CLK_HSCIF0 R8A7745_CLK_SCIF3
+ R8A7745_CLK_SCIF2 R8A7745_CLK_SCIF1
+ R8A7745_CLK_SCIF0 R8A7745_CLK_DU1
+ R8A7745_CLK_DU0
+ >;
+ clock-output-names =
+ "ehci", "hsusb", "hscif2", "scif5",
+ "scif4", "hscif1", "hscif0", "scif3",
+ "scif2", "scif1", "scif0", "du1",
+ "du0";
+ };
+ mstp8_clks: mstp8_clks@e6150990 {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+ clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>,
+ <&hp_clk>, <&p_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_IPMMU_SGX
+ R8A7745_CLK_VIN1 R8A7745_CLK_VIN0
+ R8A7745_CLK_ETHERAVB R8A7745_CLK_ETHER
+ >;
+ clock-output-names =
+ "ipmmu_sgx", "vin1", "vin0",
+ "etheravb", "ether";
+ };
+ mstp9_clks: mstp9_clks@e6150994 {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+ clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ <&cp_clk>, <&p_clk>, <&p_clk>,
+ <&cpg_clocks R8A7745_CLK_QSPI>,
+ <&hp_clk>, <&hp_clk>, <&hp_clk>,
+ <&hp_clk>, <&hp_clk>, <&hp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_GPIO6 R8A7745_CLK_GPIO5
+ R8A7745_CLK_GPIO4 R8A7745_CLK_GPIO3
+ R8A7745_CLK_GPIO2 R8A7745_CLK_GPIO1
+ R8A7745_CLK_GPIO0 R8A7745_CLK_RCAN1
+ R8A7745_CLK_RCAN0 R8A7745_CLK_QSPI_MOD
+ R8A7745_CLK_I2C5 R8A7745_CLK_I2C4
+ R8A7745_CLK_I2C3 R8A7745_CLK_I2C2
+ R8A7745_CLK_I2C1 R8A7745_CLK_I2C0
+ >;
+ clock-output-names =
+ "gpio6", "gpio5", "gpio4", "gpio3",
+ "gpio2", "gpio1", "gpio0", "rcan1",
+ "rcan0", "qspi_mod", "i2c5", "i2c4",
+ "i2c3", "i2c2", "i2c1", "i2c0";
+ };
+ mstp10_clks: mstp10_clks@e6150998 {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+ clocks = <&p_clk>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7745_CLK_SSI_ALL>,
+ <&p_clk>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7745_CLK_SCU_ALL>;
+
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_SSI_ALL
+ R8A7745_CLK_SSI9 R8A7745_CLK_SSI8
+ R8A7745_CLK_SSI7 R8A7745_CLK_SSI6
+ R8A7745_CLK_SSI5 R8A7745_CLK_SSI4
+ R8A7745_CLK_SSI3 R8A7745_CLK_SSI2
+ R8A7745_CLK_SSI1 R8A7745_CLK_SSI0
+ R8A7745_CLK_SCU_ALL
+ R8A7745_CLK_SCU_DVC1
+ R8A7745_CLK_SCU_DVC0
+ R8A7745_CLK_SCU_CTU1_MIX1
+ R8A7745_CLK_SCU_CTU0_MIX0
+ R8A7745_CLK_SCU_SRC6
+ R8A7745_CLK_SCU_SRC5
+ R8A7745_CLK_SCU_SRC4
+ R8A7745_CLK_SCU_SRC3
+ R8A7745_CLK_SCU_SRC2
+ R8A7745_CLK_SCU_SRC1
+ >;
+ clock-output-names =
+ "ssi-all",
+ "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+ "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+ "scu-all",
+ "scu-dvc1", "scu-dvc0",
+ "scu-ctu1-mix1", "scu-ctu0-mix0",
+ "scu-src6", "scu-src5", "scu-src4",
+ "scu-src3", "scu-src2", "scu-src1";
+ };
+ mstp11_clks: mstp11_clks@e615099c {
+ compatible = "renesas,r8a7743-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+ clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7745_CLK_SCIFA3 R8A7745_CLK_SCIFA4
+ R8A7745_CLK_SCIFA5
+ >;
+ clock-output-names = "scifa3", "scifa4",
+ "scifa5";
+ };
+ };
};

/* External root clock */
--
2.7.4


[PATCH 11/86] ARM: dts: r8a7745: initial SoC device tree

Fabrizio Castro <fabrizio.castro@...>
 

From: Sergei Shtylyov <sergei.shtylyov@...>

The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@...>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit c95360247bdd67d39b55f7e743153efa64e4efe3)
(removed SYSC, RST and CPG nodes)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7745.dtsi | 95 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7745.dtsi

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
new file mode 100644
index 0000000..281ab59
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -0,0 +1,95 @@
+/*
+ * Device Tree Source for the r8a7745 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "renesas,r8a7745";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clock-frequency = <1000000000>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ L2_CA7: cache-controller@0 {
+ compatible = "cache";
+ reg = <0>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
--
2.7.4


[PATCH 10/86] ARM: shmobile: r8a7745: Add clock index macros for DT sources

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Add macros usable by device tree sources to reference r8a7745 clocks by
index.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
include/dt-bindings/clock/r8a7745-clock.h | 147 ++++++++++++++++++++++++++++++
1 file changed, 147 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a7745-clock.h

diff --git a/include/dt-bindings/clock/r8a7745-clock.h b/include/dt-bindings/clock/r8a7745-clock.h
new file mode 100644
index 0000000..4f50412
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7745-clock.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2018 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7745_H__
+#define __DT_BINDINGS_CLOCK_R8A7745_H__
+
+/* CPG */
+#define R8A7745_CLK_MAIN 0
+#define R8A7745_CLK_PLL0 1
+#define R8A7745_CLK_PLL1 2
+#define R8A7745_CLK_PLL3 3
+#define R8A7745_CLK_LB 4
+#define R8A7745_CLK_QSPI 5
+#define R8A7745_CLK_SDH 6
+#define R8A7745_CLK_SD0 7
+#define R8A7745_CLK_Z2 8
+#define R8A7745_CLK_RCAN 9
+
+/* MSTP0 */
+#define R8A7745_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7745_CLK_VCP0 1
+#define R8A7745_CLK_VPC0 3
+#define R8A7745_CLK_ADG 6
+#define R8A7745_CLK_TMU1 11
+#define R8A7745_CLK_3DG 12
+#define R8A7745_CLK_2DDMAC 15
+#define R8A7745_CLK_FDP1_0 19
+#define R8A7745_CLK_TMU3 21
+#define R8A7745_CLK_TMU2 22
+#define R8A7745_CLK_CMT0 24
+#define R8A7745_CLK_TMU0 25
+#define R8A7745_CLK_VSP1DU0 28
+#define R8A7745_CLK_VSP1_SY 31
+
+/* MSTP2 */
+#define R8A7745_CLK_SCIFA2 2
+#define R8A7745_CLK_SCIFA1 3
+#define R8A7745_CLK_SCIFA0 4
+#define R8A7745_CLK_MSIOF2 5
+#define R8A7745_CLK_SCIFB0 6
+#define R8A7745_CLK_SCIFB1 7
+#define R8A7745_CLK_MSIOF1 8
+#define R8A7745_CLK_SCIFB2 16
+#define R8A7745_CLK_SYS_DMAC1 18
+#define R8A7745_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7745_CLK_TPU0 4
+#define R8A7745_CLK_SDHI2 11
+#define R8A7745_CLK_SDHI1 12
+#define R8A7745_CLK_SDHI0 14
+#define R8A7745_CLK_MMCIF0 15
+#define R8A7745_CLK_IIC0 18
+#define R8A7745_CLK_IIC1 23
+#define R8A7745_CLK_CMT1 29
+#define R8A7745_CLK_USBHS_DMAC0 30
+#define R8A7745_CLK_USBHS_DMAC1 31
+
+/* MSTP4 */
+#define R8A7745_CLK_RWDT 2
+#define R8A7745_CLK_USB_DDM 6
+#define R8A7745_CLK_IRQC 7
+#define R8A7745_CLK_INTC_SYS 8
+
+/* MSTP5 */
+#define R8A7745_CLK_AUDIO_DMAC0 2
+#define R8A7745_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7745_CLK_USB_EHCI 3
+#define R8A7745_CLK_USBHS 4
+#define R8A7745_CLK_HSCIF2 13
+#define R8A7745_CLK_SCIF5 14
+#define R8A7745_CLK_SCIF4 15
+#define R8A7745_CLK_HSCIF1 16
+#define R8A7745_CLK_HSCIF0 17
+#define R8A7745_CLK_SCIF3 18
+#define R8A7745_CLK_SCIF2 19
+#define R8A7745_CLK_SCIF1 20
+#define R8A7745_CLK_SCIF0 21
+#define R8A7745_CLK_DU1 23
+#define R8A7745_CLK_DU0 24
+
+/* MSTP8 */
+#define R8A7745_CLK_IPMMU_SGX 0
+#define R8A7745_CLK_VIN1 10
+#define R8A7745_CLK_VIN0 11
+#define R8A7745_CLK_ETHERAVB 12
+#define R8A7745_CLK_ETHER 13
+#define R8A7745_CLK_DCU 30
+
+/* MSTP9 */
+#define R8A7745_CLK_GPIO6 5
+#define R8A7745_CLK_GPIO5 7
+#define R8A7745_CLK_GPIO4 8
+#define R8A7745_CLK_GPIO3 9
+#define R8A7745_CLK_GPIO2 10
+#define R8A7745_CLK_GPIO1 11
+#define R8A7745_CLK_GPIO0 12
+#define R8A7745_CLK_RCAN1 15
+#define R8A7745_CLK_RCAN0 16
+#define R8A7745_CLK_QSPI_MOD 17
+#define R8A7745_CLK_I2C5 25
+#define R8A7745_CLK_I2C4 27
+#define R8A7745_CLK_I2C3 28
+#define R8A7745_CLK_I2C2 29
+#define R8A7745_CLK_I2C1 30
+#define R8A7745_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7745_CLK_SSI_ALL 5
+#define R8A7745_CLK_SSI9 6
+#define R8A7745_CLK_SSI8 7
+#define R8A7745_CLK_SSI7 8
+#define R8A7745_CLK_SSI6 9
+#define R8A7745_CLK_SSI5 10
+#define R8A7745_CLK_SSI4 11
+#define R8A7745_CLK_SSI3 12
+#define R8A7745_CLK_SSI2 13
+#define R8A7745_CLK_SSI1 14
+#define R8A7745_CLK_SSI0 15
+#define R8A7745_CLK_SCU_ALL 17
+#define R8A7745_CLK_SCU_DVC1 18
+#define R8A7745_CLK_SCU_DVC0 19
+#define R8A7745_CLK_SCU_CTU1_MIX1 20
+#define R8A7745_CLK_SCU_CTU0_MIX0 21
+#define R8A7745_CLK_SCU_SRC6 25
+#define R8A7745_CLK_SCU_SRC5 26
+#define R8A7745_CLK_SCU_SRC4 27
+#define R8A7745_CLK_SCU_SRC3 28
+#define R8A7745_CLK_SCU_SRC2 29
+#define R8A7745_CLK_SCU_SRC1 30
+
+/* MSTP11 */
+#define R8A7745_CLK_SCIFA3 6
+#define R8A7745_CLK_SCIFA4 7
+#define R8A7745_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7745_H__ */
--
2.7.4


[PATCH 09/86] clk: shmobile: Document r8a7745 MSTP clock support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Document r8a7745 MSTP clock support.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index f444798a..6e2c6ae 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -14,6 +14,7 @@ Required Properties:
- "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
- "renesas,r8a7743-mstp-clocks" for R8A7743 (RZ/G1M) MSTP gate clocks
+ - "renesas,r8a7745-mstp-clocks" for R8A7745 (RZ/G1E) MSTP gate clocks
- "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
--
2.7.4


[PATCH 08/86] clk: shmobile: Document r8a7745 CPG DIV6 clock support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Document r8a7745 CPG DIV6 clock support.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 2990615..feb9ab5 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -10,6 +10,7 @@ Required Properties:
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
- "renesas,r8a7743-div6-clock" for R8A7743 (RZ/G1M) DIV6 clocks
+ - "renesas,r8a7745-div6-clock" for R8A7745 (RZ/G1E) DIV6 clocks
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
- "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
--
2.7.4


[PATCH 07/86] clk: shmobile: Document r8a7745 CPG clock support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Document r8a7745 CPG clock support.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 986b8a1..a75c26a 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -9,6 +9,7 @@ Required Properties:

- compatible: Must be one of
- "renesas,r8a7743-cpg-clocks" for the r8a7743 CPG
+ - "renesas,r8a7745-cpg-clocks" for the r8a7745 CPG
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
--
2.7.4


[PATCH 06/86] ARM: shmobile: document iW-RainboW-G22D SODIMM SOM Development Platform

Fabrizio Castro <fabrizio.castro@...>
 

Document the iW-RainboW-G22D device tree bindings.
It is just a placeholder for the time being, the actual
implementation is not available yet.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 61c687e8223f842ed71267ad142f5a920b32213d)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index ed0fb82..e27b38e 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -49,6 +49,8 @@ Boards:
compatible = "renesas,gose", "renesas,r8a7793"
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
+ - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
+ compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
compatible = "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
--
2.7.4


[PATCH 05/86] ARM: shmobile: document iW-RainboW-G22M-SM SODIMM System on Module

Fabrizio Castro <fabrizio.castro@...>
 

Document the iW-RainboW-G22M-SM SODIMM System on Module device tree
bindings. It is just a placeholder for the time being, the actual
implementation is not available yet.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 9933924781c2b27dfd8c43c1c12abb450b33094b)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 7ec024c..ed0fb82 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -49,6 +49,8 @@ Boards:
compatible = "renesas,gose", "renesas,r8a7793"
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
+ - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
+ compatible = "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
--
2.7.4


[PATCH 04/86] clk: shmobile: rcar-gen2: Add RZ/G1E to pll0_mult_match list

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

RZ/G1E doesn't have the PLL0CR register, but uses a fixed multiplier
(depending on mode pins) and divider similar to R-Car E2. Add RZ/G1E
to pll0_mult_match list.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/clk/shmobile/clk-rcar-gen2.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index a874c66..636070b 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -301,6 +301,7 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
static u32 cpg_mode __initdata;

static const char * const pll0_mult_match[] = {
+ "renesas,r8a7745-cpg-clocks",
"renesas,r8a7792-cpg-clocks",
"renesas,r8a7794-cpg-clocks",
NULL
--
2.7.4


[PATCH 03/86] clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

R-Car V2H and E2 do not have the PLL0CR register, but use a fixed
multiplier (depending on mode pins) and divider.

This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on
R-Car V2H and E2 from 1.5 GHz to 1 GHz.

Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G
Clock Pulse Generator support core.

Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Fixes: 0dce5454d5c25858 ("ARM: shmobile: Initial r8a7794 SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
(cherry picked from commit b7c563c489e94417efbad68d057ea5d2030ae44c)
(modified file path)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/clk/shmobile/clk-rcar-gen2.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index 745496f..a874c66 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -271,11 +271,14 @@ struct cpg_pll_config {
unsigned int extal_div;
unsigned int pll1_mult;
unsigned int pll3_mult;
+ unsigned int pll0_mult; /* For R-Car V2H and E2 only */
};

static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
- { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
- { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
+ { 1, 208, 106, 200 }, { 1, 208, 88, 200 },
+ { 1, 156, 80, 150 }, { 1, 156, 66, 150 },
+ { 2, 240, 122, 230 }, { 2, 240, 102, 230 },
+ { 2, 208, 106, 200 }, { 2, 208, 88, 200 },
};

/* SDHI divisors */
@@ -297,6 +300,12 @@ static const struct clk_div_table cpg_sd01_div_table[] = {

static u32 cpg_mode __initdata;

+static const char * const pll0_mult_match[] = {
+ "renesas,r8a7792-cpg-clocks",
+ "renesas,r8a7794-cpg-clocks",
+ NULL
+};
+
static struct clk * __init
rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
const struct cpg_pll_config *config,
@@ -317,9 +326,15 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
* clock implementation and we currently have no need to change
* the multiplier value.
*/
- u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
+ if (of_device_compatible_match(np, pll0_mult_match)) {
+ /* R-Car V2H and E2 do not have PLL0CR */
+ mult = config->pll0_mult;
+ div = 3;
+ } else {
+ u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
+ mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
+ }
parent_name = "main";
- mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
} else if (!strcmp(name, "pll1")) {
parent_name = "main";
mult = config->pll1_mult / 2;
--
2.7.4


[PATCH 02/86] dt: Add of_device_compatible_match()

Fabrizio Castro <fabrizio.castro@...>
 

From: Benjamin Herrenschmidt <benh@...>

This provides an equivalent of of_fdt_match() for non-flat trees.

This is more practical than matching an array of of_device_id structs
when converting a bunch of existing users of of_fdt_match().

Signed-off-by: Benjamin Herrenschmidt <benh@...>
Acked-by: Rob Herring <robh@...>
Signed-off-by: Michael Ellerman <mpe@...>
(cherry picked from commit b9c13fe32faaa71c4e4f8a426d79f8c93495e9f9)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/of/base.c | 22 ++++++++++++++++++++++
include/linux/of.h | 2 ++
2 files changed, 24 insertions(+)

diff --git a/drivers/of/base.c b/drivers/of/base.c
index 3134129..c8b01c9 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -498,6 +498,28 @@ int of_device_is_compatible(const struct device_node *device,
}
EXPORT_SYMBOL(of_device_is_compatible);

+/** Checks if the device is compatible with any of the entries in
+ * a NULL terminated array of strings. Returns the best match
+ * score or 0.
+ */
+int of_device_compatible_match(struct device_node *device,
+ const char *const *compat)
+{
+ unsigned int tmp, score = 0;
+
+ if (!compat)
+ return 0;
+
+ while (*compat) {
+ tmp = of_device_is_compatible(device, *compat);
+ if (tmp > score)
+ score = tmp;
+ compat++;
+ }
+
+ return score;
+}
+
/**
* of_machine_is_compatible - Test root of device tree for a given compatible value
* @compat: compatible string to look for in root node's compatible property.
diff --git a/include/linux/of.h b/include/linux/of.h
index dd10626..4954287 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -307,6 +307,8 @@ extern int of_property_read_string_helper(struct device_node *np,
const char **out_strs, size_t sz, int index);
extern int of_device_is_compatible(const struct device_node *device,
const char *);
+extern int of_device_compatible_match(struct device_node *device,
+ const char *const *compat);
extern bool of_device_is_available(const struct device_node *device);
extern bool of_device_is_big_endian(const struct device_node *device);
extern const void *of_get_property(const struct device_node *node,
--
2.7.4


[PATCH 01/86] ARM: shmobile: rcar-gen2: Correct arch timer frequency on RZ/G1E

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

According to the datasheet, the frequency of the ARM architecture timer
on RZ/G1E depends on the frequency of the ZS clock, just like on R-Car
E2 and V2H.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit cd66fa4e0203fed9d8af6e1596ff8a68ede7fb1d)
(removed r8a7792 soc)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/mach-shmobile/setup-rcar-gen2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 3911716..549a66f 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -58,7 +58,8 @@ void __init rcar_gen2_timer_init(void)
int extal_mhz = 0;
u32 freq;

- if (of_machine_is_compatible("renesas,r8a7794")) {
+ if (of_machine_is_compatible("renesas,r8a7745") ||
+ of_machine_is_compatible("renesas,r8a7794")) {
freq = 260000000 / 8; /* ZS / 8 */
/* CNTVOFF has to be initialized either from non-secure
* Hypervisor mode or secure Monitor mode with SCR.NS==1.
--
2.7.4


[PATCH 00/86] First patch set for iwg22d

Fabrizio Castro <fabrizio.castro@...>
 

Dear Ben,

this series aims at adding initial support for the iwg22d, powered by
the RZ/G1E (r8a7745).
I hope this patch set is not too big, please let me know if you prefer
smaller chunks.

Thanks,
Fab

Andrey Gusakov (1):
pinctrl: sh-pfc: r8a7794: Fix GP2[29] muxing

Benjamin Herrenschmidt (1):
dt: Add of_device_compatible_match()

Biju Das (26):
clk: shmobile: rcar-gen2: Add RZ/G1E to pll0_mult_match list
clk: shmobile: Document r8a7745 CPG clock support
clk: shmobile: Document r8a7745 CPG DIV6 clock support
clk: shmobile: Document r8a7745 MSTP clock support
ARM: shmobile: r8a7745: Add clock index macros for DT sources
ARM: dts: r8a7745: Add clocks
ARM: dts: r8a7745: add [H]SCIF{|A|B} support
ARM: dts: iwg22m: Add iWave RZG1E SODIMM SOM
ARM: dts: iwg22d-sodimm: Add support for iWave G22D-SODIMM board
pinctrl: sh-pfc: r8a7794: Add i2c5 pin groups and function
ARM: dts: iwg22d-sodimm: Add pinctl support for scif4
gpio: rcar: Add r8a7745 (RZ/G1E) support
ARM: dts: r8a7745: Add GPIO support
dt-bindings: net: ravb : Add support for r8a7745 SoC
ARM: dts: r8a7745: Add Ethernet AVB support
ARM: dts: iwg22d-sodimm: Add Ethernet AVB support
ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core
ARM: dts: r8a7745: Add internal PCI bridge nodes
ARM: dts: r8a7745: Add USB PHY DT support
ARM: dts: r8a7745: Link PCI USB devices to USB PHY
ARM: dts: iwg22d-sodimm: Enable internal PCI
ARM: dts: iwg22d-sodimm: Enable USB PHY
ARM: dts: r8a7745: Add HS-USB device node
ARM: dts: iwg22d-sodimm: Enable HS-USB
ARM: dts: r8a7745: Add USB-DMAC device nodes
ARM: dts: r8a7745: Enable DMA for HSUSB

Fabrizio Castro (30):
ARM: shmobile: document iW-RainboW-G22M-SM SODIMM System on Module
ARM: shmobile: document iW-RainboW-G22D SODIMM SOM Development
Platform
pinctrl: sh-pfc: r8a7745: Add CAN[01] support
pinctrl: sh-pfc: r8a7794: Add can_clk function
pinctrl: sh-pfc: r8a7794: Add PWM[0123456] support
pinctrl: sh-pfc: r8a7794: Add tpu groups and function
ARM: dts: iwg22d: Use /dev/ttySC3 as debug console
dt-bindings: mmc: sh_mmcif: Document r8a7745 DT bindings
ARM: dts: r8a7745: Add MMC interface support
ARM: dts: iwg22m: Add eMMC support
ARM: debug-ll: Add support for r8a7745
ARM: shmobile: Add pm support for r8a7745
dt-bindings: apmu: Document r8a7745 support
ARM: dts: r8a7745: Add APMU node and second CPU core
ARM: dts: r8a7745: Add operating-points to cpu0
ARM: dts: r8a7745: Add I2C DT support
ARM: dts: r8a7745: Add IIC cores to dtsi
ARM: dts: iwg22m: Add RTC support
ARM: dts: r8a7745: Add SDHI controllers
ARM: dts: iwg22m: Enable SDHI1 controller
ARM: dts: iwg22d: Enable SDHI0 controller
ARM: dts: iwg22d: Add /dev/ttySC5 support
ARM: dts: iwg22d-sodimm-dbhd-ca: Add device tree for HDMI DB
ARM: dts: r8a7745: Add QSPI support
ARM: dts: iwg22m: Add SPI NOR support
of: add vendor prefix for Silicon Storage Technology Inc.
ARM: dts: r8a7745: Add MSIOF[012] support
drm: rcar-du: Add R8A7745 support
ARM: dts: r8a7745: Add DU support
ARM: dts: iwg22d-sodimm-dbhd-ca: Add HDMI video output

Geert Uytterhoeven (11):
ARM: shmobile: rcar-gen2: Correct arch timer frequency on RZ/G1E
clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2
ARM: dts: r8a7745: Link ARM GIC to clock and clock domain
ARM: dts: r8a7745: Fix SCIFB0 dmas indentation
ARM: dts: r8a7745: Remove unit-address and reg from integrated cache
pinctrl: sh-pfc: r8a7794: Use PINMUX_SINGLE() instead of raw
PINMUX_DATA()
pinctrl: sh-pfc: r8a7794: Add SCIF_CLK support
ARM: Add definition for monitor mode
ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
ARM: shmobile: rcar-gen2: Make rcar_gen2_dma_contiguous static
ARM: shmobile: Move shmobile_smp_{mpidr, fn, arg}[] from .text to .bss

Koji Matsuoka (1):
pinctrl: sh-pfc: r8a7794: Add DU pin groups

Marc Zyngier (1):
ARM: DTS: Fix register map for virt-capable GIC

Ryo Kataoka (2):
pinctrl: sh-pfc: r8a7794: Add SSI pin groups
pinctrl: sh-pfc: r8a7794: Add audio clock pin groups

Sergei Shtylyov (11):
ARM: dts: r8a7745: initial SoC device tree
ARM: dts: r8a7745: add SYS-DMAC support
ARM: dts: r8a7745: add Ether support
ARM: dts: r8a7745: add IRQC support
pinctrl: sh-pfc: r8a7794: Add EtherAVB pin groups
pinctrl: sh-pfc: r8a7794: Swap ATA signals
pinctrl: sh-pfc: r8a7794: Rename some I2C signals
pinctrl: sh-pfc: r8a7794: Remove AVB_AVTP_* groups
pinctrl: sh-pfc: r8a7794: Remove reserved bits
pinctrl: sh-pfc: r8a7794: Add R8A7745 support
ARM: dts: r8a7745: add PFC support

Simon Horman (2):
gpio: rcar: add gen[123] fallback compatibility strings
ARM: dts: r8a7743: Use R-Car GPIO Gen2 fallback compat string

Documentation/devicetree/bindings/arm/shmobile.txt | 4 +
.../bindings/clock/renesas,cpg-div6-clocks.txt | 1 +
.../bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
.../clock/renesas,rcar-gen2-cpg-clocks.txt | 1 +
.../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 15 +-
.../devicetree/bindings/mmc/renesas,mmcif.txt | 1 +
.../devicetree/bindings/net/renesas,ravb.txt | 1 +
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
.../devicetree/bindings/power/renesas,apmu.txt | 1 +
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm/Kconfig.debug | 10 +
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/r8a7743.dtsi | 16 +-
.../arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts | 146 ++
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 134 ++
arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 111 +
arch/arm/boot/dts/r8a7745.dtsi | 1391 +++++++++++
arch/arm/include/uapi/asm/ptrace.h | 1 +
arch/arm/mach-shmobile/Makefile | 1 +
arch/arm/mach-shmobile/common.h | 2 +
arch/arm/mach-shmobile/headsmp-apmu.S | 37 +
arch/arm/mach-shmobile/headsmp.S | 20 +-
arch/arm/mach-shmobile/platsmp-apmu.c | 2 +-
arch/arm/mach-shmobile/pm-rcar-gen2.c | 3 +
arch/arm/mach-shmobile/setup-rcar-gen2.c | 30 +-
drivers/clk/shmobile/clk-rcar-gen2.c | 24 +-
drivers/gpio/gpio-rcar.c | 6 +
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 23 +
drivers/of/base.c | 22 +
drivers/pinctrl/sh-pfc/Kconfig | 5 +
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c | 6 +
drivers/pinctrl/sh-pfc/core.h | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 2516 +++++++++++++++-----
include/dt-bindings/clock/r8a7745-clock.h | 147 ++
include/linux/of.h | 2 +
36 files changed, 3984 insertions(+), 702 deletions(-)
create mode 100644 arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
create mode 100644 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
create mode 100644 arch/arm/boot/dts/r8a7745-iwg22m.dtsi
create mode 100644 arch/arm/boot/dts/r8a7745.dtsi
create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S
create mode 100644 include/dt-bindings/clock/r8a7745-clock.h

--
2.7.4


[PATCH 3/3] media: dt-bindings: media: rcar_vin: add device tree support for r8a774[35]

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

Add compatible strings for r8a7743 and r8a7745. No driver change
is needed as "renesas,rcar-gen2-vin" will activate the right code.
However, it is good practice to document compatible strings for the
specific SoC as this allows SoC specific changes to the driver if
needed, in addition to document SoC support and therefore allow
checkpatch.pl to validate compatible string values.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Acked-by: Rob Herring <robh@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Acked-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Reviewed-by: Laurent Pinchart <laurent.pinchart@...>
Signed-off-by: Hans Verkuil <hans.verkuil@...>
Signed-off-by: Mauro Carvalho Chehab <mchehab@...>
(cherry picked from commit 1d14a5eaa156b0b3898c749fb3f9da1ebbc3f4aa)
(removed "renesas,rcar-gen3-vin" fallback)
Signed-off-by: Biju Das <biju.das@...>
---
Documentation/devicetree/bindings/media/rcar_vin.txt | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
index 18287b0..08eca2e 100644
--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
+++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
@@ -6,6 +6,8 @@ family of devices. The current blocks are always slaves and suppot one input
channel which can be either RGB, YUYV or BT656.

- compatible: Must be one or more of the following
+ - "renesas,vin-r8a7743" for the R8A7743 device
+ - "renesas,vin-r8a7745" for the R8A7745 device
- "renesas,vin-r8a7778" for the R8A7778 device
- "renesas,vin-r8a7779" for the R8A7779 device
- "renesas,vin-r8a7790" for the R8A7790 device
--
2.7.4

8281 - 8300 of 9573