Date   

[PATCH 1/4] spi: sh-msiof: Add R-Car Gen 2 and 3 fallback bindings

Fabrizio Castro <fabrizio.castro@...>
 

From: Simon Horman <horms+renesas@...>

In the case of Renesas R-Car hardware we know that there are generations of
SoCs, e.g. Gen 2 and Gen 3. But beyond that it's not clear what the
relationship between IP blocks might be. For example, I believe that
r8a7790 is older than r8a7791 but that doesn't imply that the latter is a
descendant of the former or vice versa.

We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.

For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme is being adopted for
drivers for Renesas SoCs.

Also:
* Deprecate renesas,sh-msiof. It seems poorly named as it is only
compatible with SH-Mobile. It also appears unused in mainline.

Signed-off-by: Simon Horman <horms+renesas@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Mark Brown <broonie@...>
(cherry picked from commit 4286db8456f4fa0c6af2b6b9abc5991a7e7da69c)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
(cherry picked from commit 77f252646eb0ec1e78847fe5725c98ee9e70b39e)
(removed "renesas,rcar-gen3-msiof")
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/spi/sh-msiof.txt | 18 ++++++++++++------
drivers/spi/spi-sh-msiof.c | 3 ++-
2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 705075d..ef65d54 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -1,15 +1,20 @@
Renesas MSIOF spi controller

Required properties:
-- compatible : "renesas,msiof-<soctype>" for SoCs,
- "renesas,sh-msiof" for SuperH, or
- "renesas,sh-mobile-msiof" for SH Mobile series.
- Examples with soctypes are:
- "renesas,msiof-r8a7790" (R-Car H2)
+- compatible : "renesas,msiof-r8a7790" (R-Car H2)
"renesas,msiof-r8a7791" (R-Car M2-W)
"renesas,msiof-r8a7792" (R-Car V2H)
"renesas,msiof-r8a7793" (R-Car M2-N)
"renesas,msiof-r8a7794" (R-Car E2)
+ "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
+ "renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device)
+ "renesas,sh-msiof" (deprecated)
+
+ When compatible with the generic version, nodes
+ must list the SoC-specific version corresponding
+ to the platform first followed by the generic
+ version.
+
- reg : A list of offsets and lengths of the register sets for
the device.
If only one register set is present, it is to be used
@@ -59,7 +64,8 @@ Documentation/devicetree/bindings/pinctrl/renesas,*.
Example:

msiof0: spi@e6e20000 {
- compatible = "renesas,msiof-r8a7791";
+ compatible = "renesas,msiof-r8a7791",
+ "renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 3de39bd..e190b33 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -974,13 +974,14 @@ static const struct sh_msiof_chipdata r8a779x_data = {
};

static const struct of_device_id sh_msiof_match[] = {
- { .compatible = "renesas,sh-msiof", .data = &sh_data },
{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
{ .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
{ .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
{ .compatible = "renesas,msiof-r8a7792", .data = &r8a779x_data },
{ .compatible = "renesas,msiof-r8a7793", .data = &r8a779x_data },
{ .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data },
+ { .compatible = "renesas,rcar-gen2-msiof", .data = &r8a779x_data },
+ { .compatible = "renesas,sh-msiof", .data = &sh_data }, // Deprecated
{},
};
MODULE_DEVICE_TABLE(of, sh_msiof_match);
--
2.7.4


[PATCH 0/4] Add MSIOF support to r8a7743

Fabrizio Castro <fabrizio.castro@...>
 

Dear All,

this series backports all that is required to add MSIOF support
to r8a7743.

Thanks,

Fabrizio Castro (3):
spi: sh-msiof: Add compatible strings for r8a774[35]
spi: sh-msiof: Add r8a774[35] to the compatible list
ARM: dts: r8a7743: Add MSIOF[012] support

Simon Horman (1):
spi: sh-msiof: Add R-Car Gen 2 and 3 fallback bindings

Documentation/devicetree/bindings/spi/sh-msiof.txt | 18 +++++---
arch/arm/boot/dts/r8a7743.dtsi | 48 ++++++++++++++++++++++
drivers/spi/spi-sh-msiof.c | 5 ++-
3 files changed, 65 insertions(+), 6 deletions(-)

--
2.7.4


[RFC/PATCH] dmaengine: ensure dmaengine helpers check valid callback

Fabrizio Castro <fabrizio.castro@...>
 

From: Vinod Koul <vinod.koul@...>

dmaengine has various device callbacks and exposes helper
functions to invoke these. These helpers should check if channel,
device and callback is valid or not before invoking them.

Reported-by: Jon Hunter <jonathanh@...>
Signed-off-by: Vinod Koul <vinod.koul@...>
(cherry picked from commit 757d12e5849be549076901b0d33c60d5f360269c)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Jianming Qiao <jianming.qiao@...>
---
Hello Ben,

we have stumbled upon a problem, and discovered there was this fix
upstream we would like to backport.

Do you think this should go through v4.4 LTS first or are you happy
to take it?

Thanks,
Fab

include/linux/dmaengine.h | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index c47c68e..a16d185 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -767,6 +767,9 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
sg_dma_address(&sg) = buf;
sg_dma_len(&sg) = len;

+ if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
+ return NULL;
+
return chan->device->device_prep_slave_sg(chan, &sg, 1,
dir, flags, NULL);
}
@@ -775,6 +778,9 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
enum dma_transfer_direction dir, unsigned long flags)
{
+ if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
+ return NULL;
+
return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
dir, flags, NULL);
}
@@ -786,6 +792,9 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
enum dma_transfer_direction dir, unsigned long flags,
struct rio_dma_ext *rio_ext)
{
+ if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
+ return NULL;
+
return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
dir, flags, rio_ext);
}
@@ -796,6 +805,9 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
size_t period_len, enum dma_transfer_direction dir,
unsigned long flags)
{
+ if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
+ return NULL;
+
return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
period_len, dir, flags);
}
@@ -804,6 +816,9 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
struct dma_chan *chan, struct dma_interleaved_template *xt,
unsigned long flags)
{
+ if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
+ return NULL;
+
return chan->device->device_prep_interleaved_dma(chan, xt, flags);
}

@@ -811,7 +826,7 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
unsigned long flags)
{
- if (!chan || !chan->device)
+ if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
return NULL;

return chan->device->device_prep_dma_memset(chan, dest, value,
@@ -824,6 +839,9 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
struct scatterlist *src_sg, unsigned int src_nents,
unsigned long flags)
{
+ if (!chan || !chan->device || !chan->device->device_prep_dma_sg)
+ return NULL;
+
return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
src_sg, src_nents, flags);
}
--
2.7.4


Re: [PATCH 0/6] Add SDHI support to r8a7743

Ben Hutchings <ben.hutchings@...>
 

On Thu, 2018-03-08 at 13:32 +0000, Fabrizio Castro wrote:
Hello Ben,

Subject: Re: [cip-dev][PATCH 0/6] Add SDHI support to r8a7743

On Fri, 2018-03-02 at 11:44 +0000, Fabrizio Castro wrote:
Dear All,

this patch series adds SDHI support to the r8a7743 SoC.

The only patch that hasn't been backported in this series is:
"ARM: shmobile: r8a7743: Rename SDHI clocks"

This work has been based on top of this series:
https://lists.cip-project.org/pipermail/cip-dev/2018-February/000863.html
Applied, thanks.  (It's a shame you had to drop UHS support... I worked
on upstreaming it but didn't quite get it into shape before 4.4.)
Thank you for that. The plan is to get back to UHS later on, what are
your thoughts about its backporting?
It seems like a reasonable thing to do.

Ben.

--
Ben Hutchings
Software Developer, Codethink Ltd.


Re: [PATCH 0/6] Add SDHI support to r8a7743

Fabrizio Castro <fabrizio.castro@...>
 

Hello Ben,

Subject: Re: [cip-dev][PATCH 0/6] Add SDHI support to r8a7743

On Fri, 2018-03-02 at 11:44 +0000, Fabrizio Castro wrote:
Dear All,

this patch series adds SDHI support to the r8a7743 SoC.

The only patch that hasn't been backported in this series is:
"ARM: shmobile: r8a7743: Rename SDHI clocks"

This work has been based on top of this series:
https://lists.cip-project.org/pipermail/cip-dev/2018-February/000863.html
Applied, thanks. (It's a shame you had to drop UHS support... I worked
on upstreaming it but didn't quite get it into shape before 4.4.)
Thank you for that. The plan is to get back to UHS later on, what are your thoughts about its backporting?

Thanks,
Fab


Ben.

Thanks,
Fabrizio

Biju Das (5):
mmc: renesas_sdhi: Add r8a7743/5 support
mmc: renesas_sdhi: Add r8a7743/5 support
ARM: dts: r8a7743: Add SDHI controllers
ARM: dts: iwg20m: Enable SDHI0 controller
ARM: dts: iwg20d-q7: Add SDHI1 support

Fabrizio Castro (1):
ARM: shmobile: r8a7743: Rename SDHI clocks

Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 2 +
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 40 ++++++++++++++++++++
arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 17 +++++++++
arch/arm/boot/dts/r8a7743.dtsi | 43 +++++++++++++++++++++-
drivers/mmc/host/sh_mobile_sdhi.c | 2 +
include/dt-bindings/clock/r8a7743-clock.h | 4 +-
6 files changed, 104 insertions(+), 4 deletions(-)
--
Ben Hutchings
Software Developer, Codethink Ltd.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.


Re: [PATCH 0/6] Add SDHI support to r8a7743

Ben Hutchings <ben.hutchings@...>
 

On Fri, 2018-03-02 at 11:44 +0000, Fabrizio Castro wrote:
Dear All,

this patch series adds SDHI support to the r8a7743 SoC.

The only patch that hasn't been backported in this series is:
"ARM: shmobile: r8a7743: Rename SDHI clocks"

This work has been based on top of this series:
https://lists.cip-project.org/pipermail/cip-dev/2018-February/000863.html
Applied, thanks. (It's a shame you had to drop UHS support... I worked
on upstreaming it but didn't quite get it into shape before 4.4.)

Ben.

Thanks,
Fabrizio

Biju Das (5):
  mmc: renesas_sdhi: Add r8a7743/5 support
  mmc: renesas_sdhi: Add r8a7743/5 support
  ARM: dts: r8a7743: Add SDHI controllers
  ARM: dts: iwg20m: Enable SDHI0 controller
  ARM: dts: iwg20d-q7: Add SDHI1 support

Fabrizio Castro (1):
  ARM: shmobile: r8a7743: Rename SDHI clocks

 Documentation/devicetree/bindings/mmc/tmio_mmc.txt |  2 +
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts            | 40 ++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi              | 17 +++++++++
 arch/arm/boot/dts/r8a7743.dtsi                     | 43 +++++++++++++++++++++-
 drivers/mmc/host/sh_mobile_sdhi.c                  |  2 +
 include/dt-bindings/clock/r8a7743-clock.h          |  4 +-
 6 files changed, 104 insertions(+), 4 deletions(-)
--
Ben Hutchings
Software Developer, Codethink Ltd.


Re: [PATCH 12/15] ARM: dts: iwg20d-q7: Rework DT architecture

Ben Hutchings <ben.hutchings@...>
 

On Wed, 2018-03-07 at 17:47 +0000, Ben Hutchings wrote:
On Mon, 2018-03-05 at 11:02 +0000, Fabrizio Castro wrote:
Since the same carrier board may host RZ/G1M and RZ/G1N based
Systems on Module, the DT architecture for iwg20d-q7 needs
better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier
  board definitions, and its content is basically the same
  as the previous version of r8a7743-iwg20d-q7.dts, only it
  has no reference to the SoM .dtsi, and that's why the
  filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together
  the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board
  .dtsi defined by this very patch, along with "model" and
  "compatible" properties.
The final DT architecture to describe the board is now:
r8a7743-iwg20d-q7.dts           # Carrier Board + SoM
├── r8a7743-iwg20m.dtsi         # SoM
│   └── r8a7743.dtsi            # SoC
└── iwg20d-q7-common.dtsi       # Carrier Board
and maximizes the reuse of the definitions for the carrier board
and for the SoM.
I got a conflict at this point.  It looks like this series has to be
applied on top of the SDHI changes, which you posted later!  Please be
explicit about any such ordering dependencies.
My mistake, you posted the SDHI changes earlier but they got reordered
in my mailbox. Still, please let me know if any patch series you send
depends on any other patch series that I haven't yet applied.

Ben.


Ben.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi | 108
++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 100 +---------------------
-------
 2 files changed, 110 insertions(+), 98 deletions(-)
 create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
new file mode 100644
index 0000000..1a0bb24
--- /dev/null
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public
License
+ * version 2.  This program is licensed "as is" without any warranty
of any
+ * kind, whether express or implied.
+ */
+
+/ {
+ aliases {
+ serial0 = &scif0;
+ ethernet0 = &avb;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+ gpios-states = <1>;
+ states = <3300000 1
+   1800000 0>;
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy3>;
+ phy-mode = "gmii";
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rtc@68 {
+ compatible = "bq32000";
+ reg = <0x68>;
+ };
+};
+
+&pfc {
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_gmii";
+ function = "avb";
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2";
+ function = "i2c2";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data_d";
+ function = "scif0";
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index 0bd9754..6aa6b74 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ * Device Tree Source for the iWave-RZ/G1M Qseven board
  *
  * Copyright (C) 2017 Renesas Electronics Corp.
  *
@@ -10,105 +10,9 @@
 
 /dts-v1/;
 #include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
 
 / {
  model = "iWave Systems RainboW-G20D-Qseven board based on
RZ/G1M";
  compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
-
- aliases {
- serial0 = &scif0;
- ethernet0 = &avb;
- };
-
- vcc_sdhi1: regulator-vcc-sdhi1 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI1 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
- gpios-states = <1>;
- states = <3300000 1
-   1800000 0>;
- };
-};
-
-&pfc {
- i2c2_pins: i2c2 {
- groups = "i2c2";
- function = "i2c2";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data_d";
- function = "scif0";
- };
-
- avb_pins: avb {
- groups = "avb_mdio", "avb_gmii";
- function = "avb";
- };
-
- sdhi1_pins: sd1 {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <3300>;
- };
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy3>;
- phy-mode = "gmii";
- renesas,no-ether-link;
- status = "okay";
-
- phy3: ethernet-phy@3 {
- reg = <3>;
- micrel,led-mode = <1>;
- };
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_sdhi1>;
- vqmmc-supply = <&vccq_sdhi1>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- rtc@68 {
- compatible = "bq32000";
- reg = <0x68>;
- };
 };
--
Ben Hutchings
Software Developer, Codethink Ltd.


Re: [PATCH 12/15] ARM: dts: iwg20d-q7: Rework DT architecture

Ben Hutchings <ben.hutchings@...>
 

On Mon, 2018-03-05 at 11:02 +0000, Fabrizio Castro wrote:
Since the same carrier board may host RZ/G1M and RZ/G1N based
Systems on Module, the DT architecture for iwg20d-q7 needs
better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier
  board definitions, and its content is basically the same
  as the previous version of r8a7743-iwg20d-q7.dts, only it
  has no reference to the SoM .dtsi, and that's why the
  filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together
  the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board
  .dtsi defined by this very patch, along with "model" and
  "compatible" properties.
The final DT architecture to describe the board is now:
r8a7743-iwg20d-q7.dts           # Carrier Board + SoM
├── r8a7743-iwg20m.dtsi         # SoM
│   └── r8a7743.dtsi            # SoC
└── iwg20d-q7-common.dtsi       # Carrier Board
and maximizes the reuse of the definitions for the carrier board
and for the SoM.
I got a conflict at this point. It looks like this series has to be
applied on top of the SDHI changes, which you posted later! Please be
explicit about any such ordering dependencies.

Ben.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi | 108
++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 100 +---------------------
-------
 2 files changed, 110 insertions(+), 98 deletions(-)
 create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
new file mode 100644
index 0000000..1a0bb24
--- /dev/null
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public
License
+ * version 2.  This program is licensed "as is" without any warranty
of any
+ * kind, whether express or implied.
+ */
+
+/ {
+ aliases {
+ serial0 = &scif0;
+ ethernet0 = &avb;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+ gpios-states = <1>;
+ states = <3300000 1
+   1800000 0>;
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy3>;
+ phy-mode = "gmii";
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rtc@68 {
+ compatible = "bq32000";
+ reg = <0x68>;
+ };
+};
+
+&pfc {
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_gmii";
+ function = "avb";
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2";
+ function = "i2c2";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data_d";
+ function = "scif0";
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index 0bd9754..6aa6b74 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ * Device Tree Source for the iWave-RZ/G1M Qseven board
  *
  * Copyright (C) 2017 Renesas Electronics Corp.
  *
@@ -10,105 +10,9 @@
 
 /dts-v1/;
 #include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
 
 / {
  model = "iWave Systems RainboW-G20D-Qseven board based on
RZ/G1M";
  compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
-
- aliases {
- serial0 = &scif0;
- ethernet0 = &avb;
- };
-
- vcc_sdhi1: regulator-vcc-sdhi1 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI1 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
- gpios-states = <1>;
- states = <3300000 1
-   1800000 0>;
- };
-};
-
-&pfc {
- i2c2_pins: i2c2 {
- groups = "i2c2";
- function = "i2c2";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data_d";
- function = "scif0";
- };
-
- avb_pins: avb {
- groups = "avb_mdio", "avb_gmii";
- function = "avb";
- };
-
- sdhi1_pins: sd1 {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <3300>;
- };
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy3>;
- phy-mode = "gmii";
- renesas,no-ether-link;
- status = "okay";
-
- phy3: ethernet-phy@3 {
- reg = <3>;
- micrel,led-mode = <1>;
- };
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_sdhi1>;
- vqmmc-supply = <&vccq_sdhi1>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- rtc@68 {
- compatible = "bq32000";
- reg = <0x68>;
- };
 };
--
Ben Hutchings
Software Developer, Codethink Ltd.


Re: [PATCH 0/3] Add RTC support to iwg20d

Ben Hutchings <ben.hutchings@...>
 

On Mon, 2018-02-19 at 18:45 +0000, Fabrizio Castro wrote:
This patch series aims at adding RTC support to the iwg20d
board from iWave.
The commits from this series backport board specific DT
support and defconfig support.
Applied. Sorry for the delay.

Ben

Biju Das (3):
  ARM: dts: iwg20d-q7: Add RTC support
  ARM: shmobile: Enable BQ32000 rtc in shmobile_defconfig
  ARM: multi_v7_defconfig: Enable BQ32000 RTC driver

 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 18 ++++++++++++++++++
 arch/arm/configs/multi_v7_defconfig     |  1 +
 arch/arm/configs/shmobile_defconfig     |  1 +
 3 files changed, 20 insertions(+)
--
Ben Hutchings
Software Developer, Codethink Ltd.


[PATCH 7/7] ARM: dts: r8a7743: Enable DMA for HSUSB

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

This patch adds DMA properties to the HSUSB node.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit e0a10e7b070624965f20205c59fb2a0c0b465782)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index db00959..40137cf 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1215,6 +1215,9 @@
reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7743_CLK_HSUSB>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
power-domains = <&cpg_clocks>;
renesas,buswait = <4>;
phys = <&usb0 1>;
--
2.7.4


[PATCH 6/7] ARM: dts: r8a7743: Add USB-DMAC device nodes

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 310861003a0d59cb410538bcdf73a218157a111d)
(modified clocks and power-domains properties, removed resets property)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 1237746..db00959 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -309,6 +309,30 @@
dma-channels = <15>;
};

+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&mstp3_clks R8A7743_CLK_USBDMAC0>;
+ power-domains = <&cpg_clocks>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&mstp3_clks R8A7743_CLK_USBDMAC1>;
+ power-domains = <&cpg_clocks>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
/* The memory map in the User's Manual maps the cores to bus
* numbers
*/
--
2.7.4


[PATCH 5/7] ARM: dts: iwg20d-q7: Enable HS-USB

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Enable HS-USB device for the iWave G20D-Q7 carrier board based on
RZ/G1M.
Also disable the host mode support on usb otg port by default to avoid
pin conflicts.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 405b580227ff1ae8fde82a666a2a5c0391a7e64a)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index fbb5215..8f203c5 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -59,6 +59,12 @@
};
};

+&hsusb {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+};
+
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
@@ -111,7 +117,6 @@
};

&pci0 {
- status = "okay";
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
};
--
2.7.4


[PATCH 4/7] ARM: dts: r8a7743: Add HS-USB device node

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Define the R8A7743 generic part of the HS-USB device node. It is up to the
board file to enable the device.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 4b4a3b1c33b7a389d90624683d8f1a8d1dc2affa)
(modified clocks, power-domains properties and removed resets property)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 1b17a20..1237746 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1185,6 +1185,19 @@
};
};

+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7743",
+ "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7743_CLK_HSUSB>;
+ power-domains = <&cpg_clocks>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
usbphy: usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7743",
"renesas,rcar-gen2-usb-phy";
--
2.7.4


[PATCH 3/7] usb: renesas_usbhs: Add compatible string for r8a7743/5

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

This patch adds support for r8a7743/5 SoCs. The Renesas RZ/G1[ME]
(R8A7743/5) usbhs is identical to the R-Car Gen2 family.

No driver change is needed due to the fallback compatible value
"renesas,rcar-gen2-usbhs".
Adding the SoC-specific compatible values here has two purposes:
1. Document which SoCs have this hardware module,
2. Allow checkpatch to validate compatible values.

Acked-by: Rob Herring <robh@...>
Acked-by: Simon Horman <horms+renesas@...>
Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Felipe Balbi <felipe.balbi@...>
(cherry picked from commit e0d63c4083852e07655dfcda1320504c304218be)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
index 45d9ae1..65af38c 100644
--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
@@ -3,6 +3,8 @@ Renesas Electronics USBHS driver
Required properties:
- compatible: Must contain one or more of the following:

+ - "renesas,usbhs-r8a7743" for r8a7743 (RZ/G1M) compatible device
+ - "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device
- "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device
- "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device
- "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device
--
2.7.4


[PATCH 2/7] usb: renesas_usbhs: add fallback compatibility strings

Fabrizio Castro <fabrizio.castro@...>
 

From: Simon Horman <horms+renesas@...>

Add fallback compatibility strings for R-Car Gen2 and Gen3.
This is in keeping with the fallback scheme being adopted wherever
appropriate for drivers for Renesas SoCs.

Signed-off-by: Simon Horman <horms+renesas@...>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@...>
Signed-off-by: Felipe Balbi <balbi@...>
(cherry picked from commit 2f1a993a0da652c50e08159f16590b7f9820d192)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 12 ++++++++++--
drivers/usb/renesas_usbhs/common.c | 9 +++++++++
2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
index a14c0bb..45d9ae1 100644
--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
@@ -1,11 +1,19 @@
Renesas Electronics USBHS driver

Required properties:
- - compatible: Must contain one of the following:
+ - compatible: Must contain one or more of the following:
+
- "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device
- "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device
- "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device
- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
+ - "renesas,rcar-gen2-usbhs" for R-Car Gen2 compatible device
+ - "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first followed
+ by the generic version.
+
- reg: Base address and length of the register for the USBHS
- interrupts: Interrupt specifier for the USBHS
- clocks: A list of phandle + clock specifier pairs
@@ -22,7 +30,7 @@ Optional properties:

Example:
usbhs: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7790";
+ compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
reg = <0 0xe6590000 0 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
index 005da08..2fa4479 100644
--- a/drivers/usb/renesas_usbhs/common.c
+++ b/drivers/usb/renesas_usbhs/common.c
@@ -481,6 +481,15 @@ static const struct of_device_id usbhs_of_match[] = {
.compatible = "renesas,usbhs-r8a7795",
.data = (void *)USBHS_TYPE_RCAR_GEN2,
},
+ {
+ .compatible = "renesas,rcar-gen2-usbhs",
+ .data = (void *)USBHS_TYPE_RCAR_GEN2,
+ },
+ {
+ /* Gen3 is compatible with Gen2 */
+ .compatible = "renesas,rcar-gen3-usbhs",
+ .data = (void *)USBHS_TYPE_RCAR_GEN2,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, usbhs_of_match);
--
2.7.4


[PATCH 1/7] usb: renesas_usbhs: add SoC names to compatibility string documentation

Fabrizio Castro <fabrizio.castro@...>
 

From: Simon Horman <horms+renesas@...>

This extends the documentation of compatibility strings a little to
include the SoC names.

Signed-off-by: Simon Horman <horms+renesas@...>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@...>
Signed-off-by: Felipe Balbi <balbi@...>
(cherry picked from commit 89d75bf18d0e3e9a02961f537c87d7991df3bd32)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
index 7d48f63..a14c0bb 100644
--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
@@ -2,10 +2,10 @@ Renesas Electronics USBHS driver

Required properties:
- compatible: Must contain one of the following:
- - "renesas,usbhs-r8a7790"
- - "renesas,usbhs-r8a7791"
- - "renesas,usbhs-r8a7794"
- - "renesas,usbhs-r8a7795"
+ - "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device
+ - "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device
+ - "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device
+ - "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
- reg: Base address and length of the register for the USBHS
- interrupts: Interrupt specifier for the USBHS
- clocks: A list of phandle + clock specifier pairs
--
2.7.4


[PATCH 0/7] Add HSUSB to r8a7743

Fabrizio Castro <fabrizio.castro@...>
 

Dear All,

this series backports all the patches necessary to add HSUSB support
to the r8a7743.

Thanks,
Fabrizio

Biju Das (5):
usb: renesas_usbhs: Add compatible string for r8a7743/5
ARM: dts: r8a7743: Add HS-USB device node
ARM: dts: iwg20d-q7: Enable HS-USB
ARM: dts: r8a7743: Add USB-DMAC device nodes
ARM: dts: r8a7743: Enable DMA for HSUSB

Simon Horman (2):
usb: renesas_usbhs: add SoC names to compatibility string
documentation
usb: renesas_usbhs: add fallback compatibility strings

.../devicetree/bindings/usb/renesas_usbhs.txt | 22 ++++++++----
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 7 +++-
arch/arm/boot/dts/r8a7743.dtsi | 40 ++++++++++++++++++++++
drivers/usb/renesas_usbhs/common.c | 9 +++++
4 files changed, 71 insertions(+), 7 deletions(-)

--
2.7.4


[PATCH 10/10] ARM: dts: iwg20d-q7: Enable USB PHY

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 51be0086e6d2ebb3f0ddbeedab8d7c4232c1c5f6)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index ecd7bd8..fbb5215 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -147,3 +147,7 @@
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+&usbphy {
+ status = "okay";
+};
--
2.7.4


[PATCH 09/10] ARM: dts: iwg20d-q7: Enable internal PCI

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers
attached to them.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 35a8eeeac89c56435277fa76f8d557bf00530320)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index 5dec247..ecd7bd8 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -98,6 +98,28 @@
function = "sdhi1";
power-source = <3300>;
};
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ groups = "usb1";
+ function = "usb1";
+ };
+};
+
+&pci0 {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+};
+
+&pci1 {
+ status = "okay";
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
};

&scif0 {
--
2.7.4


[PATCH 08/10] ARM: dts: r8a7743: Link PCI USB devices to USB PHY

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Describe the PCI USB devices that are behind the PCI bridges, adding
necessary links to the USB PHY device.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 96963454655c10663f1bc2eea57ac734cab171a7)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index be8881a..1b17a20 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1229,6 +1229,18 @@
0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
};

pci1: pci@ee0d0000 {
@@ -1254,6 +1266,18 @@
0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
>;
+
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
};
};

--
2.7.4

8701 - 8720 of 9641