Date   

[PATCH 07/10] ARM: dts: r8a7743: Add USB PHY DT support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Define the r8a7743 generic part of the USB PHY device node.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 9412c391af67fc8aa4e2d8975ba6143cd5289296)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index d90310c..be8881a 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1185,6 +1185,27 @@
};
};

+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7743",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mstp7_clks R8A7743_CLK_HSUSB>;
+ clock-names = "usbhs";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7743",
"renesas,pci-rcar-gen2";
--
2.7.4


[PATCH 06/10] phy: rcar-gen2: add fallback binding

Fabrizio Castro <fabrizio.castro@...>
 

From: Simon Horman <horms+renesas@...>

In the case of Renesas R-Car hardware we know that there are generations of
SoCs, e.g. Gen 2 and Gen 3. But beyond that its not clear what the
relationship between IP blocks might be. For example, I believe that
r8a7790 is older than r8a7791 but that doesn't imply that the latter is a
descendant of the former or vice versa.

We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.

For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme being adopted for
drivers for Renesas SoCs.

Signed-off-by: Simon Horman <horms+renesas@...>
Acked-by: Geert Uytterhoeven <geert+renesas@...>
Acked-by: Rob Herring <robh@...>
Signed-off-by: Kishon Vijay Abraham I <kishon@...>
---
Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt | 8 +++++++-
drivers/phy/phy-rcar-gen2.c | 1 +
2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
index 883b915..75abc6d 100644
--- a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
@@ -9,6 +9,12 @@ Required properties:
"renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
"renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
"renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
+ "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 compatible device.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
- reg: offset and length of the register block.
- #address-cells: number of address cells for the USB channel subnodes, must
be <1>.
@@ -36,7 +42,7 @@ the USB channel; see the selector meanings below:
Example (Lager board):

usb-phy@e6590100 {
- compatible = "renesas,usb-phy-r8a7790";
+ compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c
index c7a0599..97d4dd6 100644
--- a/drivers/phy/phy-rcar-gen2.c
+++ b/drivers/phy/phy-rcar-gen2.c
@@ -195,6 +195,7 @@ static const struct of_device_id rcar_gen2_phy_match_table[] = {
{ .compatible = "renesas,usb-phy-r8a7790" },
{ .compatible = "renesas,usb-phy-r8a7791" },
{ .compatible = "renesas,usb-phy-r8a7794" },
+ { .compatible = "renesas,rcar-gen2-usb-phy" },
{ }
};
MODULE_DEVICE_TABLE(of, rcar_gen2_phy_match_table);
--
2.7.4


[PATCH 05/10] phy: rcar-gen2: Add r8a7743/5 support

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Add USB PHY support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5)
USB PHY is identical to the R-Car Gen2 family.

Signed-off-by: Biju Das <biju.das@...>
Acked-by: Simon Horman <horms+renesas@...>
Acked-by: Rob Herring <robh@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Kishon Vijay Abraham I <kishon@...>
(cherry picked from commit f7da4e6d29539bad2c29dd8ccb4ac628fe19f82b)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
index d564ba4..883b915 100644
--- a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
@@ -4,7 +4,9 @@ This file provides information on what the device node for the R-Car generation
2 USB PHY contains.

Required properties:
-- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
+- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
+ "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
+ "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
"renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
"renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
- reg: offset and length of the register block.
--
2.7.4


[PATCH 04/10] ARM: dts: r8a7743: Add internal PCI bridge nodes

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Add device nodes for the r8a7743 internal PCI bridge devices.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 46d9cf5202fd8cd266748779c1a941aaeff0dcad)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 50 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 8515abf..d90310c 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1184,6 +1184,56 @@
"scifa5";
};
};
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7743",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7743_CLK_USB_EHCI>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0
+ 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <
+ 0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ >;
+ };
+
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7743",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7743_CLK_USB_EHCI>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0
+ 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <
+ 0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ >;
+ };
};

/* External root clock */
--
2.7.4


[PATCH 03/10] PCI: rcar: Add device tree support for r8a7743/5

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Add internal PCI bridge support for r8a7743/5 SoC. The Renesas RZ/G1[ME]
(R8A7743/5) internal PCI bridge is identical to the R-Car Gen2 family.

This doesn't change the driver, so it does nothing by itself. But it does
mean that checkpatch won't complain about a future patch that adds
"renesas,pci-r8a7743" to a DT, which helps ensure that shipped DTs use
documented compatibility strings.

Signed-off-by: Biju Das <biju.das@...>
[bhelgaas: add explanatory note]
Signed-off-by: Bjorn Helgaas <bhelgaas@...>
Acked-by: Simon Horman <horms+renesas@...>
(cherry picked from commit c31c83c970165b9f2cb4c0ad6ae89d0a8242cf7b)

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index 3690f68..421ab0a 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -6,7 +6,9 @@ AHB. There is one bridge instance per USB port connected to the internal
OHCI and EHCI controllers.

Required properties:
-- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
+- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC;
+ "renesas,pci-r8a7745" for the R8A7745 SoC;
+ "renesas,pci-r8a7790" for the R8A7790 SoC;
"renesas,pci-r8a7791" for the R8A7791 SoC;
"renesas,pci-r8a7794" for the R8A7794 SoC;
"renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
--
2.7.4


[PATCH 02/10] PCI: rcar-gen2: Use gen2 fallback compatibility last

Fabrizio Castro <fabrizio.castro@...>
 

From: Simon Horman <horms+renesas@...>

Improve readability by listing fallback compatibility strings after the
more-specific compatibility strings they provide a fallback for.

This does not affect run-time behaviour as it is the order in the DTB that
determines which compatibility string is used.

Signed-off-by: Simon Horman <horms+renesas@...>
Signed-off-by: Bjorn Helgaas <bhelgaas@...>
(cherry picked from commit 7b99d94277ba49f401b7a5c1ad8a9084cc6c34a6)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pci/host/pci-rcar-gen2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c
index 5683e70..acefff7 100644
--- a/drivers/pci/host/pci-rcar-gen2.c
+++ b/drivers/pci/host/pci-rcar-gen2.c
@@ -360,10 +360,10 @@ static int rcar_pci_probe(struct platform_device *pdev)
}

static struct of_device_id rcar_pci_of_match[] = {
- { .compatible = "renesas,pci-rcar-gen2", },
{ .compatible = "renesas,pci-r8a7790", },
{ .compatible = "renesas,pci-r8a7791", },
{ .compatible = "renesas,pci-r8a7794", },
+ { .compatible = "renesas,pci-rcar-gen2", },
{ },
};

--
2.7.4


[PATCH 01/10] PCI: rcar: Add gen2 fallback compatibility string for pci-rcar-gen2

Fabrizio Castro <fabrizio.castro@...>
 

From: Simon Horman <horms+renesas@...>

Add fallback compatibility string for R-Car Gen 2 family. This is in
keeping with the fallback scheme being adopted wherever appropriate for
drivers for Renesas SoCs.

Signed-off-by: Simon Horman <horms+renesas@...>
Signed-off-by: Bjorn Helgaas <bhelgaas@...>
Acked-by: Rob Herring <robh@...>
(cherry picked from commit 3517652fda51bfeea3768ba05819744c8ac57d9e)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 11 +++++++++--
drivers/pci/host/pci-rcar-gen2.c | 1 +
2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index 7fab84b..3690f68 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -8,7 +8,14 @@ OHCI and EHCI controllers.
Required properties:
- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
"renesas,pci-r8a7791" for the R8A7791 SoC;
- "renesas,pci-r8a7794" for the R8A7794 SoC.
+ "renesas,pci-r8a7794" for the R8A7794 SoC;
+ "renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
+
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
- reg: A list of physical regions to access the device: the first is
the operational registers for the OHCI/EHCI controllers and the
second is for the bridge configuration and control registers.
@@ -27,7 +34,7 @@ Required properties:
Example SoC configuration:

pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7790";
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
reg = <0x0 0xee090000 0x0 0xc00>,
<0x0 0xee080000 0x0 0x1100>;
diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c
index c4f64bf..5683e70 100644
--- a/drivers/pci/host/pci-rcar-gen2.c
+++ b/drivers/pci/host/pci-rcar-gen2.c
@@ -360,6 +360,7 @@ static int rcar_pci_probe(struct platform_device *pdev)
}

static struct of_device_id rcar_pci_of_match[] = {
+ { .compatible = "renesas,pci-rcar-gen2", },
{ .compatible = "renesas,pci-r8a7790", },
{ .compatible = "renesas,pci-r8a7791", },
{ .compatible = "renesas,pci-r8a7794", },
--
2.7.4


[PATCH 00/10] Add PCI and USB PHY support to iwg20d

Fabrizio Castro <fabrizio.castro@...>
 

This series backports patches necessary to add PCI and USB PHY support
to iWave's iwg20d board.

Thanks,
Fabrizio

Biju Das (7):
PCI: rcar: Add device tree support for r8a7743/5
ARM: dts: r8a7743: Add internal PCI bridge nodes
phy: rcar-gen2: Add r8a7743/5 support
ARM: dts: r8a7743: Add USB PHY DT support
ARM: dts: r8a7743: Link PCI USB devices to USB PHY
ARM: dts: iwg20d-q7: Enable internal PCI
ARM: dts: iwg20d-q7: Enable USB PHY

Simon Horman (3):
PCI: rcar: Add gen2 fallback compatibility string for pci-rcar-gen2
PCI: rcar-gen2: Use gen2 fallback compatibility last
phy: rcar-gen2: add fallback binding

.../devicetree/bindings/pci/pci-rcar-gen2.txt | 15 +++-
.../devicetree/bindings/phy/rcar-gen2-phy.txt | 12 ++-
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 26 ++++++
arch/arm/boot/dts/r8a7743.dtsi | 95 ++++++++++++++++++++++
drivers/pci/host/pci-rcar-gen2.c | 1 +
drivers/phy/phy-rcar-gen2.c | 1 +
6 files changed, 145 insertions(+), 5 deletions(-)

--
2.7.4


Re: [PATCH 0/6] Add SDHI support to r8a7743

Chris Paterson
 

Hello Fabrizio,

From: Fabrizio Castro [mailto:fabrizio.castro@...]
Sent: 02 March 2018 11:45

Dear All,

this patch series adds SDHI support to the r8a7743 SoC.
Thank you for the patches.


The only patch that hasn't been backported in this series is:
"ARM: shmobile: r8a7743: Rename SDHI clocks"

This work has been based on top of this series:
https://lists.cip-project.org/pipermail/cip-dev/2018-February/000863.html

Thanks,
Fabrizio

Biju Das (5):
mmc: renesas_sdhi: Add r8a7743/5 support
mmc: renesas_sdhi: Add r8a7743/5 support
ARM: dts: r8a7743: Add SDHI controllers
ARM: dts: iwg20m: Enable SDHI0 controller
ARM: dts: iwg20d-q7: Add SDHI1 support

Fabrizio Castro (1):
ARM: shmobile: r8a7743: Rename SDHI clocks
Series: Reviewed-by: Chris Paterson <chris.paterson2@...>

Kind regards, Chris


Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 2 +
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 40
++++++++++++++++++++
arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 17 +++++++++
arch/arm/boot/dts/r8a7743.dtsi | 43 +++++++++++++++++++++-
drivers/mmc/host/sh_mobile_sdhi.c | 2 +
include/dt-bindings/clock/r8a7743-clock.h | 4 +-
6 files changed, 104 insertions(+), 4 deletions(-)

--
2.7.4


[PATCH 15/15] ARM: dts: iwg20d-q7: Add chosen node

Fabrizio Castro <fabrizio.castro@...>
 

From: Biju Das <biju.das@...>

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit f9c1e87e77ca1ef1c4de2d419b0dcb42e4a47043)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index 7d93a7c..5dec247 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -15,6 +15,11 @@
ethernet0 = &avb;
};

+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";

--
2.7.4


[PATCH 14/15] ARM: dts: iwg20d-q7: Add support for ttySC3

Fabrizio Castro <fabrizio.castro@...>
 

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 77014a7c654c76e1c0cf82563cc48e07c546461c)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index 1a0bb24..7d93a7c 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -11,6 +11,7 @@
/ {
aliases {
serial0 = &scif0;
+ serial3 = &scifb1;
ethernet0 = &avb;
};

@@ -82,6 +83,11 @@
function = "scif0";
};

+ scifb1_pins: scifb1 {
+ groups = "scifb1_data_d", "scifb1_ctrl";
+ function = "scifb1";
+ };
+
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
@@ -96,6 +102,14 @@
status = "okay";
};

+&scifb1 {
+ pinctrl-0 = <&scifb1_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";
--
2.7.4


[PATCH 13/15] ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DB

Fabrizio Castro <fabrizio.castro@...>
 

This patch adds a .dtsi that describes the camera daughter board
and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's
RZ/G1M/G1N Qseven carrier board, and the camera daughter board.
The camera daughter board .dtsi adds support for ttySC[14].

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 2ee18841ff649e973d62afc6096b892396a676ef)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi | 43 +++++++++++++++++++++++++
arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts | 19 +++++++++++
3 files changed, 63 insertions(+)
create mode 100644 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f8fd692..22fc8ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -545,6 +545,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-iwg20d-q7.dtb \
+ r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
new file mode 100644
index 0000000..31fab5f
--- /dev/null
+++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
@@ -0,0 +1,43 @@
+/*
+ * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/ {
+ aliases {
+ serial1 = &scif1;
+ serial4 = &hscif1;
+ };
+};
+
+&hscif1 {
+ pinctrl-0 = <&hscif1_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&pfc {
+ hscif1_pins: hscif1 {
+ groups = "hscif1_data_c", "hscif1_ctrl_c";
+ function = "hscif1";
+ };
+
+ scif1_pins: scif1 {
+ groups = "scif1_data_d";
+ function = "scif1";
+ };
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
new file mode 100644
index 0000000..d90eb84
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
@@ -0,0 +1,19 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
+#include "iwg20d-q7-dbcm-ca.dtsi"
+
+/ {
+ model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
+ compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
+};
--
2.7.4


[PATCH 12/15] ARM: dts: iwg20d-q7: Rework DT architecture

Fabrizio Castro <fabrizio.castro@...>
 

Since the same carrier board may host RZ/G1M and RZ/G1N based
Systems on Module, the DT architecture for iwg20d-q7 needs
better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier
board definitions, and its content is basically the same
as the previous version of r8a7743-iwg20d-q7.dts, only it
has no reference to the SoM .dtsi, and that's why the
filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together
the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board
.dtsi defined by this very patch, along with "model" and
"compatible" properties.
The final DT architecture to describe the board is now:
r8a7743-iwg20d-q7.dts # Carrier Board + SoM
├── r8a7743-iwg20m.dtsi # SoM
│   └── r8a7743.dtsi # SoC
└── iwg20d-q7-common.dtsi # Carrier Board
and maximizes the reuse of the definitions for the carrier board
and for the SoM.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 108 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 100 +----------------------------
2 files changed, 110 insertions(+), 98 deletions(-)
create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
new file mode 100644
index 0000000..1a0bb24
--- /dev/null
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/ {
+ aliases {
+ serial0 = &scif0;
+ ethernet0 = &avb;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy3>;
+ phy-mode = "gmii";
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rtc@68 {
+ compatible = "bq32000";
+ reg = <0x68>;
+ };
+};
+
+&pfc {
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_gmii";
+ function = "avb";
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2";
+ function = "i2c2";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data_d";
+ function = "scif0";
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index 0bd9754..6aa6b74 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -1,5 +1,5 @@
/*
- * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ * Device Tree Source for the iWave-RZ/G1M Qseven board
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
@@ -10,105 +10,9 @@

/dts-v1/;
#include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"

/ {
model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
-
- aliases {
- serial0 = &scif0;
- ethernet0 = &avb;
- };
-
- vcc_sdhi1: regulator-vcc-sdhi1 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI1 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
- gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
- };
-};
-
-&pfc {
- i2c2_pins: i2c2 {
- groups = "i2c2";
- function = "i2c2";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data_d";
- function = "scif0";
- };
-
- avb_pins: avb {
- groups = "avb_mdio", "avb_gmii";
- function = "avb";
- };
-
- sdhi1_pins: sd1 {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <3300>;
- };
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy3>;
- phy-mode = "gmii";
- renesas,no-ether-link;
- status = "okay";
-
- phy3: ethernet-phy@3 {
- reg = <3>;
- micrel,led-mode = <1>;
- };
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_sdhi1>;
- vqmmc-supply = <&vccq_sdhi1>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- rtc@68 {
- compatible = "bq32000";
- reg = <0x68>;
- };
};
--
2.7.4


[PATCH 11/15] serial: sh-sci: Add DT support for dedicated RTS/CTS

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Add support for indicating the availability of dedicated lines for
RTS/CTS hardware flow control, using the standard "uart-has-rtscts" DT
property.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Greg Kroah-Hartman <gregkh@...>
(cherry picked from commit 861a70abb483645d4474a6bc006471c2db59a78d)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/tty/serial/sh-sci.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 4e53fa4..b09db16 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2728,6 +2728,9 @@ sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
p->regtype = info->regtype;
p->scscr = SCSCR_RE | SCSCR_TE;

+ if (of_find_property(np, "uart-has-rtscts", NULL))
+ p->capabilities |= SCIx_HAVE_RTSCTS;
+
return p;
}

--
2.7.4


[PATCH 10/15] serial: sh-sci: Fix support for hardware-assisted RTS/CTS

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

The existing support for hardware-assisted RTS/CTS is rudimentary and
doesn't work.

Add support for hardware-assisted RTS/CTS hardware flow control for the
(H)SCIF, SCIFA, and SCIFB variants.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Greg Kroah-Hartman <gregkh@...>
(cherry picked from commit 33f50ffc253854cf6cd556786ae893c7454a1a67)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/tty/serial/sh-sci.c | 90 +++++++++++++++++++++++++++++++++++++++++----
1 file changed, 83 insertions(+), 7 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index e351c6f..4e53fa4 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -117,6 +117,8 @@ struct sci_port {
struct timer_list rx_timer;
unsigned int rx_timeout;
#endif
+
+ bool autorts;
};

#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
@@ -1732,6 +1734,46 @@ static unsigned int sci_tx_empty(struct uart_port *port)
return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
}

+static void sci_set_rts(struct uart_port *port, bool state)
+{
+ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+ u16 data = serial_port_in(port, SCPDR);
+
+ /* Active low */
+ if (state)
+ data &= ~SCPDR_RTSD;
+ else
+ data |= SCPDR_RTSD;
+ serial_port_out(port, SCPDR, data);
+
+ /* RTS# is output */
+ serial_port_out(port, SCPCR,
+ serial_port_in(port, SCPCR) | SCPCR_RTSC);
+ } else if (sci_getreg(port, SCSPTR)->size) {
+ u16 ctrl = serial_port_in(port, SCSPTR);
+
+ /* Active low */
+ if (state)
+ ctrl &= ~SCSPTR_RTSDT;
+ else
+ ctrl |= SCSPTR_RTSDT;
+ serial_port_out(port, SCSPTR, ctrl);
+ }
+}
+
+static bool sci_get_cts(struct uart_port *port)
+{
+ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+ /* Active low */
+ return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
+ } else if (sci_getreg(port, SCSPTR)->size) {
+ /* Active low */
+ return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
+ }
+
+ return true;
+}
+
/*
* Modem control is a bit of a mixed bag for SCI(F) ports. Generally
* CTS/RTS is supported in hardware by at least one port and controlled
@@ -1762,6 +1804,31 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
}

mctrl_gpio_set(s->gpios, mctrl);
+
+ if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
+ return;
+
+ if (!(mctrl & TIOCM_RTS)) {
+ /* Disable Auto RTS */
+ serial_port_out(port, SCFCR,
+ serial_port_in(port, SCFCR) & ~SCFCR_MCE);
+
+ /* Clear RTS */
+ sci_set_rts(port, 0);
+ } else if (s->autorts) {
+ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+ /* Enable RTS# pin function */
+ serial_port_out(port, SCPCR,
+ serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
+ }
+
+ /* Enable Auto RTS */
+ serial_port_out(port, SCFCR,
+ serial_port_in(port, SCFCR) | SCFCR_MCE);
+ } else {
+ /* Set RTS */
+ sci_set_rts(port, 1);
+ }
}

static unsigned int sci_get_mctrl(struct uart_port *port)
@@ -1774,10 +1841,14 @@ static unsigned int sci_get_mctrl(struct uart_port *port)

/*
* CTS/RTS is handled in hardware when supported, while nothing
- * else is wired up. Keep it simple and simply assert CTS/DSR/CAR.
+ * else is wired up.
*/
- if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)))
+ if (s->autorts) {
+ if (sci_get_cts(port))
+ mctrl |= TIOCM_CTS;
+ } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
mctrl |= TIOCM_CTS;
+ }
if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
mctrl |= TIOCM_DSR;
if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
@@ -1850,6 +1921,7 @@ static void sci_shutdown(struct uart_port *port)

dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);

+ s->autorts = false;
mctrl_gpio_disable_ms(to_sci_port(port)->gpios);

spin_lock_irqsave(&port->lock, flags);
@@ -2035,15 +2107,18 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,

sci_init_pins(port, termios->c_cflag);

+ port->status &= ~UPSTAT_AUTOCTS;
+ s->autorts = false;
reg = sci_getreg(port, SCFCR);
if (reg->size) {
unsigned short ctrl = serial_port_in(port, SCFCR);

- if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
- if (termios->c_cflag & CRTSCTS)
- ctrl |= SCFCR_MCE;
- else
- ctrl &= ~SCFCR_MCE;
+ if ((port->flags & UPF_HARD_FLOW) &&
+ (termios->c_cflag & CRTSCTS)) {
+ /* There is no CTS interrupt to restart the hardware */
+ port->status |= UPSTAT_AUTOCTS;
+ /* MCE is enabled when RTS is raised */
+ s->autorts = true;
}

/*
@@ -2687,6 +2762,7 @@ static int sci_probe_single(struct platform_device *dev,
dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
return -EINVAL;
}
+ sciport->port.flags |= UPF_HARD_FLOW;
}

ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
--
2.7.4


[PATCH 09/15] serial: sh-sci: Add pin initialization for SCIFA/SCIFB

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Before, the driver relied on initialization by the boot loader, or by
implicit reset state.

Note that unlike on (H)SCIF, the RTS/CTS bits exist only if dedicated
RTS/CTS pins are available, which depends on the SoC and UART instance.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Greg Kroah-Hartman <gregkh@...>
(cherry picked from commit e9d7a45a039913497a57887d85f5decfda4679f0)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/tty/serial/sh-sci.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index e725023..e351c6f 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -633,7 +633,21 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
return;
}

- if (sci_getreg(port, SCSPTR)->size) {
+ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+ u16 ctrl = serial_port_in(port, SCPCR);
+
+ /* Enable RXD and TXD pin functions */
+ ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
+ if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
+ /* RTS# is output, driven 1 */
+ ctrl |= SCPCR_RTSC;
+ serial_port_out(port, SCPDR,
+ serial_port_in(port, SCPDR) | SCPDR_RTSD);
+ /* Enable CTS# pin function */
+ ctrl &= ~SCPCR_CTSC;
+ }
+ serial_port_out(port, SCPCR, ctrl);
+ } else if (sci_getreg(port, SCSPTR)->size) {
u16 status = serial_port_in(port, SCSPTR);

/* RTS# is output, driven 1 */
--
2.7.4


[PATCH 08/15] serial: sh-sci: Correct pin initialization on (H)SCIF

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Correct pin initialization on (H)SCIF:
- RTS must be deasserted (it's active low),
- SCK must be an input, as it may be used as the optional external
clock input.

Initial pin configuration must always be done:
- Regardless of the presence of dedicated RTS and CTS pins: if the
register exists, the RTS/CTS bits exist, too,
- Regardless of hardware flow control being enabled or not: RTS must
be deasserted.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Greg Kroah-Hartman <gregkh@...>
(cherry picked from commit d2b9775d795ec05fb42504c0f47dd06ba5fd709e)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/tty/serial/sh-sci.c | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index f96f44c..e725023 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -633,21 +633,14 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
return;
}

- /*
- * For the generic path SCSPTR is necessary. Bail out if that's
- * unavailable, too.
- */
- if (!sci_getreg(port, SCSPTR)->size)
- return;
-
- if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
- ((!(cflag & CRTSCTS)))) {
- unsigned short status;
-
- status = serial_port_in(port, SCSPTR);
- status &= ~SCSPTR_CTSIO;
- status |= SCSPTR_RTSIO;
- serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
+ if (sci_getreg(port, SCSPTR)->size) {
+ u16 status = serial_port_in(port, SCSPTR);
+
+ /* RTS# is output, driven 1 */
+ status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
+ /* CTS# and SCK are inputs */
+ status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
+ serial_port_out(port, SCSPTR, status);
}
}

--
2.7.4


[PATCH 07/15] serial: sh-sci: Add more Serial Port Control/Data Register documentation

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Improve documentation for the SCIFA/SCIFB Serial Port Control and Data
Registers:
- State clearly that the RTS and CTS lines are active-low,
- Document the bits related to the serial port's SCK, RXD, and TXD
pins.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Peter Hurley <peter@...>
Signed-off-by: Greg Kroah-Hartman <gregkh@...>
(cherry picked from commit 4780c09f7a0926674c96c0a40dfeb7469f759c8e)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/tty/serial/sh-sci.h | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index fa560c0..1b699ea 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -104,12 +104,18 @@ enum {
#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */

/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
-#define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */
-#define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */
+#define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */
+#define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */
+#define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */
+#define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */
+#define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */

/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
-#define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */
-#define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */
+#define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */
+#define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */
+#define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */
+#define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */
+#define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */


#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
--
2.7.4


[PATCH 06/15] serial: sh-sci: Add more Serial Port Register documentation

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Improve documentation for the (H)SCIF Serial Port Register:
- Make it clear the RTS and CTS lines are active-low,
- Document the bits related to the serial port's clock pin.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Peter Hurley <peter@...>
Signed-off-by: Greg Kroah-Hartman <gregkh@...>
(cherry picked from commit ef5e90e8ccb7b715c0a1509339f730b2bf9698a2)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/tty/serial/sh-sci.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index bf69bbd..fa560c0 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -91,10 +91,12 @@ enum {
#define SCLSR_ORER BIT(0) /* Overrun Error */

/* SCSPTR (Serial Port Register), optional */
-#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS Pin Input/Output */
-#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS Pin Data */
-#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS Pin Input/Output */
-#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS Pin Data */
+#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */
+#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */
+#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */
+#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */
+#define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */
+#define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */
#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */

--
2.7.4


[PATCH 05/15] serial: sh-sci: Do not open-code sci_getreg()

Fabrizio Castro <fabrizio.castro@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Replace open-coded variants of sci_getreg() by function calls, and drop
intermediate variables where appropriate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Peter Hurley <peter@...>
Signed-off-by: Greg Kroah-Hartman <gregkh@...>
(cherry picked from commit abbf121fb6dae6657388a32feac346e5e1debdbd)
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/tty/serial/sh-sci.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index cf91172..f96f44c 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -624,7 +624,6 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
static void sci_init_pins(struct uart_port *port, unsigned int cflag)
{
struct sci_port *s = to_sci_port(port);
- const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;

/*
* Use port-specific handler if provided.
@@ -638,7 +637,7 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
* For the generic path SCSPTR is necessary. Bail out if that's
* unavailable, too.
*/
- if (!reg->size)
+ if (!sci_getreg(port, SCSPTR)->size)
return;

if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
@@ -1787,12 +1786,10 @@ static void sci_enable_ms(struct uart_port *port)

static void sci_break_ctl(struct uart_port *port, int break_state)
{
- struct sci_port *s = to_sci_port(port);
- const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
unsigned short scscr, scsptr;

/* check wheter the port has SCSPTR */
- if (!reg->size) {
+ if (!sci_getreg(port, SCSPTR)->size) {
/*
* Not supported by hardware. Most parts couple break and rx
* interrupts together, with break detection always enabled.
--
2.7.4

8721 - 8740 of 9641