Date   

[PATCH 5/7] i2c: sh_mobile: Add per-Generation fallback bindings

Biju Das <biju.das@...>
 

From: Simon Horman <horms+renesas@...>

Add per-Generation fallback bindings for R-Car SoCs.

This is in keeping with the compatibility string scheme is being adopted
for drivers for Renesas SoCs.

Also, improve readability by listing the rmobile fallback compatibility
string after the more-specific compatibility strings they provide a
fallback for.

Signed-off-by: Simon Horman <horms+renesas@...>
Acked-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Wolfram Sang <wsa@...>
(cherry picked from commit b880ccaf1742c28e91534ad7820c4405c04dabf9)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 17 ++++++++++++++---
drivers/i2c/busses/i2c-sh_mobile.c | 4 +++-
2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
index 214f94c..7716acc 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
@@ -1,8 +1,7 @@
Device tree configuration for Renesas IIC (sh_mobile) driver

Required properties:
-- compatible : "renesas,iic-<soctype>". "renesas,rmobile-iic" as fallback
- Examples with soctypes are:
+- compatible :
- "renesas,iic-r8a73a4" (R-Mobile APE6)
- "renesas,iic-r8a7740" (R-Mobile A1)
- "renesas,iic-r8a7790" (R-Car H2)
@@ -12,6 +11,17 @@ Required properties:
- "renesas,iic-r8a7794" (R-Car E2)
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
+ - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
+ - "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
+ - "renesas,rmobile-iic" (generic device)
+
+ When compatible with a generic R-Car version, nodes
+ must list the SoC-specific version corresponding to
+ the platform first followed by the generic R-Car
+ version.
+
+ renesas,rmobile-iic must always follow.
+
- reg : address start and address range size of device
- interrupts : interrupt of device
- clocks : clock for device
@@ -31,7 +41,8 @@ Pinctrl properties might be needed, too. See there.
Example:

iic0: i2c@e6500000 {
- compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
reg = <0 0xe6500000 0 0x425>;
interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 7d2bd3e..3eb5167 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -828,7 +828,6 @@ static const struct sh_mobile_dt_config r8a7740_dt_config = {
};

static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
- { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
{ .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
{ .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
{ .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
@@ -836,8 +835,11 @@ static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
{ .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
{ .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
{ .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
+ { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config },
{ .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
+ { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
{ .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
+ { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
{},
};
MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
--
2.7.4


[PATCH 4/7] ARM: dts: r8a7743: Add I2C DT support

Biju Das <biju.das@...>
 

Add the I2C[0-5] devices to the r8a7743 device tree.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 2d33ced5500320f55fd2f63364f1212ba19453e8)
(modified clk property,removed reset property)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 85 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index e755cb9..b7be573 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -18,6 +18,15 @@
#address-cells = <2>;
#size-cells = <2>;

+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -297,6 +306,82 @@
dma-channels = <15>;
};

+ /* The memory map in the User's Manual maps the cores to bus
+ * numbers
+ */
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7743_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7743_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7743_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7743_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7743_CLK_I2C4>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7743_CLK_I2C5>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7743", "renesas,scifa";
reg = <0 0xe6c40000 0 0x40>;
--
2.7.4


[PATCH 3/7] dt-bindings: i2c: Document r8a7743/5 support

Biju Das <biju.das@...>
 

Document i2c Device Tree support for RZ/G1[ME]
(also known as r8aA774[35]) SoCs. They are compatible with
R-Car Gen2 SoC family.

Signed-off-by: Biju Das <biju.das@...>
Acked-by: Simon Horman <horms+renesas@...>
Signed-off-by: Wolfram Sang <wsa@...>
(cherry picked from commit 4523656ff6cba7a217d44e5e8f726ccca2736473)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
index e26f224..f6cb9e5 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
@@ -2,6 +2,8 @@ I2C for R-Car platforms

Required properties:
- compatible:
+ "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
+ "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
@@ -11,7 +13,8 @@ Required properties:
"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
- "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device.
+ "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
+ device.
"renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device.
"renesas,i2c-rcar" (deprecated)

--
2.7.4


[PATCH 2/7] i2c: rcar: Add per-Generation fallback bindings

Biju Das <biju.das@...>
 

From: Simon Horman <horms+renesas@...>

In the case of Renesas R-Car hardware we know that there are generations of
SoCs, e.g. Gen 2 and Gen 3. But beyond that it's not clear what the
relationship between IP blocks might be. For example, I believe that
r8a7790 is older than r8a7791 but that doesn't imply that the latter is a
descendant of the former or vice versa.

We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.

For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme is being adopted for
drivers for Renesas SoCs.

Also:
* Deprecate renesas,i2c-rcar. It seems poorly named as it is only
compatible with R-Car Gen 1. It also appears unused in mainline.
* Add some text to describe per-SoC bindings

Signed-off-by: Simon Horman <horms+renesas@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Wolfram Sang <wsa@...>
(cherry picked from commit ad4a8dc3fec6485b18654d1090ef8012fcfc37b8)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>

Conflicts:
Documentation/devicetree/bindings/i2c/i2c-rcar.txt
drivers/i2c/busses/i2c-rcar.c
---
Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 30 ++++++++++++++--------
drivers/i2c/busses/i2c-rcar.c | 5 +++-
2 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
index dea14f7..e26f224 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
@@ -1,16 +1,24 @@
I2C for R-Car platforms

Required properties:
-- compatible: Must be one of
- "renesas,i2c-rcar"
- "renesas,i2c-r8a7778"
- "renesas,i2c-r8a7779"
- "renesas,i2c-r8a7790"
- "renesas,i2c-r8a7791"
- "renesas,i2c-r8a7792"
- "renesas,i2c-r8a7793"
- "renesas,i2c-r8a7794"
- "renesas,i2c-r8a7795"
+- compatible:
+ "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
+ "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
+ "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
+ "renesas,i2c-r8a7791" if the device is a part of a R8A7791 SoC.
+ "renesas,i2c-r8a7792" if the device is a part of a R8A7792 SoC.
+ "renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC.
+ "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
+ "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
+ "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
+ "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device.
+ "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device.
+ "renesas,i2c-rcar" (deprecated)
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first followed
+ by the generic version.
+
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt specifier.
@@ -25,7 +33,7 @@ Examples :
i2c0: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "renesas,i2c-r8a7791";
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index 599c0d7..aa3730d 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -618,7 +618,6 @@ static const struct i2c_algorithm rcar_i2c_algo = {
};

static const struct of_device_id rcar_i2c_dt_ids[] = {
- { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
@@ -627,6 +626,10 @@ static const struct of_device_id rcar_i2c_dt_ids[] = {
{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
{ .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
+ { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */
+ { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
+ { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
+ { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
{},
};
MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
--
2.7.4


[PATCH 1/7] dt-bindings: i2c: Spelling s/propoerty/property/

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Wolfram Sang <wsa@...>
(cherry picked from commit ddf3dc82f10e15469b3967ae777d39745d3aab16)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
Documentation/devicetree/bindings/i2c/i2c-imx.txt | 2 +-
Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 2 +-
Documentation/devicetree/bindings/i2c/i2c-sirf.txt | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
index eab5836..b967544 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
@@ -11,7 +11,7 @@ Required properties:

Optional properties:
- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
- The absence of the propoerty indicates the default frequency 100 kHz.
+ The absence of the property indicates the default frequency 100 kHz.
- dmas: A list of two dma specifiers, one for each entry in dma-names.
- dma-names: should contain "tx" and "rx".
- scl-gpios: specify the gpio related to SCL pin
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
index ea406eb2..dea14f7 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
@@ -17,7 +17,7 @@ Required properties:

Optional properties:
- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this
- propoerty indicates the default frequency 100 kHz.
+ property indicates the default frequency 100 kHz.
- clocks: clock specifier.

Examples :
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sirf.txt b/Documentation/devicetree/bindings/i2c/i2c-sirf.txt
index 7baf9e1..2701eef 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-sirf.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-sirf.txt
@@ -8,7 +8,7 @@ Required properties :

Optional properties:
- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
- The absence of the propoerty indicates the default frequency 100 kHz.
+ The absence of the property indicates the default frequency 100 kHz.

Examples :

--
2.7.4


[PATCH 0/7] Add i2c/iic support for r8a7743

Biju Das <biju.das@...>
 

This patch series aims to add i2c/iic support for r8a7743 SoC.

Backported dt-bindings patch
Backported per-Generation fallbacks

It is tested against linux-v4.4.112-cip18

This patch depends on the below patch series
https://lists.cip-project.org/pipermail/cip-dev/2018-January/000820.html

Biju Das (4):
dt-bindings: i2c: Document r8a7743/5 support
ARM: dts: r8a7743: Add I2C DT support
dt-bindings: i2c: sh_mobile: Document r8a7743/5 support
ARM: dts: r8a7743: Add IIC cores to dtsi

Geert Uytterhoeven (1):
dt-bindings: i2c: Spelling s/propoerty/property/

Simon Horman (2):
i2c: rcar: Add per-Generation fallback bindings
i2c: sh_mobile: Add per-Generation fallback bindings

Documentation/devicetree/bindings/i2c/i2c-imx.txt | 2 +-
Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 35 ++++--
.../devicetree/bindings/i2c/i2c-sh_mobile.txt | 20 ++-
Documentation/devicetree/bindings/i2c/i2c-sirf.txt | 2 +-
arch/arm/boot/dts/r8a7743.dtsi | 137 +++++++++++++++++++++
drivers/i2c/busses/i2c-rcar.c | 5 +-
drivers/i2c/busses/i2c-sh_mobile.c | 4 +-
7 files changed, 186 insertions(+), 19 deletions(-)

--
2.7.4


Re: CIP in the News

Chris Paterson
 

Hello all,

 

Yoshi-san’s and Urs’ talk also got a mention in Eric Brown’s article:

 

https://www.linux.com/blog/event/elc-open-iot/2018/1/elc-openiot-cloud-computing-robot-apocalypse

 

Kind regards, Chris

 

From: cip-dev-bounces@... [mailto:cip-dev-bounces@...] On Behalf Of Maemalynn Meanor
Sent: 01 February 2018 04:40
To: cip-members@...; cip-dev@...
Cc: Jeff ErnstFriedman <jernstfriedman@...>
Subject: [cip-dev] CIP in the News

 

CIP Community: 

 

IoT Evolution World showcased CIP in a feature article today. You can read the article here: http://www.iotevolutionworld.com/iot/articles/436745-smart-city-iot-infrastructure-moxa-joins-linux-foundations.htm

 

We ask that you please share this article with your social followers. You can retweet us here: https://twitter.com/cip_project/status/958920358769451008

 

Or, use the below suggested posts:  

 

Twitter: .@cip_project was featured in @IoTEvolution for its news about @MoxaInc joining the project. Learn more:  http://bit.ly/2nqRA7x #opensource #smartcities #IoT #Infrastructure



LinkedIn: IoT Evolution World features the news that Moxa joined the CIP Project in a new article. Read it here: http://bit.ly/2nqRA7x

 

Thanks so much for your help!

Maemalynn

 

Maemalynn Meanor

PR Manager 
The Linux Foundation
Maemalynn@...
(602) 541-0356
Skype: Maemalynn

 

 

 

 


CIP in the News

Maemalynn Meanor <maemalynn@...>
 

CIP Community: 

IoT Evolution World showcased CIP in a feature article today. You can read the article here: http://www.iotevolutionworld.com/iot/articles/436745-smart-city-iot-infrastructure-moxa-joins-linux-foundations.htm

We ask that you please share this article with your social followers. You can retweet us here: https://twitter.com/cip_project/status/958920358769451008

Or, use the below suggested posts:  

Twitter: .@cip_project was featured in @IoTEvolution for its news about @MoxaInc joining the project. Learn more:  http://bit.ly/2nqRA7x #opensource #smartcities #IoT #Infrastructure

LinkedIn: IoT Evolution World features the news that Moxa joined the CIP Project in a new article. Read it here: http://bit.ly/2nqRA7x

Thanks so much for your help!
Maemalynn

Maemalynn Meanor
PR Manager 
The Linux Foundation
Maemalynn@...
(602) 541-0356
Skype: Maemalynn






Re: [yocto] Generating Yocto SDK as .deb (Debian) pacakge

Khem Raj <raj.khem@...>
 

On Wed, Jan 31, 2018 at 4:31 AM, Zoran Stojsavljevic
<zoran.stojsavljevic@...> wrote:
I'll add here another list, since these people might be interested in
this thread/topic.
thats a fine idea you might want to look into

http://downloads.yoctoproject.org/releases/yocto/yocto-2.4.1/toolchain/

for prebuilt SDKs

Best Regards,
Zoran
_______

On Wed, Jan 31, 2018 at 9:05 AM, Gaurang Shastri <gmshastri@...> wrote:
Hi Team,

How can I generate Yocto generated SDK as .deb package? Currently it is in
the form of installable shell script but I want to generate it as .deb
package so that I can directly install it on my Ubuntu VM using "apt-get"
command.

Is this supported? Any documentation?

Regards,
Gaurang

--
_______________________________________________
yocto mailing list
yocto@...
https://lists.yoctoproject.org/listinfo/yocto
--
_______________________________________________
yocto mailing list
yocto@...
https://lists.yoctoproject.org/listinfo/yocto


Re: [yocto] Generating Yocto SDK as .deb (Debian) pacakge

Zoran Stojsavljevic <zoran.stojsavljevic@...>
 

I'll add here another list, since these people might be interested in
this thread/topic.

Best Regards,
Zoran
_______

On Wed, Jan 31, 2018 at 9:05 AM, Gaurang Shastri <gmshastri@...> wrote:
Hi Team,

How can I generate Yocto generated SDK as .deb package? Currently it is in
the form of installable shell script but I want to generate it as .deb
package so that I can directly install it on my Ubuntu VM using "apt-get"
command.

Is this supported? Any documentation?

Regards,
Gaurang

--
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yocto mailing list
yocto@...
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[PATCH 10/10] ARM: dts: r8a7743: Add missing clock for secondary CA15 CPU core

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit a60ddf507dda0ede43b72d348283d8725a5a83c7)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>

Conflicts:
arch/arm/boot/dts/r8a7743.dtsi
---
arch/arm/boot/dts/r8a7743.dtsi | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index e4e0dc3..e755cb9 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -46,6 +46,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
+ clocks = <&cpg_clocks R8A7743_CLK_Z>;
next-level-cache = <&L2_CA15>;
};

--
2.7.4


[PATCH 09/10] ARM: dts: r8a7743: Add OPP table for frequency scaling

Biju Das <biju.das@...>
 

Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.

- clock-latency = 300 us
Approximate worst-case latency to do clock transition for every
OPPs. Using an arbitrary safe value similar to r8a7791(R-Car M2) Soc.

- operating-points = < kHz - uV >
List of 6 operating points. All of them are using the same voltage
since DVS is not supported in RZ/G1 Soc.

Note:This also fixes the below errors seen on kernel logs
[ 0.876877] cpu cpu0: dev_pm_opp_get_opp_count: OPP table not found (-19)
[ 0.883727] cpu cpu1: cpufreq_init: failed to get clk: -2

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 0417814ea140d1bc7e8a5d54e95e17a234b34e49)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>

Conflicts:
arch/arm/boot/dts/r8a7743.dtsi
---
arch/arm/boot/dts/r8a7743.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index bd1121a..e4e0dc3 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -29,7 +29,16 @@
reg = <0>;
clock-frequency = <1500000000>;
clocks = <&cpg_clocks R8A7743_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
next-level-cache = <&L2_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
};

cpu1: cpu@1 {
--
2.7.4


[PATCH 08/10] ARM: dts: r8a7743: Add APMU node and second CPU core

Biju Das <biju.das@...>
 

Add DT nodes for the Advanced Power Management Unit (APMU) and the
second CPU core. Use the enable-method to point out that the APMU
should be used for SMP support.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 60dce695b097a52e6ea5874aa80301f2e4ac627a)
(removed power domain property, since we don't have sysc driver
in 4.4 kernel to support CA15-CPU1 and CA15-SCU power domains).

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index a9dda28..bd1121a 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -21,6 +21,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";

cpu0: cpu@0 {
device_type = "cpu";
@@ -31,6 +32,14 @@
next-level-cache = <&L2_CA15>;
};

+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ next-level-cache = <&L2_CA15>;
+ };
+
L2_CA15: cache-controller-0 {
compatible = "cache";
cache-unified;
@@ -46,6 +55,12 @@
#size-cells = <2>;
ranges;

+ apmu@e6152000 {
+ compatible = "renesas,r8a7743-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4


[PATCH 07/10] dt-bindings: apmu: Document r8a7743 support

Biju Das <biju.das@...>
 

Document APMU and SMP enable method for RZ/G1M
(also known as r8a7743) SoC.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 304ce59242e11e715bfdc86577771502df99f7cd)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
Documentation/devicetree/bindings/power/renesas,apmu.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt
index bc8de21..e3a0e55 100644
--- a/Documentation/devicetree/bindings/power/renesas,apmu.txt
+++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt
@@ -1,12 +1,13 @@
DT bindings for the Renesas Advanced Power Management Unit

-Renesas R-Car line of SoCs utilize one or more APMU hardware units
+Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units
for CPU core power domain control including SMP boot and CPU Hotplug.

Required properties:

- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
Examples with soctypes are:
+ - "renesas,r8a7743-apmu" (RZ/G1M)
- "renesas,r8a7790-apmu" (R-Car H2)
- "renesas,r8a7791-apmu" (R-Car M2-W)

--
2.7.4


[PATCH 06/10] devicetree: bindings: Renesas APMU and SMP Enable method

Biju Das <biju.das@...>
 

From: Magnus Damm <damm+renesas@...>

Add DT binding documentation for the APMU hardware and add "renesas,apmu"
to the list of enable methods for the ARM cpus.

Signed-off-by: Magnus Damm <damm+renesas@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Acked-by: Rob Herring <robh@...>
Cc: devicetree@...
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit e454b359b7a0a6f59e3d83394e6d4e598554cb33)
[removed r8a7792,r8a7793 and r8a7794 devices]
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
.../devicetree/bindings/power/renesas,apmu.txt | 28 ++++++++++++++++++++++
2 files changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/renesas,apmu.txt

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 3a07a87..9ef9a20 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -200,6 +200,7 @@ nodes to be present and contain the properties described below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
+ "renesas,apmu"
"rockchip,rk3066-smp"
"ste,dbx500-smp"

diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt
new file mode 100644
index 0000000..bc8de21
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt
@@ -0,0 +1,28 @@
+DT bindings for the Renesas Advanced Power Management Unit
+
+Renesas R-Car line of SoCs utilize one or more APMU hardware units
+for CPU core power domain control including SMP boot and CPU Hotplug.
+
+Required properties:
+
+- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
+ Examples with soctypes are:
+ - "renesas,r8a7790-apmu" (R-Car H2)
+ - "renesas,r8a7791-apmu" (R-Car M2-W)
+
+- reg: Base address and length of the I/O registers used by the APMU.
+
+- cpus: This node contains a list of CPU cores, which should match the order
+ of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
+ Management Unit section of the device's datasheet.
+
+
+Example:
+
+This shows the r8a7791 APMU that can control CPU0 and CPU1.
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
--
2.7.4


[PATCH 05/10] ARM: shmobile: apmu: Allow booting secondary CPU cores in debug mode

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Now debug resource reset is handled properly, allow booting secondary
CPU cores when hardware debug mode is enabled (MD21=1) on SoCs using the
"renesas,apmu" enable method.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Tested-by: Hiep Cao Minh <cm-hiep@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit d03c8f78d03af2a46127537dd1daa67164e53c09)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
arch/arm/mach-shmobile/platsmp-apmu.c | 14 +-------------
1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 81a687f..331409a 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -216,21 +216,9 @@ static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
rcar_gen2_pm_init();
}

-static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu,
- struct task_struct *idle)
-{
- /* Error out when hardware debug mode is enabled */
- if (rcar_gen2_read_mode_pins() & BIT(21)) {
- pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);
- return -ENOTSUPP;
- }
-
- return shmobile_smp_apmu_boot_secondary(cpu, idle);
-}
-
static struct smp_operations apmu_smp_ops __initdata = {
.smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt,
- .smp_boot_secondary = shmobile_smp_apmu_boot_secondary_md21,
+ .smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_can_disable = shmobile_smp_cpu_can_disable,
.cpu_die = shmobile_smp_apmu_cpu_die,
--
2.7.4


[PATCH 04/10] ARM: shmobile: apmu: Add debug resource reset for secondary CPU boot

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

In debug mode (MD21=1), reset requests derived from power-shutoff to the
AP-system CPU cores must be enabled before the AP-system CPU cores
resume from power-shutoff for the first time. Else resume may fail,
causing the system to hang during boot.

As setting these bits is a no-op in normal mode, there's no need to
check the actual state of MD21 first.

Inspired by CPU-specific patches in the BSP by Hisashi Nakamura
<hisashi.nakamura.ak@...>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Tested-by: Hiep Cao Minh <cm-hiep@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 10f778a97845e8b10af8878af99c9cfe6c31baf9)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>

Conflicts:
arch/arm/mach-shmobile/platsmp-apmu.c
---
arch/arm/mach-shmobile/platsmp-apmu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 444765e..81a687f 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -35,6 +35,13 @@ static struct {
#define PSTR_OFFS 0x40
#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))

+#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */
+
+/* Debug Resource Reset Control Register */
+#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */
+#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */
+#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */
+
static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
{
/* request power on */
@@ -78,6 +85,8 @@ static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)
#ifdef CONFIG_SMP
static void apmu_init_cpu(struct resource *res, int cpu, int bit)
{
+ u32 x;
+
if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
return;

@@ -85,6 +94,11 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit)
apmu_cpus[cpu].bit = bit;

pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
+
+ /* Setup for debug mode */
+ x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);
+ x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN;
+ writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
}

static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
--
2.7.4


[PATCH 03/10] ARM: shmobile: apmu: Add APMU DT support via Enable method

Biju Das <biju.das@...>
 

From: Magnus Damm <damm+renesas@...>

Allow DT configuration of the APMU hardware in the case when the APMU is
pointed out in the DTB via the enable-method. The ability to configure
the APMU via C code is still kept intact to prevent DTB breakage for older
SoCs that do not rely on the enable-method for SMP support.

Signed-off-by: Magnus Damm <damm+renesas@...>
[geert: Fix CONFIG_SMP=n build]
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>

(cherry picked from commit 5f3bca0db8ac01a73622361f6062939638bf4730)
(Backported APMU DT support via Enable method)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>

Conflicts:
arch/arm/mach-shmobile/platsmp-apmu.c
---
arch/arm/mach-shmobile/platsmp-apmu.c | 90 ++++++++++++++++++++++++++++++++++-
1 file changed, 89 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index cff623f..444765e 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -24,6 +24,7 @@
#include <asm/suspend.h>
#include "common.h"
#include "platsmp-apmu.h"
+#include "rcar-gen2.h"

static struct {
void __iomem *iomem;
@@ -118,12 +119,68 @@ static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
}
}

+static const struct of_device_id apmu_ids[] = {
+ { .compatible = "renesas,apmu" },
+ { /*sentinel*/ }
+};
+
+static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
+{
+ struct device_node *np_apmu, *np_cpu;
+ struct resource res;
+ int bit, index;
+ u32 id;
+
+ for_each_matching_node(np_apmu, apmu_ids) {
+ /* only enable the cluster that includes the boot CPU */
+ bool is_allowed = false;
+
+ for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
+ np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
+ if (np_cpu) {
+ if (!of_property_read_u32(np_cpu, "reg", &id)) {
+ if (id == cpu_logical_map(0)) {
+ is_allowed = true;
+ of_node_put(np_cpu);
+ break;
+ }
+
+ }
+ of_node_put(np_cpu);
+ }
+ }
+ if (!is_allowed)
+ continue;
+
+ for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
+ np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
+ if (np_cpu) {
+ if (!of_property_read_u32(np_cpu, "reg", &id)) {
+ index = get_logical_index(id);
+ if ((index >= 0) &&
+ !of_address_to_resource(np_apmu,
+ 0, &res))
+ fn(&res, index, bit);
+ }
+ of_node_put(np_cpu);
+ }
+ }
+ }
+}
+
+static void __init shmobile_smp_apmu_setup_boot(void)
+{
+ /* install boot code shared by all CPUs */
+ shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+ shmobile_boot_arg = MPIDR_HWID_BITMASK;
+}
+
void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
struct rcar_apmu_config *apmu_config,
int num)
{
/* install boot code shared by all CPUs */
- shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+ shmobile_smp_apmu_setup_boot();
shmobile_boot_arg = MPIDR_HWID_BITMASK;

/* perform per-cpu setup */
@@ -137,7 +194,38 @@ int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)

return apmu_wrap(cpu, apmu_power_on);
}
+
+static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
+{
+ shmobile_smp_apmu_setup_boot();
+ apmu_parse_dt(apmu_init_cpu);
+ rcar_gen2_pm_init();
+}
+
+static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu,
+ struct task_struct *idle)
+{
+ /* Error out when hardware debug mode is enabled */
+ if (rcar_gen2_read_mode_pins() & BIT(21)) {
+ pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);
+ return -ENOTSUPP;
+ }
+
+ return shmobile_smp_apmu_boot_secondary(cpu, idle);
+}
+
+static struct smp_operations apmu_smp_ops __initdata = {
+ .smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt,
+ .smp_boot_secondary = shmobile_smp_apmu_boot_secondary_md21,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_can_disable = shmobile_smp_cpu_can_disable,
+ .cpu_die = shmobile_smp_apmu_cpu_die,
+ .cpu_kill = shmobile_smp_apmu_cpu_kill,
#endif
+};
+
+CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);
+#endif /* CONFIG_SMP */

#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
/* nicked from arch/arm/mach-exynos/hotplug.c */
--
2.7.4


[PATCH 02/10] ARM: shmobile: apmu: Move #ifdef CONFIG_SMP to cover more functions #ifdef

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

shmobile_smp_apmu_prepare_cpus() is used only if CONFIG_SMP=y.

Hence move the #ifdef to cover shmobile_smp_apmu_prepare_cpus() and all
functions only called by it (apmu_init_cpu() and apmu_parse_cfg()).

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit d3f3fb0cfdcf4cbf69af65e8bfdde65cedf4e53a)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
arch/arm/mach-shmobile/platsmp-apmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 911884f..cff623f 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -74,6 +74,7 @@ static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)
return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
}

+#ifdef CONFIG_SMP
static void apmu_init_cpu(struct resource *res, int cpu, int bit)
{
if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
@@ -129,7 +130,6 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
}

-#ifdef CONFIG_SMP
int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/* For this particular CPU register boot vector */
--
2.7.4


[PATCH 01/10] ARM: shmobile: Add pm support for r8a7743

Biju Das <biju.das@...>
 

Adding pm support for r8a7743 SoC.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
---
arch/arm/mach-shmobile/pm-rcar-gen2.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index 6815781..94a2759 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -82,6 +82,9 @@ void __init rcar_gen2_pm_init(void)
} else if (of_machine_is_compatible("renesas,r8a7791")) {
boot_vector_addr = RAM;
syscier = 0x00111003;
+ } else if (of_machine_is_compatible("renesas,r8a7743")) {
+ boot_vector_addr = RAM;
+ syscier = 0x00101003;
}

/* RAM for jump stub, because BAR requires 256KB aligned address */
--
2.7.4

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