Date   

[PATCH 4.4.y-cip 01/14] ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically

Lad Prabhakar
 

commit be571bec2cfdb7aaa096d547aa8a1559a0c0cc90 upstream.

Sort the DT nodes alphabetically so that its easier to maintain.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200816193316.7641-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
index 85aff429d408..6e8df79bea94 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -35,13 +35,6 @@
clock-frequency = <20000000>;
};

-&pfc {
- mmc1_pins: mmc1 {
- groups = "mmc1_data4", "mmc1_ctrl";
- function = "mmc1";
- };
-};
-
&mmcif1 {
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
@@ -51,3 +44,10 @@
non-removable;
status = "okay";
};
+
+&pfc {
+ mmc1_pins: mmc1 {
+ groups = "mmc1_data4", "mmc1_ctrl";
+ function = "mmc1";
+ };
+};
--
2.17.1


[PATCH 4.4.y-cip 00/14] Renesas RZ/G1H add support for CAN, IPMMU, QSPI, RTC

Lad Prabhakar
 

Hi All,

This patch series adds support for below peripherals (along with fixes to
msiof driver),
* CAN
* IPMMU
* QSPI
* RTC

All the patches have been cherry picked from upstream kernel.

Cheers,
Prabhakar

Geert Uytterhoeven (2):
spi: sh-msiof: Avoid writing to registers from spi_master.setup()
spi: sh-msiof: Implement cs-gpios configuration

Lad Prabhakar (12):
ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically
ARM: dts: r8a7742-iwg21m: Add RTC support
spi: renesas,rspi: Add r8a7742 to the compatible list
ARM: dts: r8a7742: Add QSPI support
ARM: dts: r8a7742-iwg21m: Add SPI NOR support
ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support
pinctrl: sh-pfc: r8a7790: Add CAN pins, groups and functions
dt-bindings: can: rcar_can: Add r8a7742 support
ARM: dts: r8a7742: Add CAN support
ARM: dts: r8a7742-iwg21d-q7: Add can1 support to carrier board
ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add can0 support to camera DB
ARM: dts: r8a7742: Add IPMMU DT nodes

.../devicetree/bindings/net/can/rcar_can.txt | 3 +-
.../devicetree/bindings/spi/spi-rspi.txt | 1 +
.../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 11 ++
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 52 ++++++++
arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 79 +++++++++++-
arch/arm/boot/dts/r8a7742.dtsi | 90 ++++++++++++++
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 112 +++++++++++++++++-
drivers/spi/spi-sh-msiof.c | 92 +++++++++++---
8 files changed, 418 insertions(+), 22 deletions(-)

--
2.17.1


ISAR Populate SDK

Rajashree Sankar <rajashree.sankar@...>
 

Hello All,
In the ISAR framework,we ran the command to generate SDK
  bitbake <image_name> -c populate_sdk
There was an sdkchroot folder generated in tmp directory.
The instructions given in the readme of this folder tells us to use rootfs of the target.
Should we specify the rootfs  folder of the generated image? If not Please give us detailed instructions.

I have attached the readme file for your reference.
Thanks and Regards,
Rajashree Sankar

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Re: ISAR Populate SDK

Jan Kiszka
 

On 09.11.20 09:56, Rajashree Sankar wrote:
Hello All,
In the ISAR framework,we ran the command to generate SDK
  *bitbake <image_name> -c populate_sdk*
There was an sdkchroot folder generated in tmp directory.
The instructions given in the readme of this folder tells us to use
rootfs of the target.
Should we specify the rootfs  folder of the generated image? If not
Please give us detailed instructions.

I have attached the readme file for your reference.
Thanks and Regards,
Rajashree Sankar
You are on the wrong list again.

Jan

--
Siemens AG, T RDA IOT
Corporate Competence Center Embedded Linux


Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Lad Prabhakar
 

Hi Nobuhiro, Pavel,

-----Original Message-----
From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
Sent: 09 November 2020 01:46
To: pavel@denx.de; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Hi all,

-----Original Message-----
From: Pavel Machek [mailto:pavel@denx.de]
Sent: Saturday, November 7, 2020 4:33 PM
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Hi!

This patch series adds support for PCIe, SATA and VSP.

All the patches have been cherry-picked from Linux v5.10-rc2.
I don't see any problems with the series, and it passed basic testing,
so I can apply it if there are no other comments.
I reviewed this patch series, there was no issue.
So, I applied and pushed.
Thank you for the review and acceptance.

Cheers,
Prabhakar


Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Nobuhiro Iwamatsu
 

Hi all,

-----Original Message-----
From: Pavel Machek [mailto:pavel@denx.de]
Sent: Saturday, November 7, 2020 4:33 PM
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Hi!

This patch series adds support for PCIe, SATA and VSP.

All the patches have been cherry-picked from Linux v5.10-rc2.
I don't see any problems with the series, and it passed basic testing,
so I can apply it if there are no other comments.
I reviewed this patch series, there was no issue.
So, I applied and pushed.

Best regards,
Nobuhiro


Re: [PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Pavel Machek
 

Hi!

This patch series adds support for PCIe, SATA and VSP.

All the patches have been cherry-picked from Linux v5.10-rc2.
I don't see any problems with the series, and it passed basic testing,
so I can apply it if there are no other comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


[PATCH 4.4.y-cip 8/8] ARM: dts: r8a7742: Add VSP support

Lad Prabhakar
 

commit a937909702e00d98eac5b91b31a7f2ae112f47bf upstream.

Add VSP support to R8A7742 (RZ/G1H) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200911080929.15058-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: dropped resets property. changed clocks and power-domains properties.
added vsp device configuration]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 55 ++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index ae7c8cbf9f79..eff54f7ed812 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -1617,6 +1617,61 @@
status = "disabled";
};

+ vsp@fe920000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe920000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7742_CLK_VSP1_R>;
+ power-domains = <&cpg_clocks>;
+
+ renesas,has-sru;
+ renesas,#rpf = <5>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <4>;
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7742_CLK_VSP1_S>;
+ power-domains = <&cpg_clocks>;
+
+ renesas,has-lut;
+ renesas,has-sru;
+ renesas,#rpf = <5>;
+ renesas,#uds = <3>;
+ renesas,#wpf = <4>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7742_CLK_VSP1_DU0>;
+ power-domains = <&cpg_clocks>;
+
+ renesas,has-lif;
+ renesas,has-lut;
+ renesas,#rpf = <4>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <4>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7742_CLK_VSP1_DU1>;
+ power-domains = <&cpg_clocks>;
+
+ renesas,has-lif;
+ renesas,has-lut;
+ renesas,#rpf = <4>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <4>;
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7742",
"renesas,cmt-48-gen2";
--
2.17.1


[PATCH 4.4.y-cip 7/8] ARM: dts: r8a7742: Add SATA nodes

Lad Prabhakar
 

commit b9884a16398161bea177f48ddc05884741a8b944 upstream.

Add the SATA device nodes to the R8A7742 device tree.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/1589555337-5498-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: changed clocks and power-domain properties, removed resets property]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 0268c46d8f59..ae7c8cbf9f79 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -1557,6 +1557,26 @@
status = "disabled";
};

+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7742",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7742_CLK_SATA0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7742",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee500000 0 0x200000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7742_CLK_SATA1>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1


[PATCH 4.4.y-cip 6/8] dt-bindings: ata: renesas,rcar-sata: Add r8a7742 support

Lad Prabhakar
 

commit 33e70291d1ded119313ac1c20346a1f9f3b3b66f upstream.

Document SATA support for the RZ/G1H, which is compatible with
R-Car Gen2 SoC family.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
[PL: Manually applied changes to text version of binding file]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/ata/sata_rcar.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt
index ee0a4b6d615f..2c3a2eba0258 100644
--- a/Documentation/devicetree/bindings/ata/sata_rcar.txt
+++ b/Documentation/devicetree/bindings/ata/sata_rcar.txt
@@ -2,6 +2,7 @@

Required properties:
- compatible : should contain one or more of the following:
+ - "renesas,sata-r8a7742" for RZ/G1H
- "renesas,sata-r8a7779" for R-Car H1
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
--
2.17.1


[PATCH 4.4.y-cip 5/8] ata: sata_rcar: Fix DMA boundary mask

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit df9c590986fdb6db9d5636d6cd93bc919c01b451 upstream.

Before commit 9495b7e92f716ab2 ("driver core: platform: Initialize
dma_parms for platform devices"), the R-Car SATA device didn't have DMA
parameters. Hence the DMA boundary mask supplied by its driver was
silently ignored, as __scsi_init_queue() doesn't check the return value
of dma_set_seg_boundary(), and the default value of 0xffffffff was used.

Now the device has gained DMA parameters, the driver-supplied value is
used, and the following warning is printed on Salvator-XS:

DMA-API: sata_rcar ee300000.sata: mapping sg segment across boundary [start=0x00000000ffffe000] [end=0x00000000ffffefff] [boundary=0x000000001ffffffe]
WARNING: CPU: 5 PID: 38 at kernel/dma/debug.c:1233 debug_dma_map_sg+0x298/0x300

(the range of start/end values depend on whether IOMMU support is
enabled or not)

The issue here is that SATA_RCAR_DMA_BOUNDARY doesn't have bit 0 set, so
any typical end value, which is odd, will trigger the check.

Fix this by increasing the DMA boundary value by 1.

This also fixes the following WRITE DMA EXT timeout issue:

# dd if=/dev/urandom of=/mnt/de1/file1-1024M bs=1M count=1024
ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
ata1.00: failed command: WRITE DMA EXT
ata1.00: cmd 35/00:00:00:e6:0c/00:0a:00:00:00/e0 tag 0 dma 1310720 out
res 40/00:01:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
ata1.00: status: { DRDY }

as seen by Shimoda-san since commit 429120f3df2dba2b ("block: fix
splitting segments on boundary masks").

Fixes: 8bfbeed58665dbbf ("sata_rcar: correct 'sata_rcar_sht'")
Fixes: 9495b7e92f716ab2 ("driver core: platform: Initialize dma_parms for platform devices")
Fixes: 429120f3df2dba2b ("block: fix splitting segments on boundary masks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/ata/sata_rcar.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index a3fee38a3635..8f43669ca29e 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -122,7 +122,7 @@
/* Descriptor table word 0 bit (when DTA32M = 1) */
#define SATA_RCAR_DTEND BIT(0)

-#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
+#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL

/* Gen2 Physical Layer Control Registers */
#define RCAR_GEN2_PHY_CTL1_REG 0x1704
--
2.17.1


[PATCH 4.4.y-cip 4/8] ata: sata_rcar: add gen[23] fallback compatibility strings

Lad Prabhakar
 

From: Simon Horman <horms+renesas@verge.net.au>

commit 6ac1d1532c888b030acb3b4ac82425448cb15198 upstream.

Add fallback compatibility string for R-Car Gen 2 and 3.

In the case of Renesas R-Car hardware we know that there are generations of
SoCs, e.g. Gen 1 and 2. But beyond that its not clear what the relationship
between IP blocks might be. For example, I believe that r8a7790 is older
than r8a7791 but that doesn't imply that the latter is a descendant of the
former or vice versa.

We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.

For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme being adopted for
drivers for Renesas SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tejun Heo <tj@kernel.org>
[PL: Dropped R-Car Gen3 support]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/ata/sata_rcar.txt | 13 ++++++++++---
drivers/ata/sata_rcar.c | 4 ++++
2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt
index 2493a5a31655..ee0a4b6d615f 100644
--- a/Documentation/devicetree/bindings/ata/sata_rcar.txt
+++ b/Documentation/devicetree/bindings/ata/sata_rcar.txt
@@ -1,13 +1,20 @@
* Renesas R-Car SATA

Required properties:
-- compatible : should contain one of the following:
+- compatible : should contain one or more of the following:
- "renesas,sata-r8a7779" for R-Car H1
- ("renesas,rcar-sata" is deprecated)
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
- "renesas,sata-r8a7791" for R-Car M2-W
- "renesas,sata-r8a7793" for R-Car M2-N
+ - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
+ - "renesas,rcar-sata" is deprecated
+
+ When compatible with the generic version nodes
+ must list the SoC-specific version corresponding
+ to the platform first followed by the generic
+ version.
+
- reg : address and length of the SATA registers;
- interrupts : must consist of one interrupt specifier.
- clocks : must contain a reference to the functional clock.
@@ -15,7 +22,7 @@ Required properties:
Example:

sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7791";
+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 4199f7a39be0..a3fee38a3635 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -856,6 +856,10 @@ static struct of_device_id sata_rcar_match[] = {
.compatible = "renesas,sata-r8a7793",
.data = (void *)RCAR_GEN2_SATA
},
+ {
+ .compatible = "renesas,rcar-gen2-sata",
+ .data = (void *)RCAR_GEN2_SATA
+ },
{ },
};
MODULE_DEVICE_TABLE(of, sata_rcar_match);
--
2.17.1


[PATCH 4.4.y-cip 3/8] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller

Lad Prabhakar
 

commit a0be3c32b15675e9f9dc0d3dc4e0361c019b93d8 upstream.

Enable PCIe Controller and set PCIe bus clock frequency.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200825162718.5838-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
index 428c494d88a3..858d206514e0 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
@@ -134,6 +134,18 @@
status = "okay";
};

+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec {
+ /* SW2[6] determines which connector is activated
+ * ON = PCIe X4 (connector-J7)
+ * OFF = mini-PCIe (connector-J26)
+ */
+ status = "okay";
+};
+
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
--
2.17.1


[PATCH 4.4.y-cip 2/8] ARM: dts: r8a7742: Add PCIe Controller device node

Lad Prabhakar
 

commit ebe5f898b60b341bd223d835dd3d7d77a5b38979 upstream.

Add a device node for the PCIe controller on the Renesas
RZ/G1H (r8a7742) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200810174156.30880-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: changed clocks and power-domain properties, removed resets property]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index e37f65655479..0268c46d8f59 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -594,6 +594,13 @@
clock-frequency = <0>;
};

+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
pmu-0 {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -1563,6 +1570,33 @@
power-domains = <&cpg_clocks>;
};

+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7742",
+ "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7742_CLK_PCIEC>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7742",
"renesas,cmt-48-gen2";
--
2.17.1


[PATCH 4.4.y-cip 1/8] dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r8a7742

Lad Prabhakar
 

commit c6233c504974f131445a21891de725d1ac4d116c upstream.

Add internal PCI bridge support for r8a7742 SoC. The Renesas RZ/G1H
(R8A7742) internal PCI bridge is identical to the R-Car Gen2 family.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index 8ea3ec0c535a..7857d87646cf 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -6,7 +6,8 @@ AHB. There is one bridge instance per USB port connected to the internal
OHCI and EHCI controllers.

Required properties:
-- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC;
+- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC;
+ "renesas,pci-r8a7743" for the R8A7743 SoC;
"renesas,pci-r8a7744" for the R8A7744 SoC;
"renesas,pci-r8a7745" for the R8A7745 SoC;
"renesas,pci-r8a7790" for the R8A7790 SoC;
--
2.17.1


[PATCH 4.4.y-cip 0/8] Renesas RZ/G1H add PCIe, SATA and VSP support

Lad Prabhakar
 

Hi All,

This patch series adds support for PCIe, SATA and VSP.

All the patches have been cherry-picked from Linux v5.10-rc2.

Cheers,
Prabhakar

Geert Uytterhoeven (1):
ata: sata_rcar: Fix DMA boundary mask

Lad Prabhakar (6):
dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r8a7742
ARM: dts: r8a7742: Add PCIe Controller device node
ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller
dt-bindings: ata: renesas,rcar-sata: Add r8a7742 support
ARM: dts: r8a7742: Add SATA nodes
ARM: dts: r8a7742: Add VSP support

Simon Horman (1):
ata: sata_rcar: add gen[23] fallback compatibility strings

.../devicetree/bindings/ata/sata_rcar.txt | 14 ++-
.../devicetree/bindings/pci/pci-rcar-gen2.txt | 3 +-
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 12 ++
arch/arm/boot/dts/r8a7742.dtsi | 109 ++++++++++++++++++
drivers/ata/sata_rcar.c | 6 +-
5 files changed, 139 insertions(+), 5 deletions(-)

--
2.17.1


Re: [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add USB{2,3} support

Lad Prabhakar
 

Hi Nobuhiro,Pavel,

-----Original Message-----
From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
Sent: 06 November 2020 07:10
To: pavel@denx.de; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add USB{2,3} support

Hi,

-----Original Message-----
From: Pavel Machek [mailto:pavel@denx.de]
Sent: Thursday, November 5, 2020 9:12 PM
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add USB{2,3} support

Hi!

This patch series adds USB{2,3} support to Renesas RZ/G2H SoC.

All the patches have been cherry-picked from Linux v5.10-rc2.
Series looks ok to me and passes our testing, I can apply it if there
are no other comments.
Looks good to me too. I applied and pushed to kernel.org.
Thank you for the review and acceptance.

Cheers,
Prabhakar


Re: [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add USB{2,3} support

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: Pavel Machek [mailto:pavel@denx.de]
Sent: Thursday, November 5, 2020 9:12 PM
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add USB{2,3} support

Hi!

This patch series adds USB{2,3} support to Renesas RZ/G2H SoC.

All the patches have been cherry-picked from Linux v5.10-rc2.
Series looks ok to me and passes our testing, I can apply it if there
are no other comments.
Looks good to me too. I applied and pushed to kernel.org.

Best regards,
Nobuhiro


cip-kernel-sec Updates for Week of 2020-11-05

Chen-Yu Tsai <wens213@...>
 

New CVEs:

- CVE-2020-25668 [concurrency use-after-free in vt] - fixed for v4.19 and later
- CVE-2020-25670 [net/nfc/llcp res. leak]
- CVE-2020-25671 [net/nfc/llcp res. leak]
- CVE-2020-25672 [net/nfc/llcp res. leak]
- CVE-2020-25673 [net/nfc/llcp res. leak]

No member enables NFC so we can ignore 25670 ~ 25673.

Old CVEs now fixed:

- CVE-2020-25656 [use-after-free in vt_do_kdgkb_ioctl] - fixed for
v4.14 and later

For CVE-2020-25668, the commit log says the bug has been around for at
least 12 years,
so likely needing a backport to older kernels.

For CVE-2020-25656, we still need to identify when it was introduced.

Regards,
ChenYu
Moxa


Re: cip-kernel-sec Updates for Last Week of October

Chen-Yu Tsai (Moxa) <wens@...>
 

On Tue, Nov 3, 2020 at 5:12 AM Pavel Machek <pavel@denx.de> wrote:

Hi!

- Fix for CVE-2020-27673 has not been backported yet.
Some kind of Xen issue, not really relevant to us, and fix is not
easy.

I'd say we can ignore this one.
This is queued for 4.19.155:

| a9d6e970261d 0891fb39ba67 o: | xen/events: don't use chip_data for legacy IRQs
| d103e667bb8c 073d0552ead5 o: | xen/events: avoid removing an event channel while handling it
| ed86a5182306 4d3fe31bd993 o: | xen/events: add a proper barrier to 2-level uevent unmasking
| 6e894d279f4e f01337197419 o: | xen/events: fix race in evtchn_fifo_unmask()
| 0279bd8ca365 54c9de89895e o: | xen/events: add a new "late EOI" evtchn framework
| adc67cdf742f 01263a1fabe3 .: | xen/blkback: use lateeoi irq binding
| 322a5dc88d82 23025393dbeb .: | xen/netback: use lateeoi irq binding
| 515827d40949 86991b6e7ea6 .: | xen/scsiback: use lateeoi irq binding
| f2db1b870c08 c8d647a326f0 .: | xen/pvcallsback: use lateeoi irq binding
| 8b0ac9a498d2 c2711441bc96 .: | xen/pciback: use lateeoi irq binding
| 757d54717fae c44b849cee8c o: | xen/events: switch user event channels to lateeoi model
| c3c580896847 7beb290caa2a o: | xen/events: use a common cpu hotplug hook for event channels
| 7835cdf92784 e99502f76271 o: | xen/events: defer eoi in case of excessive number of events
| f8bf3977d67c 5f7f77400ab5 o: | xen/events: block rogue events for some time

"defer eoi" should be fix for this bug.

So..we don't need to do anything here, and it will get fixed.
Confirmed. The fixes for CVE-2020-27673 and 27675 are part of 4.19.155.

Looks like there is no backport for older LTS branches though.

ChenYu

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