Date   

[RESEND PATCH 5.10.y-cip 38/40] arm64: dts: renesas: r9a07g044: Add SDHI nodes

Lad Prabhakar
 

From: Biju Das <biju.das.jz@...>

commit a83ad872f4ba6b9fbf81b9f70d6ff6d61d74bf7e upstream.

Add SDHI{0, 1} nodes to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@...>
Link: https://lore.kernel.org/r/20211007155451.10654-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index ebe155ccd721..468a3d8cbd1f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -460,6 +460,38 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};

+ sdhi0: mmc@11c00000 {
+ compatible = "renesas,sdhi-r9a07g044",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x11c00000 0 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
+ <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
+ <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
+ <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
+ clock-names = "imclk", "imclk2", "clk_hs", "aclk";
+ resets = <&cpg R9A07G044_SDHI0_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sdhi1: mmc@11c10000 {
+ compatible = "renesas,sdhi-r9a07g044",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x11c10000 0 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
+ <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
+ <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
+ <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
+ clock-names = "imclk", "imclk2", "clk_hs", "aclk";
+ resets = <&cpg R9A07G044_SDHI1_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
eth0: ethernet@11c20000 {
compatible = "renesas,r9a07g044-gbeth",
"renesas,rzg2l-gbeth";
--
2.17.1


[RESEND PATCH 5.10.y-cip 37/40] dt-bindings: mmc: renesas,sdhi: Rename RZ/G2L clocks

Lad Prabhakar
 

From: Biju Das <biju.das.jz@...>

commit 217c7d1840b5377543eff84fe28409d0bd4d3433 upstream.

Rename the below RZ/G2L clocks to match with the clock names used in
R-Car Gen2 and later generations.

imclk->core
clk_hs->clkh
imclk2->cd

This changes will avoid using fallback for RZ/G2L high speed clock,
if "clkh" is not used in device tree and also the code changes in
driver related to this clocks.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Wolfram Sang <wsa+renesas@...>
Acked-by: Ulf Hansson <ulf.hansson@...>
Link: https://lore.kernel.org/r/20211122103905.14439-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index c20ee9e5b8e8..3aeff9036628 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -112,17 +112,17 @@ allOf:
clocks:
items:
- description: IMCLK, SDHI channel main clock1.
+ - description: CLK_HS, SDHI channel High speed clock which operates
+ 4 times that of SDHI channel main clock1.
- description: IMCLK2, SDHI channel main clock2. When this clock is
turned off, external SD card detection cannot be
detected.
- - description: CLK_HS, SDHI channel High speed clock which operates
- 4 times that of SDHI channel main clock1.
- description: ACLK, SDHI channel bus clock.
clock-names:
items:
- - const: imclk
- - const: imclk2
- - const: clk_hs
+ - const: core
+ - const: clkh
+ - const: cd
- const: aclk
required:
- clock-names
--
2.17.1


[RESEND PATCH 5.10.y-cip 36/40] dt-bindings: mmc: renesas,sdhi: Add optional SDnH clock

Lad Prabhakar
 

From: Wolfram Sang <wsa+renesas@...>

commit e051025efac3929ca7e3e2f2c8860d3447366ebc upstream.

This only applies to R-Car Gen2 and later generations, so we need to
distinguish.

Signed-off-by: Wolfram Sang <wsa+renesas@...>
Acked-by: Ulf Hansson <ulf.hansson@...>
Link: https://lore.kernel.org/r/20211115160600.4455-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 38 ++++++++++++++-----
1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 77b1bb907497..c20ee9e5b8e8 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -128,15 +128,35 @@ allOf:
- clock-names
- resets
else:
- properties:
- clocks:
- minItems: 1
- maxItems: 2
- clock-names:
- minItems: 1
- items:
- - const: core
- - const: cd
+ if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-sdhi
+ - renesas,rcar-gen3-sdhi
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 3
+ clock-names:
+ minItems: 1
+ uniqueItems: true
+ items:
+ - const: core
+ - enum: [ clkh, cd ]
+ - const: cd
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+ clock-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: cd

- if:
properties:
--
2.17.1


[RESEND PATCH 5.10.y-cip 35/40] dt-bindings: mmc: renesas,sdhi: Document RZ/G2L bindings

Lad Prabhakar
 

From: Biju Das <biju.das.jz@...>

commit bfadee4554c3782bfbc5943866bd2ad44d631e50 upstream.

Document RZ/G2L SDHI controller bindings.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Rob Herring <robh@...>
Link: https://lore.kernel.org/r/20210817090313.31858-3-biju.das.jz@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
[PL: Manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 71 +++++++++++++------
1 file changed, 51 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 16050b29bc89..77b1bb907497 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -44,18 +44,19 @@ properties:
- const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
- items:
- enum:
- - renesas,sdhi-r8a774a1 # RZ/G2M
- - renesas,sdhi-r8a774b1 # RZ/G2N
- - renesas,sdhi-r8a774c0 # RZ/G2E
- - renesas,sdhi-r8a774e1 # RZ/G2H
- - renesas,sdhi-r8a7795 # R-Car H3
- - renesas,sdhi-r8a7796 # R-Car M3-W
- - renesas,sdhi-r8a77961 # R-Car M3-W+
- - renesas,sdhi-r8a77965 # R-Car M3-N
- - renesas,sdhi-r8a77970 # R-Car V3M
- - renesas,sdhi-r8a77980 # R-Car V3H
- - renesas,sdhi-r8a77990 # R-Car E3
- - renesas,sdhi-r8a77995 # R-Car D3
+ - renesas,sdhi-r8a774a1 # RZ/G2M
+ - renesas,sdhi-r8a774b1 # RZ/G2N
+ - renesas,sdhi-r8a774c0 # RZ/G2E
+ - renesas,sdhi-r8a774e1 # RZ/G2H
+ - renesas,sdhi-r8a7795 # R-Car H3
+ - renesas,sdhi-r8a7796 # R-Car M3-W
+ - renesas,sdhi-r8a77961 # R-Car M3-W+
+ - renesas,sdhi-r8a77965 # R-Car M3-N
+ - renesas,sdhi-r8a77970 # R-Car V3M
+ - renesas,sdhi-r8a77980 # R-Car V3H
+ - renesas,sdhi-r8a77990 # R-Car E3
+ - renesas,sdhi-r8a77995 # R-Car D3
+ - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2

reg:
@@ -65,15 +66,9 @@ properties:
minItems: 1
maxItems: 3

- clocks:
- minItems: 1
- maxItems: 2
+ clocks: true

- clock-names:
- minItems: 1
- items:
- - const: core
- - const: cd
+ clock-names: true

dmas:
minItems: 4
@@ -107,6 +102,42 @@ properties:
allOf:
- $ref: "mmc-controller.yaml"

+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,sdhi-r9a07g044
+ then:
+ properties:
+ clocks:
+ items:
+ - description: IMCLK, SDHI channel main clock1.
+ - description: IMCLK2, SDHI channel main clock2. When this clock is
+ turned off, external SD card detection cannot be
+ detected.
+ - description: CLK_HS, SDHI channel High speed clock which operates
+ 4 times that of SDHI channel main clock1.
+ - description: ACLK, SDHI channel bus clock.
+ clock-names:
+ items:
+ - const: imclk
+ - const: imclk2
+ - const: clk_hs
+ - const: aclk
+ required:
+ - clock-names
+ - resets
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+ clock-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: cd
+
- if:
properties:
compatible:
--
2.17.1


[RESEND PATCH 5.10.y-cip 34/40] dt-bindings: mmc: renesas,sdhi: Fix dtbs-check warning

Lad Prabhakar
 

From: Biju Das <biju.das.jz@...>

commit 4aba5dc71eae041aa1a9240de10ad2e30e9f32dd upstream.

Fix dtbs-check warning pinctrl-names:0:'default' was expected
for r8a77470-iwg23s-sbc.dts file.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Rob Herring <robh@...>
Link: https://lore.kernel.org/r/20210817090313.31858-2-biju.das.jz@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 60 ++++++++++++-------
1 file changed, 37 insertions(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 21afaf9e7676..16050b29bc89 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -9,9 +9,6 @@ title: Renesas SDHI SD/MMC controller
maintainers:
- Wolfram Sang <wsa+renesas@...>

-allOf:
- - $ref: "mmc-controller.yaml"
-
properties:
compatible:
oneOf:
@@ -103,14 +100,46 @@ properties:
pinctrl-1:
maxItems: 1

- pinctrl-names:
- minItems: 1
- items:
- - const: default
- - const: state_uhs
+ pinctrl-names: true

max-frequency: true

+allOf:
+ - $ref: "mmc-controller.yaml"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,sdhi-mmc-r8a77470
+ then:
+ properties:
+ pinctrl-names:
+ items:
+ - const: state_uhs
+ else:
+ properties:
+ pinctrl-names:
+ minItems: 1
+ items:
+ - const: default
+ - const: state_uhs
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,sdhi-r7s72100
+ - renesas,sdhi-r7s9210
+ then:
+ required:
+ - clock-names
+ description:
+ The internal card detection logic that exists in these controllers is
+ sectioned off to be run by a separate second clock source to allow
+ the main core clock to be turned off to save power.
+
required:
- compatible
- reg
@@ -118,21 +147,6 @@ required:
- clocks
- power-domains

-if:
- properties:
- compatible:
- contains:
- enum:
- - renesas,sdhi-r7s72100
- - renesas,sdhi-r7s9210
-then:
- required:
- - clock-names
- description:
- The internal card detection logic that exists in these controllers is
- sectioned off to be run by a separate second clock source to allow
- the main core clock to be turned off to save power.
-
unevaluatedProperties: false

examples:
--
2.17.1


[RESEND PATCH 5.10.y-cip 33/40] dt-bindings: Drop redundant minItems/maxItems

Lad Prabhakar
 

From: Rob Herring <robh@...>

commit 972d6a7dcec3ad3226661034c5d8cb2d30585157 upstream.

If a property has an 'items' list, then a 'minItems' or 'maxItems' with the
same size as the list is redundant and can be dropped. Note that is DT
schema specific behavior and not standard json-schema behavior. The tooling
will fixup the final schema adding any unspecified minItems/maxItems.

This condition is partially checked with the meta-schema already, but
only if both 'minItems' and 'maxItems' are equal to the 'items' length.
An improved meta-schema is pending.

Cc: Jens Axboe <axboe@...>
Cc: Stephen Boyd <sboyd@...>
Cc: Herbert Xu <herbert@...>
Cc: "David S. Miller" <davem@...>
Cc: David Airlie <airlied@...>
Cc: Daniel Vetter <daniel@...>
Cc: Bartosz Golaszewski <bgolaszewski@...>
Cc: Kamal Dasu <kdasu.kdev@...>
Cc: Lars-Peter Clausen <lars@...>
Cc: Thomas Gleixner <tglx@...>
Cc: Marc Zyngier <maz@...>
Cc: Joerg Roedel <joro@...>
Cc: Mauro Carvalho Chehab <mchehab@...>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...>
Cc: Jakub Kicinski <kuba@...>
Cc: Wolfgang Grandegger <wg@...>
Cc: Andrew Lunn <andrew@...>
Cc: Vivien Didelot <vivien.didelot@...>
Cc: Vladimir Oltean <olteanv@...>
Cc: Bjorn Helgaas <bhelgaas@...>
Cc: Kishon Vijay Abraham I <kishon@...>
Cc: Linus Walleij <linus.walleij@...>
Cc: "Uwe Kleine-König" <u.kleine-koenig@...>
Cc: Lee Jones <lee.jones@...>
Cc: Ohad Ben-Cohen <ohad@...>
Cc: Mathieu Poirier <mathieu.poirier@...>
Cc: Paul Walmsley <paul.walmsley@...>
Cc: Palmer Dabbelt <palmer@...>
Cc: Albert Ou <aou@...>
Cc: Alessandro Zummo <a.zummo@...>
Cc: Alexandre Belloni <alexandre.belloni@...>
Cc: Zhang Rui <rui.zhang@...>
Cc: Daniel Lezcano <daniel.lezcano@...>
Cc: Wim Van Sebroeck <wim@...>
Cc: Guenter Roeck <linux@...>
Signed-off-by: Rob Herring <robh@...>
Acked-by: Marc Kleine-Budde <mkl@...>
Acked-by: Ulf Hansson <ulf.hansson@...> # for MMC
Acked-by: Jassi Brar <jassisinghbrar@...>
Acked-By: Vinod Koul <vkoul@...>
Reviewed-by: Greg Kroah-Hartman <gregkh@...>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@...>
Acked-by: Mark Brown <broonie@...>
Acked-by: Philipp Zabel <p.zabel@...>
Acked-by: Wolfram Sang <wsa@...> # for I2C
Acked-by: Jonathan Cameron <Jonathan.Cameron@...>
Link: https://lore.kernel.org/r/20210615191543.1043414-1-robh@kernel.org
[PL: Only applies changes to renesas,sdhi.yaml]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 2 --
1 file changed, 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 6c13703b31db..21afaf9e7676 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -74,7 +74,6 @@ properties:

clock-names:
minItems: 1
- maxItems: 2
items:
- const: core
- const: cd
@@ -106,7 +105,6 @@ properties:

pinctrl-names:
minItems: 1
- maxItems: 2
items:
- const: default
- const: state_uhs
--
2.17.1


[RESEND PATCH 5.10.y-cip 32/40] dt-bindings: Fix errors in 'if' schemas

Lad Prabhakar
 

From: Rob Herring <robh@...>

commit 9183908e70e913d2db052588172968da55d82af5 upstream.

Properties in if/then schemas weren't getting checked by the meta-schemas.
Enabling meta-schema checks finds several errors.

The use of an 'items' schema (as opposed to the list form) is wrong in
some cases as it applies to all entries. 'contains' is the correct schema
to use in the case of multiple entries.

Cc: Herbert Xu <herbert@...>
Cc: "David S. Miller" <davem@...>
Cc: Chen-Yu Tsai <wens@...>
Cc: Eric Anholt <eric@...>
Cc: Florian Fainelli <f.fainelli@...>
Cc: Ray Jui <rjui@...>
Cc: Scott Branden <sbranden@...>
Cc: Pavel Machek <pavel@...>
Cc: Ulf Hansson <ulf.hansson@...>
Cc: Kishon Vijay Abraham I <kishon@...>
Cc: Geert Uytterhoeven <geert+renesas@...>
Cc: Linus Walleij <linus.walleij@...>
Cc: Daniel Lezcano <daniel.lezcano@...>
Cc: linux-crypto@...
Cc: dri-devel@...
Cc: linux-leds@...
Cc: linux-mmc@...
Cc: linux-gpio@...
Acked-by: Maxime Ripard <mripard@...>
Acked-By: Vinod Koul <vkoul@...>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@...>
Acked-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Rob Herring <robh@...>
Link: https://lore.kernel.org/r/20210202205544.24812-3-robh@kernel.org
[PL: Only applied changes to renesas,sdhi.yaml]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 6bbf29b5c239..6c13703b31db 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -123,7 +123,7 @@ required:
if:
properties:
compatible:
- items:
+ contains:
enum:
- renesas,sdhi-r7s72100
- renesas,sdhi-r7s9210
--
2.17.1


[RESEND PATCH 5.10.y-cip 31/40] clk: renesas: r9a07g044: Add SDHI clock and reset entries

Lad Prabhakar
 

From: Biju Das <biju.das.jz@...>

commit 373bd6f487562e8727bc842e9983b093d57968cc upstream.

Add SDHI{0,1} mux, clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/clk/renesas/r9a07g044-cpg.c | 36 +++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.h | 4 ++++
2 files changed, 40 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 6c5204981dfb..463b658a0c54 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -44,6 +44,12 @@ enum clk_ids {
CLK_PLL6,
CLK_PLL6_250,
CLK_P1_DIV2,
+ CLK_PLL2_800,
+ CLK_PLL2_SDHI_533,
+ CLK_PLL2_SDHI_400,
+ CLK_PLL2_SDHI_266,
+ CLK_SD0_DIV4,
+ CLK_SD1_DIV4,

/* Module Clocks */
MOD_CLK_BASE,
@@ -62,6 +68,7 @@ static const struct clk_div_table dtable_1_32[] = {
/* Mux clock tables */
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
+static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };

static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
/* External Clock Inputs */
@@ -82,6 +89,11 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),

DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
+ DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
+ DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
+ DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
+ DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
+
DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),

@@ -114,6 +126,12 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
+ DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
+ sel_shdi, ARRAY_SIZE(sel_shdi)),
+ DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,
+ sel_shdi, ARRAY_SIZE(sel_shdi)),
+ DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
+ DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
};

static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
@@ -131,6 +149,22 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
0x550, 0),
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
0x550, 1),
+ DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
+ 0x554, 0),
+ DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
+ 0x554, 1),
+ DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
+ 0x554, 2),
+ DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
+ 0x554, 3),
+ DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
+ 0x554, 4),
+ DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
+ 0x554, 5),
+ DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
+ 0x554, 6),
+ DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
+ 0x554, 7),
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
0x570, 0),
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -202,6 +236,8 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
+ DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
+ DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index da41bd2a7e74..484c7cee2629 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -11,6 +11,7 @@

#define CPG_PL2_DDIV (0x204)
#define CPG_PL3A_DDIV (0x208)
+#define CPG_PL2SDHI_DSEL (0x218)
#define CPG_CLKSTATUS (0x280)
#define CPG_PL3_SSEL (0x408)
#define CPG_PL6_ETH_SSEL (0x418)
@@ -39,6 +40,9 @@
#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)

+#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
+#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
+
/**
* Definitions of CPG Core Clocks
*
--
2.17.1


[RESEND PATCH 5.10.y-cip 30/40] clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()

Lad Prabhakar
 

commit 33748744f15a110a233b6ae0380f476006e770f0 upstream.

of_genpd_add_provider_simple() might fail, this patch makes sure we check
the return value of of_genpd_add_provider_simple() by propagating the
return value to the caller of rzg2l_cpg_add_clk_domain().

Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211117115101.28281-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/clk/renesas/rzg2l-cpg.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 1b1555deb20b..edd0abe34a37 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -879,8 +879,7 @@ static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
if (ret)
return ret;

- of_genpd_add_provider_simple(np, genpd);
- return 0;
+ return of_genpd_add_provider_simple(np, genpd);
}

static int __init rzg2l_cpg_probe(struct platform_device *pdev)
--
2.17.1


[RESEND PATCH 5.10.y-cip 29/40] clk: renesas: rzg2l: Check return value of pm_genpd_init()

Lad Prabhakar
 

commit 27527a3d3b162e4512798c058c0e8a216c721187 upstream.

Make sure we check the return value of pm_genpd_init() which might fail.
Also add a devres action to remove the power-domain in-case the probe
callback fails further down in the code flow.

Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211117115101.28281-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/clk/renesas/rzg2l-cpg.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index a77cb47b75e7..1b1555deb20b 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -851,10 +851,16 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
pm_clk_destroy(dev);
}

+static void rzg2l_cpg_genpd_remove(void *data)
+{
+ pm_genpd_remove(data);
+}
+
static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
{
struct device_node *np = dev->of_node;
struct generic_pm_domain *genpd;
+ int ret;

genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
if (!genpd)
@@ -865,7 +871,13 @@ static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
GENPD_FLAG_ACTIVE_WAKEUP;
genpd->attach_dev = rzg2l_cpg_attach_dev;
genpd->detach_dev = rzg2l_cpg_detach_dev;
- pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+ ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
+ if (ret)
+ return ret;

of_genpd_add_provider_simple(np, genpd);
return 0;
--
2.17.1


[RESEND PATCH 5.10.y-cip 28/40] clk: renesas: rzg2l: Add missing kerneldoc for resets

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 099ee03271208c880aa33b8833edfacd5010a89a upstream.

make W=1:

drivers/clk/renesas/rzg2l-cpg.c:95: warning: Function parameter or member 'num_resets' not described in 'rzg2l_cpg_priv'

Add the missing kerneldoc for fields in struct rzg2l_cpg_priv and struct
rzg2l_cpg_info related to Module Resets.

Fixes: c3e67ad6f5a2c698 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Link: https://lore.kernel.org/r/39c2c5fd4232b6620a4a56dba4e2b0d61476ee36.1634646869.git.geert+renesas@glider.be
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/clk/renesas/rzg2l-cpg.c | 1 +
drivers/clk/renesas/rzg2l-cpg.h | 3 +++
2 files changed, 4 insertions(+)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 4021f6cabda4..a77cb47b75e7 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -74,6 +74,7 @@ struct sd_hw_data {
* @clks: Array containing all Core and Module Clocks
* @num_core_clks: Number of Core Clocks in clks[]
* @num_mod_clks: Number of Module Clocks in clks[]
+ * @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @notifiers: Notifier chain to save/restore clock state for system resume
* @info: Pointer to platform data
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 952fca98ba71..da41bd2a7e74 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -164,6 +164,9 @@ struct rzg2l_reset {
* @num_mod_clks: Number of entries in mod_clks[]
* @num_hw_mod_clks: Number of Module Clocks supported by the hardware
*
+ * @resets: Array of Module Reset definitions
+ * @num_resets: Number of entries in resets[]
+ *
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
--
2.17.1


[RESEND PATCH 5.10.y-cip 27/40] clk: renesas: rzg2l: Add SDHI clk mux support

Lad Prabhakar
 

From: Biju Das <biju.das.jz@...>

commit eaff33646f4cb6a541d01013b0a222f03f6dfac3 upstream.

Add SDHI clk mux support to select SDHI clock from different clock
sources.

As per HW manual, direct clock switching from 533MHz to 400MHz and
vice versa is not recommended. So added support for handling this
in mux.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211007111434.8665-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/clk/renesas/rzg2l-cpg.c | 118 ++++++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.h | 12 ++++
2 files changed, 130 insertions(+)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 1501547a11a3..4021f6cabda4 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -17,6 +17,7 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
+#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_address.h>
@@ -55,6 +56,14 @@
#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)

+struct sd_hw_data {
+ struct clk_hw hw;
+ u32 conf;
+ struct rzg2l_cpg_priv *priv;
+};
+
+#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw)
+
/**
* struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
*
@@ -150,6 +159,112 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
return clk_hw->clk;
}

+static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ return clk_mux_determine_rate_flags(hw, req, 0);
+}
+
+static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct sd_hw_data *hwdata = to_sd_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = hwdata->priv;
+ u32 off = GET_REG_OFFSET(hwdata->conf);
+ u32 shift = GET_SHIFT(hwdata->conf);
+ const u32 clk_src_266 = 2;
+ u32 bitmask;
+
+ /*
+ * As per the HW manual, we should not directly switch from 533 MHz to
+ * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz)
+ * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first,
+ * and then switch to the target setting (2’b01 (533 MHz) or 2’b10
+ * (400 MHz)).
+ * Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock
+ * switching register is prohibited.
+ * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and
+ * the index to value mapping is done by adding 1 to the index.
+ */
+ bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
+ if (index != clk_src_266) {
+ u32 msk, val;
+ int ret;
+
+ writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
+
+ msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
+
+ ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
+ !(val & msk), 100,
+ CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+ if (ret) {
+ dev_err(priv->dev, "failed to switch clk source\n");
+ return ret;
+ }
+ }
+
+ writel(bitmask | ((index + 1) << shift), priv->base + off);
+
+ return 0;
+}
+
+static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct sd_hw_data *hwdata = to_sd_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = hwdata->priv;
+ u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf));
+
+ val >>= GET_SHIFT(hwdata->conf);
+ val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);
+ if (val) {
+ val--;
+ } else {
+ /* Prohibited clk source, change it to 533 MHz(reset value) */
+ rzg2l_cpg_sd_clk_mux_set_parent(hw, 0);
+ }
+
+ return val;
+}
+
+static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {
+ .determine_rate = rzg2l_cpg_sd_clk_mux_determine_rate,
+ .set_parent = rzg2l_cpg_sd_clk_mux_set_parent,
+ .get_parent = rzg2l_cpg_sd_clk_mux_get_parent,
+};
+
+static struct clk * __init
+rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
+ void __iomem *base,
+ struct rzg2l_cpg_priv *priv)
+{
+ struct sd_hw_data *clk_hw_data;
+ struct clk_init_data init;
+ struct clk_hw *clk_hw;
+ int ret;
+
+ clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
+ if (!clk_hw_data)
+ return ERR_PTR(-ENOMEM);
+
+ clk_hw_data->priv = priv;
+ clk_hw_data->conf = core->conf;
+
+ init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";
+ init.ops = &rzg2l_cpg_sd_clk_mux_ops;
+ init.flags = 0;
+ init.num_parents = core->num_parents;
+ init.parent_names = core->parent_names;
+
+ clk_hw = &clk_hw_data->hw;
+ clk_hw->init = &init;
+
+ ret = devm_clk_hw_register(priv->dev, clk_hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return clk_hw->clk;
+}
+
struct pll_clk {
struct clk_hw hw;
unsigned int conf;
@@ -311,6 +426,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
case CLK_TYPE_MUX:
clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv);
break;
+ case CLK_TYPE_SD_MUX:
+ clk = rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv);
+ break;
default:
goto fail;
}
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index dc5b65a4029e..952fca98ba71 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -11,9 +11,15 @@

#define CPG_PL2_DDIV (0x204)
#define CPG_PL3A_DDIV (0x208)
+#define CPG_CLKSTATUS (0x280)
#define CPG_PL3_SSEL (0x408)
#define CPG_PL6_ETH_SSEL (0x418)

+#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
+#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
+
+#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000
+
/* n = 0/1/2 for PLL1/4/6 */
#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n))
#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n))
@@ -67,6 +73,9 @@ enum clk_types {

/* Clock with clock source selector */
CLK_TYPE_MUX,
+
+ /* Clock with SD clock source selector */
+ CLK_TYPE_SD_MUX,
};

#define DEF_TYPE(_name, _id, _type...) \
@@ -87,6 +96,9 @@ enum clk_types {
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents, \
.flag = _flag, .mux_flags = _mux_flags)
+#define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \
+ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
+ .parent_names = _parent_names, .num_parents = _num_parents)

/**
* struct rzg2l_mod_clk - Module Clocks definitions
--
2.17.1


[RESEND PATCH 5.10.y-cip 26/40] mmc: tmio: reinit card irqs in reset routine

Lad Prabhakar
 

From: Biju Das <biju.das.jz@...>

commit e315b1f3a170f368da5618f8a598e68880302ed1 upstream.

Refactor the code so that card detect irqs are always reenabled after a
reset. This avoids doing it manually all over the code or forgetting to
do this in the future.

Reported-by: Wolfram Sang <wsa+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
[wsa: added a comment when 'native_hotplug' has to be set]
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Link: https://lore.kernel.org/r/20211103122646.64422-1-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/mmc/host/tmio_mmc_core.c | 15 +++------------
1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 690094b0b6a8..79f237d754bd 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -958,14 +958,8 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
case MMC_POWER_OFF:
tmio_mmc_power_off(host);
/* For R-Car Gen2+, we need to reset SDHI specific SCC */
- if (host->pdata->flags & TMIO_MMC_MIN_RCAR2) {
- host->reset(host);
-
- if (host->native_hotplug)
- tmio_mmc_enable_mmc_irqs(host,
- TMIO_STAT_CARD_REMOVE |
- TMIO_STAT_CARD_INSERT);
- }
+ if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
+ tmio_mmc_reset(host);

host->set_clock(host, 0);
break;
@@ -1173,6 +1167,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
if (mmc_can_gpio_cd(mmc))
_host->ops.get_cd = mmc_gpio_get_cd;

+ /* must be set before tmio_mmc_reset() */
_host->native_hotplug = !(mmc_can_gpio_cd(mmc) ||
mmc->caps & MMC_CAP_NEEDS_POLL ||
!mmc_card_is_removable(mmc));
@@ -1302,10 +1297,6 @@ int tmio_mmc_host_runtime_resume(struct device *dev)
if (host->clk_cache)
host->set_clock(host, host->clk_cache);

- if (host->native_hotplug)
- tmio_mmc_enable_mmc_irqs(host,
- TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
-
tmio_mmc_enable_dma(host, true);

return 0;
--
2.17.1


[RESEND PATCH 5.10.y-cip 25/40] mmc: tmio: reenable card irqs after the reset callback

Lad Prabhakar
 

From: Wolfram Sang <wsa+renesas@...>

commit 90935eb303e0d12f3d3d0383262e65290321f5f6 upstream.

The reset callback may clear the internal card detect interrupts, so
make sure to reenable them if needed.

Fixes: b4d86f37eacb ("mmc: renesas_sdhi: do hard reset if possible")
Reported-by: Biju Das <biju.das.jz@...>
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Cc: stable@...
Link: https://lore.kernel.org/r/20211028195149.8003-1-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/mmc/host/tmio_mmc_core.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index bb5eb478b6cf..690094b0b6a8 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -195,6 +195,10 @@ static void tmio_mmc_reset(struct tmio_mmc_host *host)
sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all);
host->sdcard_irq_mask = host->sdcard_irq_mask_all;

+ if (host->native_hotplug)
+ tmio_mmc_enable_mmc_irqs(host,
+ TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
+
tmio_mmc_set_bus_width(host, host->mmc->ios.bus_width);

if (host->pdata->flags & TMIO_MMC_SDIO_IRQ) {
@@ -954,8 +958,15 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
case MMC_POWER_OFF:
tmio_mmc_power_off(host);
/* For R-Car Gen2+, we need to reset SDHI specific SCC */
- if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
+ if (host->pdata->flags & TMIO_MMC_MIN_RCAR2) {
host->reset(host);
+
+ if (host->native_hotplug)
+ tmio_mmc_enable_mmc_irqs(host,
+ TMIO_STAT_CARD_REMOVE |
+ TMIO_STAT_CARD_INSERT);
+ }
+
host->set_clock(host, 0);
break;
case MMC_POWER_UP:
@@ -1192,10 +1203,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
_host->set_clock(_host, 0);
tmio_mmc_reset(_host);

- if (_host->native_hotplug)
- tmio_mmc_enable_mmc_irqs(_host,
- TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
-
spin_lock_init(&_host->lock);
mutex_init(&_host->ios_lock);

--
2.17.1


[RESEND PATCH 5.10.y-cip 24/40] mmc: tmio: always restore irq register

Lad Prabhakar
 

From: Wolfram Sang <wsa+renesas@...>

commit 0751d56ef1f25c4206626dff99445db34dedf437 upstream.

Currently, only SDHI on R-Car Gen2+ reinitializes the irq register
during reset but it should be done on all instances. We can move it from
the SDHI driver to the TMIO core, because we now have the
'sd_irq_mask_all' variable which carries the proper value to use. That
also means we can remove the initialization from tmio_mmc_probe()
because it calls tmio_mmc_reset(), too. We only move that
tmio_mmc_reset() call there a little to ensure 'sd_irq_mask_all' is
properly set.

Signed-off-by: Wolfram Sang <wsa+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Link: https://lore.kernel.org/r/20210413083137.11171-1-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/mmc/host/renesas_sdhi_core.c | 2 --
drivers/mmc/host/tmio_mmc_core.c | 11 ++++++-----
2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 1783a0a6ee56..8a9d74474768 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -588,8 +588,6 @@ static void renesas_sdhi_reset(struct tmio_mmc_host *host)
renesas_sdhi_scc_reset(host, priv);
}

- sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_ALL_RCAR2);
-
if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
val |= CARD_OPT_EXTOP;
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 59372de733b2..bb5eb478b6cf 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -192,6 +192,9 @@ static void tmio_mmc_reset(struct tmio_mmc_host *host)
if (host->reset)
host->reset(host);

+ sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all);
+ host->sdcard_irq_mask = host->sdcard_irq_mask_all;
+
tmio_mmc_set_bus_width(host, host->mmc->ios.bus_width);

if (host->pdata->flags & TMIO_MMC_SDIO_IRQ) {
@@ -1183,13 +1186,11 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
if (pdata->flags & TMIO_MMC_SDIO_IRQ)
_host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;

- _host->set_clock(_host, 0);
- tmio_mmc_reset(_host);
-
- _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
if (!_host->sdcard_irq_mask_all)
_host->sdcard_irq_mask_all = TMIO_MASK_ALL;
- tmio_mmc_disable_mmc_irqs(_host, _host->sdcard_irq_mask_all);
+
+ _host->set_clock(_host, 0);
+ tmio_mmc_reset(_host);

if (_host->native_hotplug)
tmio_mmc_enable_mmc_irqs(_host,
--
2.17.1


[RESEND PATCH 5.10.y-cip 23/40] mmc: tmio: always flag retune when resetting and a card is present

Lad Prabhakar
 

From: Wolfram Sang <wsa+renesas@...>

commit 6e5c951b4c3a0bd9aa5838ecec98f3c795c83ff1 upstream.

After reset, we manually flagged retune in runtime resume, but missed it
in the workqueue. To fix that and avoid the problem in the future, let's
flag retune in the reset handler directly whenever a card is present.

Reported-by: Takeshi Saito <takeshi.saito.xv@...>
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Link: https://lore.kernel.org/r/20210316085717.7276-3-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/mmc/host/tmio_mmc_core.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index ee9dc175e444..59372de733b2 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -198,6 +198,9 @@ static void tmio_mmc_reset(struct tmio_mmc_host *host)
sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
}
+
+ if (host->mmc->card)
+ mmc_retune_needed(host->mmc);
}

static void tmio_mmc_reset_work(struct work_struct *work)
@@ -1297,8 +1300,6 @@ int tmio_mmc_host_runtime_resume(struct device *dev)

tmio_mmc_enable_dma(host, true);

- mmc_retune_needed(host->mmc);
-
return 0;
}
EXPORT_SYMBOL_GPL(tmio_mmc_host_runtime_resume);
--
2.17.1


[RESEND PATCH 5.10.y-cip 22/40] mmc: renesas_sdhi: do hard reset if possible

Lad Prabhakar
 

From: Wolfram Sang <wsa+renesas@...>

commit b4d86f37eacb724690d0d300576b82806bc743d5 upstream.

All recent SDHI instances can be reset via the reset controller. If one
is found, use it instead of the open coded reset. This is to get a
future-proof sane reset state.

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Link: https://lore.kernel.org/r/20210317091622.31890-4-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/renesas_sdhi.h | 2 ++
drivers/mmc/host/renesas_sdhi_core.c | 17 ++++++++++++++++-
3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 30ff42fd173e..3538f9e9bce9 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -711,6 +711,7 @@ config MMC_SDHI
tristate "Renesas SDHI SD/SDIO controller support"
depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
select MMC_TMIO_CORE
+ select RESET_CONTROLLER if ARCH_RENESAS
help
This provides support for the SDHI SD/SDIO controller found in
Renesas SuperH, ARM and ARM64 based SoCs
diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
index cb962c7883dc..53eded81a53e 100644
--- a/drivers/mmc/host/renesas_sdhi.h
+++ b/drivers/mmc/host/renesas_sdhi.h
@@ -70,6 +70,8 @@ struct renesas_sdhi {
DECLARE_BITMAP(smpcmp, BITS_PER_LONG);
unsigned int tap_num;
unsigned int tap_set;
+
+ struct reset_control *rstc;
};

#define host_to_priv(host) \
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index eaf6071ab3cc..1783a0a6ee56 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -20,6 +20,7 @@

#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
@@ -32,6 +33,7 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
#include <linux/sh_dma.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
@@ -572,10 +574,19 @@ static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sd
static void renesas_sdhi_reset(struct tmio_mmc_host *host)
{
struct renesas_sdhi *priv = host_to_priv(host);
+ int ret;
u16 val;

- if (priv->scc_ctl)
+ if (priv->rstc) {
+ reset_control_reset(priv->rstc);
+ /* Unknown why but without polling reset status, it will hang */
+ read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
+ false, priv->rstc);
+ priv->needs_adjust_hs400 = false;
+ renesas_sdhi_set_clock(host, host->clk_cache);
+ } else if (priv->scc_ctl) {
renesas_sdhi_scc_reset(host, priv);
+ }

sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_ALL_RCAR2);

@@ -1086,6 +1097,10 @@ int renesas_sdhi_probe(struct platform_device *pdev,
if (ret)
goto efree;

+ priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(priv->rstc))
+ return PTR_ERR(priv->rstc);
+
ver = sd_ctrl_read16(host, CTL_VERSION);
/* GEN2_SDR104 is first known SDHI to use 32bit block count */
if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
--
2.17.1


[RESEND PATCH 5.10.y-cip 21/40] mmc: renesas_sdhi: break SCC reset into own function

Lad Prabhakar
 

From: Wolfram Sang <wsa+renesas@...>

commit 0e5870145840e91fc33cd4eca6e228b009d86705 upstream.

renesas_sdhi_reset used to mainly reset the SCC but is now doing more
and even more will be added. So, factor out SCC reset to have a clear
distinction when we want to reset either SCC or SDHI+SCC.

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Link: https://lore.kernel.org/r/20210317091622.31890-3-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/mmc/host/renesas_sdhi_core.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index bee27e2fe446..eaf6071ab3cc 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -557,21 +557,25 @@ static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_io
return 0;
}

+static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
+{
+ renesas_sdhi_disable_scc(host->mmc);
+ renesas_sdhi_reset_hs400_mode(host, priv);
+ priv->needs_adjust_hs400 = false;
+
+ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
+ ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
+ sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
+}
+
/* only populated for TMIO_MMC_MIN_RCAR2 */
static void renesas_sdhi_reset(struct tmio_mmc_host *host)
{
struct renesas_sdhi *priv = host_to_priv(host);
u16 val;

- if (priv->scc_ctl) {
- renesas_sdhi_disable_scc(host->mmc);
- renesas_sdhi_reset_hs400_mode(host, priv);
- priv->needs_adjust_hs400 = false;
-
- sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
- ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
- sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
- }
+ if (priv->scc_ctl)
+ renesas_sdhi_scc_reset(host, priv);

sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_ALL_RCAR2);

@@ -696,7 +700,7 @@ static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)

ret = renesas_sdhi_select_tuning(host);
if (ret < 0)
- renesas_sdhi_reset(host);
+ renesas_sdhi_scc_reset(host, priv);
return ret;
}

--
2.17.1


[RESEND PATCH 5.10.y-cip 20/40] mmc: tmio: restore bus width when resetting

Lad Prabhakar
 

From: Takeshi Saito <takeshi.saito.xv@...>

commit 0a446288aa9f28ab00a31b8b51fdb005953f9f99 upstream.

Resetting the IP core will lose the bus width information and not all
code paths recover it. So, make sure the latest bus width gets restored
in the reset routine. For that, tmio_mmc_set_bus_width() is moved, but
not modified.

Signed-off-by: Takeshi Saito <takeshi.saito.xv@...>
[wsa: reworded commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Link: https://lore.kernel.org/r/20210316085717.7276-2-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/mmc/host/tmio_mmc_core.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 0c752b4348de..ee9dc175e444 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -164,6 +164,21 @@ static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
}
}

+static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
+ unsigned char bus_width)
+{
+ u16 reg = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT)
+ & ~(CARD_OPT_WIDTH | CARD_OPT_WIDTH8);
+
+ /* reg now applies to MMC_BUS_WIDTH_4 */
+ if (bus_width == MMC_BUS_WIDTH_1)
+ reg |= CARD_OPT_WIDTH;
+ else if (bus_width == MMC_BUS_WIDTH_8)
+ reg |= CARD_OPT_WIDTH8;
+
+ sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, reg);
+}
+
static void tmio_mmc_reset(struct tmio_mmc_host *host)
{
/* FIXME - should we set stop clock reg here */
@@ -177,6 +192,8 @@ static void tmio_mmc_reset(struct tmio_mmc_host *host)
if (host->reset)
host->reset(host);

+ tmio_mmc_set_bus_width(host, host->mmc->ios.bus_width);
+
if (host->pdata->flags & TMIO_MMC_SDIO_IRQ) {
sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
@@ -872,21 +889,6 @@ static void tmio_mmc_power_off(struct tmio_mmc_host *host)
host->set_pwr(host->pdev, 0);
}

-static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
- unsigned char bus_width)
-{
- u16 reg = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT)
- & ~(CARD_OPT_WIDTH | CARD_OPT_WIDTH8);
-
- /* reg now applies to MMC_BUS_WIDTH_4 */
- if (bus_width == MMC_BUS_WIDTH_1)
- reg |= CARD_OPT_WIDTH;
- else if (bus_width == MMC_BUS_WIDTH_8)
- reg |= CARD_OPT_WIDTH8;
-
- sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, reg);
-}
-
static unsigned int tmio_mmc_get_timeout_cycles(struct tmio_mmc_host *host)
{
u16 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
--
2.17.1


[RESEND PATCH 5.10.y-cip 19/40] mmc: tmio: abort DMA before reset

Lad Prabhakar
 

From: Wolfram Sang <wsa+renesas@...>

commit ab0cdefec052825303c05687d9416bafc867fe3d upstream.

We will soon allow resetting the whole IP core via a reset controller.
For this case, DMA must be terminated before the actual reset. For the
other cases, it is probably better, too.

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...>
Signed-off-by: Wolfram Sang <wsa+renesas@...>
Link: https://lore.kernel.org/r/20210317091622.31890-2-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/mmc/host/tmio_mmc_core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 48083acdb077..0c752b4348de 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -172,11 +172,11 @@ static void tmio_mmc_reset(struct tmio_mmc_host *host)
sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
usleep_range(10000, 11000);

+ tmio_mmc_abort_dma(host);
+
if (host->reset)
host->reset(host);

- tmio_mmc_abort_dma(host);
-
if (host->pdata->flags & TMIO_MMC_SDIO_IRQ) {
sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
--
2.17.1

1321 - 1340 of 9267