Date   

Re: cip-kernel-sec Updates for Last Week of October

Pavel Machek
 

Hi!

- Fix for CVE-2020-27673 has not been backported yet.
Some kind of Xen issue, not really relevant to us, and fix is not
easy.

I'd say we can ignore this one.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Pavel Machek
 

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.

Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also
lspci output)
Thank you!

Best regards,

Pavel


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support

Pavel Machek
 

Hi!

This patch series adds PCIe{EP}/SATA support to Renesas RZ/G2H.

All the patches have been cherry-picked from mainline kernel
v5.10-rc2.
Looks good and passes our tests. I can apply it if there are no other
comments.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


[PATCH 4.19.y-cip 6/6] arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata

Lad Prabhakar
 

commit 7345e5c1853d7173bf06923c29f93c0308ac89e5 upstream.

Enable sata interface on HiHope RZ/G2H board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200907073214.13929-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
index 265355e0de5f..812995939841 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
@@ -13,3 +13,8 @@
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
"renesas,r8a774e1";
};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+&sata {
+ status = "okay";
+};
--
2.17.1


[PATCH 4.19.y-cip 5/6] misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller

Lad Prabhakar
 

commit a63c5f3db07dab2b205ac9a6a6ca96c4f72290de upstream.

Add Renesas R8A774E1 in pci_device_id table so that pci-epf-test
can be used for testing PCIe EP on RZ/G2H.

Link: https://lore.kernel.org/r/20200904103851.3946-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index a1083f568d2c..9413a08ee351 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -83,6 +83,7 @@
#define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
+#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025

static DEFINE_IDA(pci_endpoint_test_ida);

@@ -821,6 +822,7 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
--
2.17.1


[PATCH 4.19.y-cip 4/6] arm64: dts: renesas: r8a774e1: Add PCIe EP nodes

Lad Prabhakar
 

commit b7ecb51b2d9bd12c80c24d2fd1cadedd35e7cb7e upstream.

Add PCIe EP nodes for R8A774E1 Soc dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200904103851.3946-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 832abe712e6c..8e9292d46cc4 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1582,6 +1582,44 @@
status = "disabled";
};

+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774e1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774e1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
hdmi0: hdmi@fead0000 {
reg = <0 0xfead0000 0 0x10000>;
status = "disabled";
--
2.17.1


[PATCH 4.19.y-cip 3/6] dt-bindings: pci: rcar-pci-ep: Document r8a774e1

Lad Prabhakar
 

commit 5e94083c781445b4b5c00689167558dce694da65 upstream.

Document the support for R-Car PCIe EP on R8A774E1 SoC device.

Link: https://lore.kernel.org/r/20200904103851.3946-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
index 70c45f72ab20..a059c96c294b 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
@@ -18,6 +18,7 @@ properties:
- renesas,r8a774a1-pcie-ep # RZ/G2M
- renesas,r8a774b1-pcie-ep # RZ/G2N
- renesas,r8a774c0-pcie-ep # RZ/G2E
+ - renesas,r8a774e1-pcie-ep # RZ/G2H
- const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2

reg:
--
2.17.1


[PATCH 4.19.y-cip 2/6] arm64: dts: renesas: r8a774e1: Add SATA controller node

Lad Prabhakar
 

commit 2f3c7323aba207b5cf1e769b8f48ce726531de4a upstream.

Add the SATA controller node to the RZ/G2H SoC specific dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594919915-5225-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index aaa55f9449f5..832abe712e6c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1499,6 +1499,18 @@
status = "disabled";
};

+ sata: sata@ee300000 {
+ compatible = "renesas,sata-r8a774e1",
+ "renesas,rcar-gen3-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ iommus = <&ipmmu_hc 2>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1


[PATCH 4.19.y-cip 1/6] arm64: dts: renesas: r8a774e1: Add PCIe device nodes

Lad Prabhakar
 

commit cbb2f09abcd635888508338d4436771fe07688d1 upstream.

Add PCIe{0,1} device nodes for R8A774E1 SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594919915-5225-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 47 ++++++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 0f86cfd52425..aaa55f9449f5 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1517,12 +1517,57 @@
};

pciec0: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a774e1",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
status = "disabled";
+ };

- /* placeholder */
+ pciec1: pcie@ee800000 {
+ compatible = "renesas,pcie-r8a774e1",
+ "renesas,pcie-rcar-gen3";
+ reg = <0 0xee800000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
+ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
+ <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
+ <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
};

hdmi0: hdmi@fead0000 {
--
2.17.1


[PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support

Lad Prabhakar
 

Hi All,

This patch series adds PCIe{EP}/SATA support to Renesas RZ/G2H.

All the patches have been cherry-picked from mainline kernel
v5.10-rc2.

Cheers,
Prabhakar

Lad Prabhakar (6):
arm64: dts: renesas: r8a774e1: Add PCIe device nodes
arm64: dts: renesas: r8a774e1: Add SATA controller node
dt-bindings: pci: rcar-pci-ep: Document r8a774e1
arm64: dts: renesas: r8a774e1: Add PCIe EP nodes
misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller
arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata

.../devicetree/bindings/pci/rcar-pci-ep.yaml | 1 +
.../dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 5 +
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 97 ++++++++++++++++++-
drivers/misc/pci_endpoint_test.c | 2 +
4 files changed, 104 insertions(+), 1 deletion(-)

--
2.17.1


[ANNOUNCE] v4.19.152-cip37-rt16

Pavel Machek
 

Hi!

New realtime trees should be available at kernel.org.

I'm doing release at unusual time because the last one had problems
booting on Renesas boards. This one should work ok.

Trees are available at

https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/log/?h=linux-4.19.y-cip-rt
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/log/?h=linux-4.19.y-cip-rt-rebase

And their content should be identical.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Lad Prabhakar
 

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 30 October 2020 10:26
To: Pavel Machek <pavel@denx.de>
Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu
<nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Hi!

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.
Series looks okay to me, it is currently being tested. I can
apply/push it if there are no other comments.
Thanks for patches, I pushed out the series.
Thank you.

Cheers,
Prabhakar


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Lad Prabhakar
 

Hi Nobuhiro,

-----Original Message-----
From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
Sent: 30 October 2020 10:58
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; pavel@denx.de
Cc: cip-dev@lists.cip-project.org; Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi Prabhakar,

-----Original Message-----
From: Prabhakar Mahadev Lad [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Thursday, October 29, 2020 12:36 AM
To: Pavel Machek <pavel@denx.de>
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 28 October 2020 15:27
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
<pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fcip-
dev%2F&amp;data=04%7C01%7Cprabhakar.mahadev-
lad.rj%40bp.renesas.com%7C55e2a70e90c54aed478908d87cc2ab6c%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637396522
837081719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;
sdata=P4d9zKypm%2B0kGpmD32bPiC2W6SXLX5Fp%2Fm99bwzb6Y8%3D&amp;reserved=0
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled
as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.
OK.


Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also lspci output)
Thank you for attaching the test results.
I will apply and push this series.
Thank you.

Cheers,
Prabhakar


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Nobuhiro Iwamatsu
 

Hi Prabhakar,

-----Original Message-----
From: Prabhakar Mahadev Lad [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Thursday, October 29, 2020 12:36 AM
To: Pavel Machek <pavel@denx.de>
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 28 October 2020 15:27
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
<pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled
as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.
OK.


Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also lspci output)
Thank you for attaching the test results.
I will apply and push this series.


Cheers,
Prabhakar
Best regards,
Nobuhiro


Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Pavel Machek
 

Hi!

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.
Series looks okay to me, it is currently being tested. I can
apply/push it if there are no other comments.
Thanks for patches, I pushed out the series.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Pavel Machek
 

Hi!

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.
Series looks okay to me, it is currently being tested. I can
apply/push it if there are no other comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Lad Prabhakar
 

Hi,

-----Original Message-----
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Lad Prabhakar via lists.cip-project.org
Sent: 29 October 2020 11:46
To: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [cip-dev] [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Hi All,

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.
Missed to mention all the patches have been cherry picked from v5.10-rc1.

Cheers,
Prabhakar


Fabrizio Castro (2):
dt-bindings: ata: sata_rcar: Add r8a774b1 support
arm64: dts: renesas: r8a774b1: Add SATA controller node

Geert Uytterhoeven (1):
ata: sata_rcar: Fix DMA boundary mask

Lad Prabhakar (1):
arm64: dts: renesas: r8a774b1-hihope-rzg2n-ex: Enable sata

Documentation/devicetree/bindings/ata/sata_rcar.txt | 7 +++++--
.../boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 11 +++++++++++
drivers/ata/sata_rcar.c | 2 +-
4 files changed, 22 insertions(+), 3 deletions(-)

--
2.17.1


[PATCH 4.19.y-cip 4/4] ata: sata_rcar: Fix DMA boundary mask

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit df9c590986fdb6db9d5636d6cd93bc919c01b451 upstream.

Before commit 9495b7e92f716ab2 ("driver core: platform: Initialize
dma_parms for platform devices"), the R-Car SATA device didn't have DMA
parameters. Hence the DMA boundary mask supplied by its driver was
silently ignored, as __scsi_init_queue() doesn't check the return value
of dma_set_seg_boundary(), and the default value of 0xffffffff was used.

Now the device has gained DMA parameters, the driver-supplied value is
used, and the following warning is printed on Salvator-XS:

DMA-API: sata_rcar ee300000.sata: mapping sg segment across boundary [start=0x00000000ffffe000] [end=0x00000000ffffefff] [boundary=0x000000001ffffffe]
WARNING: CPU: 5 PID: 38 at kernel/dma/debug.c:1233 debug_dma_map_sg+0x298/0x300

(the range of start/end values depend on whether IOMMU support is
enabled or not)

The issue here is that SATA_RCAR_DMA_BOUNDARY doesn't have bit 0 set, so
any typical end value, which is odd, will trigger the check.

Fix this by increasing the DMA boundary value by 1.

This also fixes the following WRITE DMA EXT timeout issue:

# dd if=/dev/urandom of=/mnt/de1/file1-1024M bs=1M count=1024
ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
ata1.00: failed command: WRITE DMA EXT
ata1.00: cmd 35/00:00:00:e6:0c/00:0a:00:00:00/e0 tag 0 dma 1310720 out
res 40/00:01:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
ata1.00: status: { DRDY }

as seen by Shimoda-san since commit 429120f3df2dba2b ("block: fix
splitting segments on boundary masks").

Fixes: 8bfbeed58665dbbf ("sata_rcar: correct 'sata_rcar_sht'")
Fixes: 9495b7e92f716ab2 ("driver core: platform: Initialize dma_parms for platform devices")
Fixes: 429120f3df2dba2b ("block: fix splitting segments on boundary masks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/ata/sata_rcar.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 8323f88d17a5..4dcdf8ee0055 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -124,7 +124,7 @@
/* Descriptor table word 0 bit (when DTA32M = 1) */
#define SATA_RCAR_DTEND BIT(0)

-#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
+#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL

/* Gen2 Physical Layer Control Registers */
#define RCAR_GEN2_PHY_CTL1_REG 0x1704
--
2.17.1


[PATCH 4.19.y-cip 3/4] arm64: dts: renesas: r8a774b1-hihope-rzg2n-ex: Enable sata

Lad Prabhakar
 

commit e7cc614be7886b464a429f83162171128c205b2e upstream.

Enable sata interface on HiHope RZ/G2N board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200810171239.30401-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
index a3edd55113df..60d7c8adea02 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
@@ -14,3 +14,8 @@
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
"renesas,r8a774b1";
};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+&sata {
+ status = "okay";
+};
--
2.17.1


[PATCH 4.19.y-cip 2/4] arm64: dts: renesas: r8a774b1: Add SATA controller node

Lad Prabhakar
 

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit 1510faee309010194ebb6ad3068cc9c0f7bc761b upstream.

Add the SATA controller node to the RZ/G2N SoC specific
dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1571761279-17347-3-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 62d011107cc5..11cc0f274ef3 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1902,6 +1902,17 @@
status = "disabled";
};

+ sata: sata@ee300000 {
+ compatible = "renesas,sata-r8a774b1",
+ "renesas,rcar-gen3-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1

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