Date   

[PATCH 4.19.y-cip 1/4] dt-bindings: ata: sata_rcar: Add r8a774b1 support

Lad Prabhakar
 

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit b00e14c536574fb3e45aa0cf899e67fc3ac51d06 upstream.

Document SATA support for the RZ/G2N, no driver change required.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/ata/sata_rcar.txt | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt
index 4268e17d2411..a2fbdc91570d 100644
--- a/Documentation/devicetree/bindings/ata/sata_rcar.txt
+++ b/Documentation/devicetree/bindings/ata/sata_rcar.txt
@@ -2,6 +2,7 @@

Required properties:
- compatible : should contain one or more of the following:
+ - "renesas,sata-r8a774b1" for RZ/G2N
- "renesas,sata-r8a7779" for R-Car H1
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
@@ -9,8 +10,10 @@ Required properties:
- "renesas,sata-r8a7793" for R-Car M2-N
- "renesas,sata-r8a7795" for R-Car H3
- "renesas,sata-r8a77965" for R-Car M3-N
- - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
- - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
+ - "renesas,rcar-gen2-sata" for a generic R-Car Gen2
+ compatible device
+ - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or
+ RZ/G2 compatible device
- "renesas,rcar-sata" is deprecated

When compatible with the generic version nodes
--
2.17.1


[PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Lad Prabhakar
 

Hi All,

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.

Cheers,
Prabhakar

Fabrizio Castro (2):
dt-bindings: ata: sata_rcar: Add r8a774b1 support
arm64: dts: renesas: r8a774b1: Add SATA controller node

Geert Uytterhoeven (1):
ata: sata_rcar: Fix DMA boundary mask

Lad Prabhakar (1):
arm64: dts: renesas: r8a774b1-hihope-rzg2n-ex: Enable sata

Documentation/devicetree/bindings/ata/sata_rcar.txt | 7 +++++--
.../boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 11 +++++++++++
drivers/ata/sata_rcar.c | 2 +-
4 files changed, 22 insertions(+), 3 deletions(-)

--
2.17.1


Re: cip-kernel-sec Updates for Last Week of October

masashi.kudo@cybertrust.co.jp <masashi.kudo@...>
 

Hi, Chen-Yu san,

Thanks for your report! This is very helpful.

Could you add the backporting status for 4.4 and 4.19 stable kernels?
We may want to discuss the necessity of the backporting for them.

Best regards,
--
M. Kudo

-----Original Message-----
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of
Chen-Yu Tsai (Moxa)
Sent: Thursday, October 29, 2020 11:42 AM
To: cip-dev@lists.cip-project.org
Cc: Pavel Machek <pavel@denx.de>; Nobuhiro Iwamatsu
<nobuhiro1.iwamatsu@toshiba.co.jp>
Subject: [cip-dev] cip-kernel-sec Updates for Last Week of October

Hi everyone,

Since there's no CIP weekly meeting this week, I'm sharing the details on the
mailing list. If people prefer this format, I can also do this in the future. This could
make up for the merge request which summarized the information.

Here's this week's update:

New CVEs:
- CVE-2019-0146 [net/i40e] - likely fixed
- CVE-2020-27673 [xen/dom0] - fixed in mainline
- CVE-2020-27675 [xen/dom0] - fixed in mainline

Old CVEs now fixed:
- CVE-2020-14351 [perf] - fixed in mainline
- CVE-2020-27152 [KVM] - fixed in mainline

So we have yet another Intel i40e CVE that has a nearly useless description.

For the rest, they are all fixed in v5.10-rc1.

- Fixes for CVE-2020-14351 and CVE-2020-27152 have been queued
up for v5.8 and v5.9.

- Fix for CVE-2020-27675 has been queued up for v5.9

- Fix for CVE-2020-27673 has not been backported yet.


Regards
ChenYu
Moxa


cip-kernel-sec Updates for Last Week of October

Chen-Yu Tsai (Moxa) <wens@...>
 

Hi everyone,

Since there's no CIP weekly meeting this week, I'm sharing the details
on the mailing list. If people prefer this format, I can also do this
in the future. This could make up for the merge request which summarized
the information.

Here's this week's update:

New CVEs:
- CVE-2019-0146 [net/i40e] - likely fixed
- CVE-2020-27673 [xen/dom0] - fixed in mainline
- CVE-2020-27675 [xen/dom0] - fixed in mainline

Old CVEs now fixed:
- CVE-2020-14351 [perf] - fixed in mainline
- CVE-2020-27152 [KVM] - fixed in mainline

So we have yet another Intel i40e CVE that has a nearly useless
description.

For the rest, they are all fixed in v5.10-rc1.

- Fixes for CVE-2020-14351 and CVE-2020-27152 have been queued
up for v5.8 and v5.9.

- Fix for CVE-2020-27675 has been queued up for v5.9

- Fix for CVE-2020-27673 has not been backported yet.


Regards
ChenYu
Moxa


No IRC meeting today

masashi.kudo@cybertrust.co.jp <masashi.kudo@...>
 

Hi,

It is just a reminder.
As we discussed at the IRC meeting last week, there is no IRC meeting this week.

See you next week,
--
M. Kudo


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Lad Prabhakar
 

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 28 October 2020 15:27
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.

Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also lspci output)

Cheers,
Prabhakar

Best regards,
Pavel


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Pavel Machek
 

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.

Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).

Best regards,
Pavel


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Leaving Codethink and CIP

Ben Hutchings <ben.hutchings@...>
 

I will be leaving Codethink next month, and will no longer be working
directly on CIP. (With my Debian hat on, I may still submit merge
requests to the cip-kernel-sec repository.) My last working day here
will be 11 November.

I want to thank everyone who's worked to make super-long-term Linux
kernel maintenance possible. CIP has a great kernel team now and I'm
confident that you'll carry on doing a fine job without me.

Ben.

--
Ben Hutchings, Software Developer Codethink Ltd
https://www.codethink.co.uk/ Dale House, 35 Dale Street
Manchester, M1 2HF, United Kingdom


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Nobuhiro Iwamatsu
 

Hi,

Thanks for your work.

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Wednesday, October 28, 2020 1:56 AM
To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi All,

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both

Cheers,
Prabhakar

Lad Prabhakar (5):
dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
arm64: dts: renesas: r8a774c0: Add PCIe EP node
arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
controllers
I have reviewed this patch series. There seems to be no problem.
I will apply this if there is no other opinion.

Best regards,
Nobuhiro


.../devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++-
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
drivers/misc/pci_endpoint_test.c | 7 +++-
5 files changed, 105 insertions(+), 4 deletions(-)

--
2.17.1


[PATCH 4.19.y-cip 5/5] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers

Lad Prabhakar
 

commit cfb824ddd1c040a7ac65eea3f900f14268e8f383 upstream.

Add Renesas R8A774A1 and R8A774B1 in pci_device_id table so that
pci-epf-test can be used for testing PCIe EP on RZ/G2M and RZ/G2N.

Link: https://lore.kernel.org/r/20200814173037.17822-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/misc/pci_endpoint_test.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index aff8cbca5d18..a1083f568d2c 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -80,6 +80,8 @@
#define is_am654_pci_dev(pdev) \
((pdev)->device == PCI_DEVICE_ID_TI_AM654)

+#define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
+#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d

static DEFINE_IDA(pci_endpoint_test_ida);
@@ -816,8 +818,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
.driver_data = (kernel_ulong_t)&am654_data
},
- { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
- },
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
--
2.17.1


[PATCH 4.19.y-cip 4/5] arm64: dts: renesas: r8a774b1: Add PCIe EP nodes

Lad Prabhakar
 

commit d12d16205f7993da195002eea24b7467deb9ac8c upstream.

Add PCIe EP nodes to R8A774B1 (RZ/G2N) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 11cc0f274ef3..0e5bfaeda983 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1984,6 +1984,44 @@
status = "disabled";
};

+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774b1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774b1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
--
2.17.1


[PATCH 4.19.y-cip 3/5] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes

Lad Prabhakar
 

commit 578450883bb1ff878ac8e3d38060802b222adcbe upstream.

Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 16166f3b66a0..90f5fb49957e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2115,6 +2115,44 @@
status = "disabled";
};

+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774a1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774a1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
--
2.17.1


[PATCH 4.19.y-cip 2/5] arm64: dts: renesas: r8a774c0: Add PCIe EP node

Lad Prabhakar
 

commit 0c77ecdcfcd35e97c677e49a8516a0b10c1e8fb7 upstream.

Add PCIe EP node to R8A774C0 (RZ/G2E) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 7ba934c32696..44d66fcb412d 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1698,6 +1698,25 @@
status = "disabled";
};

+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774c0-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
vspb0: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
--
2.17.1


[PATCH 4.19.y-cip 1/5] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1

Lad Prabhakar
 

commit 2de82ec8667465236e15f8c6af7cecf8da63fc60 upstream.

Document the support for R-Car PCIe EP on R8A774A1 and R8A774B1 SoC
devices.

Also constify "renesas,rcar-gen3-pcie-ep" so that it can be used as
fallback compatible string for R-Car Gen3 and RZ/G2 devices as the
PCIe module is identical.

Link: https://lore.kernel.org/r/20200814173037.17822-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
index aa483c7f27fd..70c45f72ab20 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
@@ -14,8 +14,11 @@ maintainers:
properties:
compatible:
items:
- - const: renesas,r8a774c0-pcie-ep
- - const: renesas,rcar-gen3-pcie-ep
+ - enum:
+ - renesas,r8a774a1-pcie-ep # RZ/G2M
+ - renesas,r8a774b1-pcie-ep # RZ/G2N
+ - renesas,r8a774c0-pcie-ep # RZ/G2E
+ - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2

reg:
maxItems: 5
--
2.17.1


[PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Lad Prabhakar
 

Hi All,

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both

Cheers,
Prabhakar

Lad Prabhakar (5):
dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
arm64: dts: renesas: r8a774c0: Add PCIe EP node
arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
controllers

.../devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++-
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
drivers/misc/pci_endpoint_test.c | 7 +++-
5 files changed, 105 insertions(+), 4 deletions(-)

--
2.17.1


Re: Direct Pushes for cip-kernel-sec

Ben Hutchings <ben.hutchings@...>
 

On Tue, 2020-10-27 at 14:49 +0800, Chen-Yu Tsai wrote:
On Fri, Oct 23, 2020 at 1:27 AM Ben Hutchings
<ben.hutchings@codethink.co.uk> wrote:
On Thu, 2020-10-22 at 18:00 +0800, Chen-Yu Tsai wrote:
Hi,

After today's CIP weekly meeting, Pavel proposed the idea of skipping
merge requests for the cip-kernel-sec repository:
[...]
Ben, could you share your thoughts on this?
I was going to suggest you do that, for other reasons. I didn't
realise you weren't able to do so. It looks you have been granted that
permission now, is that right?
Yes. So in the future I'll push all script-imported updates directly.
Would you still like to review manual data input, or should I push those
directly as well?
Please push them directly.

Ben.

--
Ben Hutchings, Software Developer Codethink Ltd
https://www.codethink.co.uk/ Dale House, 35 Dale Street
Manchester, M1 2HF, United Kingdom


Re: Direct Pushes for cip-kernel-sec

Chen-Yu Tsai (Moxa) <wens@...>
 

On Fri, Oct 23, 2020 at 1:27 AM Ben Hutchings
<ben.hutchings@codethink.co.uk> wrote:

On Thu, 2020-10-22 at 18:00 +0800, Chen-Yu Tsai wrote:
Hi,

After today's CIP weekly meeting, Pavel proposed the idea of skipping
merge requests for the cip-kernel-sec repository:
[...]
Ben, could you share your thoughts on this?
I was going to suggest you do that, for other reasons. I didn't
realise you weren't able to do so. It looks you have been granted that
permission now, is that right?
Yes. So in the future I'll push all script-imported updates directly.
Would you still like to review manual data input, or should I push those
directly as well?

ChenYu


[ANNOUNCE] Release v4.19.152-cip37

Nobuhiro Iwamatsu
 

Hi,

CIP kernel team has released Linux kernel v4.19.152-cip37.
The linux-4.19.y-cip tree has been updated base version from v4.19.150
to v4.19.152. And this release adds PCI-E driver support for Renesas RZ/G2.

You can get this release via the git tree at:

v4.19.152-cip37:
repository:
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git
branch:
linux-4.19.y-cip
commit hash:
6dbf6c14540a8a35584b4414d02f3e08294c6c36
added commits:
CIP: Bump version suffix to -cip37 after merge from stable
misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller
arm64: defconfig: Enable R-Car PCIe endpoint driver
PCI: rcar: Add endpoint mode support
dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller
PCI: rcar: Fix calculating mask for PCIEPAMR register
PCI: rcar: Move shareable code to a common file
arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST
PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c
PCI: endpoint: functions/pci-epf-test: Print throughput information
PCI: endpoint: Add support to handle multiple base for mapping outbound memory
PCI: endpoint: Pass page size as argument to pci_epc_mem_init()
PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
PCI: pci-epf-test: Add support to defer core initialization
PCI: endpoint: Add notification for core init completion
PCI: endpoint: Add core init notifying feature
PCI: endpoint: Assign function number for each PF in EPC core
PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex
PCI: endpoint: Replace spinlock with mutex
PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF
tools: PCI: Fix fd leakage
tools: PCI: Exit with error code when test fails
PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address
PCI: endpoint: Fix clearing start entry in configfs
PCI: endpoint: Cast the page number to phys_addr_t
PCI: endpoint: Clear BAR before freeing its space
PCI: endpoint: Skip odd BAR when skipping 64bit BAR
PCI: endpoint: Allocate enough space for fixed size BAR
PCI: endpoint: Set endpoint controller pointer to NULL
PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
PCI: endpoint: Fix a potential NULL pointer dereference
PCI: endpoint: Remove features member in struct pci_epc
PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
PCI: pci-epf-test: Remove setting epf_bar flags in function driver
PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
PCI: endpoint: Add helper to get first unreserved BAR
PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
PCI: endpoint: Add new pci_epc_ops to get EPC features

Best regards,
Nobuhiro


Re: [PATCH 4.19.y-cip 4/6] PCI: rcar: Add endpoint mode support

Pavel Machek
 

Hi!

+ pm_runtime_enable(dev);
+ err = pm_runtime_get_sync(dev);
+ if (err < 0) {
+ dev_err(dev, "pm_runtime_get_sync failed\n");
+ goto err_pm_disable;
+ }
I believe this should go to pm_put.
Agreed pm_runtime_get_sync() increments the runtime PM usage counter even when it fails. I'll fix this in upstream first and then backport.
Thank you. This one is worth backporting, I don't believe we need the
other cleanups in -cip.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 1/6] PCI: rcar: Move shareable code to a common file

Pavel Machek
 

Hi!

+int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
+{
+ unsigned int timeout = 10000;
+
+ while (timeout--) {
+ if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
+ return 0;
+
+ udelay(5);
+ cpu_relax();
+ }
+
+ return -ETIMEDOUT;
+}
This has same problem. Plus, I don't believe cpu_relax() is good idea
there. Relaxing CPU every 5usec will not change anything.
Agreed (as above). wrt cpu_relax() I believe this was added to improve the performance of other HW threads.
Yes, but you'd need to call it in a loop. It will be effective if done
inside udelay(), but not like this.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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