Date   

[isar-cip-core][PATCH] linux-cip-common: Add files directory to FILESEXTRAPATHS

Kanagarajan, Vijaikumar
 

Add recipes-kernel/linux/files directory to searchpath.

Files like preempt-rt.cfg are not accesible when you use
the linux-cip-rt-common.inc file in linux recipes defined
in other layers.
This makes the linux-cip-rt-common.inc file unusable in
other layers.

Fix that by adding recipes-kernel/linux/files to
FILESEXTRAPATHS.

Signed-off-by: Vijai Kumar K <Vijaikumar_Kanagarajan@mentor.com>
---
recipes-kernel/linux/linux-cip-common.inc | 2 ++
1 file changed, 2 insertions(+)

diff --git a/recipes-kernel/linux/linux-cip-common.inc b/recipes-kernel/linux/linux-cip-common.inc
index 6db1d1d..f35168f 100644
--- a/recipes-kernel/linux/linux-cip-common.inc
+++ b/recipes-kernel/linux/linux-cip-common.inc
@@ -9,6 +9,8 @@
# SPDX-License-Identifier: MIT
#

+FILESEXTRAPATHS_prepend := "${FILE_DIRNAME}/files:"
+
KERNEL_DEFCONFIG ?= "${MACHINE}_defconfig"

def conditional(variable, checkvalue, truevalue, falsevalue, d):
--
2.17.1


Re: [PATCH 4.4.y-cip 0/9] Renesas RZ/G1 add support for DU, TPU, PWM, LCD

Pavel Machek
 

Hi!


This patch series adds support for TPU, PWM, DU to R8A7742 SoC and
enable LCD on iwg21d board.

All the patches have been cherry picked from v5.11-rc3.
Series looks okay to me. I can apply it if there are no other
comments.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


[PATCH 4.4.y-cip 9/9] ARM: dts: r8a7742-iwg21d-q7: Add LCD support

Lad Prabhakar
 

commit 9b533dc8f340f5e9e7f2ed610510b2191d5e447c upstream.

The iwg21d comes with a 7" capacitive touch screen, therefore
add support for it.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200929140502.16017-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: remove the LVDS decoder as there is no driver for it; add panel
timings to panel node since the LVDS driver reads them off the panel DT
node; dropped power-supply property from panel node; dropped vcc_3v3_tft1
node; dropped vcc-supply property from touch node]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 73 +++++++++++++++++++++++++
1 file changed, 73 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
index 958edef2004c..e876ba63c8c3 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
@@ -51,6 +51,41 @@
clock-frequency = <26000000>;
};

+ lcd_backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&tpu 2 5000000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ pinctrl-0 = <&backlight_pins>;
+ pinctrl-names = "default";
+ default-brightness-level = <7>;
+ enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ panel {
+ compatible = "edt,etm0700g0dh6";
+ backlight = <&lcd_backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <33260>;
+ hactive = <800>;
+ vactive = <480>;
+
+ hfront-porch = <40>;
+ hback-porch = <88>;
+ hsync-len = <128>;
+
+ vback-porch = <33>;
+ vfront-porch = <10>;
+ vsync-len = <2>;
+ };
+ };
+
reg_1p5v: 1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
@@ -128,6 +163,15 @@
VDDIO-supply = <&reg_3p3v>;
VDDD-supply = <&reg_1p5v>;
};
+
+ touch: touchpanel@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
+ /* GP1_29 is also shared with audio codec reset pin */
+ reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ };
};

&can1 {
@@ -141,6 +185,26 @@
status = "okay";
};

+&du {
+ status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&gpio0 {
+ touch-interrupt {
+ gpio-hog;
+ gpios = <24 GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
+
&gpio1 {
can-trx-en-gpio{
gpio-hog;
@@ -218,6 +282,11 @@
function = "avb";
};

+ backlight_pins: backlight {
+ groups = "tpu0_to2";
+ function = "tpu0";
+ };
+
can1_pins: can1 {
groups = "can1_data_b";
function = "can1";
@@ -303,6 +372,10 @@
shared-pin;
};

+&tpu {
+ status = "okay";
+};
+
&usbphy {
status = "okay";
};
--
2.17.1


[PATCH 4.4.y-cip 8/9] ARM: dts: r8a7742: Add PWM SoC support

Lad Prabhakar
 

commit b4a43810f596b55cb29b37ce4212ac7319661fb7 upstream.

Add the definitions for pwm[0123456] to the SoC .dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/20200806183152.11809-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL:changed clocks and power-domain properties, removed resets property]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 63 ++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 755136f88b01..ba2ddff1eff6 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -1371,6 +1371,69 @@
status = "disabled";
};

+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&mstp5_clks R8A7742_CLK_PWM>;
+ power-domains = <&cpg_clocks>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = <&mstp5_clks R8A7742_CLK_PWM>;
+ power-domains = <&cpg_clocks>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = <&mstp5_clks R8A7742_CLK_PWM>;
+ power-domains = <&cpg_clocks>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = <&mstp5_clks R8A7742_CLK_PWM>;
+ power-domains = <&cpg_clocks>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = <&mstp5_clks R8A7742_CLK_PWM>;
+ power-domains = <&cpg_clocks>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = <&mstp5_clks R8A7742_CLK_PWM>;
+ power-domains = <&cpg_clocks>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = <&mstp5_clks R8A7742_CLK_PWM>;
+ power-domains = <&cpg_clocks>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
--
2.17.1


[PATCH 4.4.y-cip 7/9] dt-bindings: pwm: renesas,pwm-rcar: Add r8a7742 support

Lad Prabhakar
 

commit 3b1954cd57bf7648417c593d60eac1ec661ad514 upstream.

Document RZ/G1H (R8A7742) SoC bindings.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
[PL:Patched text version of bindings file]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
index 4493fc5771a9..e47a8d2495e8 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
@@ -2,6 +2,7 @@

Required Properties:
- compatible: should be "renesas,pwm-rcar" and one of the following.
+ - "renesas,pwm-r8a7742": for RZ/G1H
- "renesas,pwm-r8a7743": for RZ/G1M
- "renesas,pwm-r8a7745": for RZ/G1E
- "renesas,pwm-r8a7778": for R-Car M1A
--
2.17.1


[PATCH 4.4.y-cip 6/9] ARM: dts: r8a7742: Add TPU support

Lad Prabhakar
 

commit 02b24822953571d3ef83029e53bcd011d39dcb39 upstream.

Add TPU support to R8A7742 SoC DT.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/20200806183152.11809-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL:changed clocks and power-domain properties, removed resets property]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index d4087bacd6f2..755136f88b01 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -742,6 +742,16 @@
reg = <0 0xe6060000 0 0x250>;
};

+ tpu: pwm@e60f0000 {
+ compatible = "renesas,tpu-r8a7742", "renesas,tpu";
+ reg = <0 0xe60f0000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7742_CLK_TPU0>;
+ power-domains = <&cpg_clocks>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
apmu@e6151000 {
compatible = "renesas,r8a7742-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
--
2.17.1


[PATCH 4.4.y-cip 5/9] dt-bindings: pwm: renesas,tpu-pwm: Document r8a7742 support

Lad Prabhakar
 

commit 6a78dfb8facadef74bdf5af5ed84f6c722299fbb upstream.

Document r8a7742 specific compatible strings. No driver change is
needed as the fallback compatible string "renesas,tpu" activates the
right code in the driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
[PL:Patched text version of bindings file]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
index 90e0a0a3ae71..1613243d88aa 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
@@ -5,6 +5,7 @@ Required Properties:
- compatible: should be one of the following.
- "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
- "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
+ - "renesas,tpu-r8a7742": for R8A7742 (RZ/G1H) compatible PWM controller.
- "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller.
- "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller.
- "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
--
2.17.1


[PATCH 4.4.y-cip 4/9] ARM: dts: r8a7742: Add DU support

Lad Prabhakar
 

commit 6a62f64305c65e78db290c0ca153759b6b9ca130 upstream.

Add a Display Unit (DU) node to r8a7742 SoC DT.
Boards that want to enable the DU need to specify the output topology.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200807174954.14448-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: changed clocks and reg property, added reg-names property, dropped
resets, reset-names properties]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 39 ++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 2ad6f965ccbd..d4087bacd6f2 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -1927,6 +1927,45 @@
renesas,#wpf = <4>;
};

+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7742";
+ reg = <0 0xfeb00000 0 0x70000>,
+ <0 0xfeb90000 0 0x1c>,
+ <0 0xfeb94000 0 0x1c>;
+ reg-names = "du", "lvds.0", "lvds.1";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7742_CLK_DU0>,
+ <&mstp7_clks R8A7742_CLK_DU1>,
+ <&mstp7_clks R8A7742_CLK_DU2>,
+ <&mstp7_clks R8A7742_CLK_LVDS0>,
+ <&mstp7_clks R8A7742_CLK_LVDS1>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds1: endpoint {
+ };
+ };
+ };
+ };
+
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
--
2.17.1


[PATCH 4.4.y-cip 3/9] drm: rcar-du: Add r8a7742 support

Lad Prabhakar
 

commit 9edf73fece3d27e6fb5a764b732eca94c941838e upstream.

Add display support for the r8a7742 (RZ/G1H).

The RZ/G1H shares a common, compatible configuration with the r8a7790
(R-Car H2) so that device info structure is reused, the only difference
being TCON is unsupported on RZ/G1H (Currently unsupported by the driver).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[PL:LVDS lanes 1 and 3 are switched in ES1 hardware (R8A7790) due to which
RCAR_DU_QUIRK_LVDS_LANES quirk was introduced, this quirk is not valid on
R8A7742 SoC so instead added new device info structure for R8A7742 SoC;
fixed typo in commit message direct->display]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index edb9c3f0b862..586bc28b641e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -35,6 +35,32 @@
* Device Information
*/

+static const struct rcar_du_device_info rcar_du_r8a7742_info = {
+ .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+ .quirks = RCAR_DU_QUIRK_ALIGN_128B,
+ .num_crtcs = 3,
+ .routes = {
+ /* R8A7742 has one RGB output and two LVDS outputs. */
+ [RCAR_DU_OUTPUT_DPAD0] = {
+ .possible_crtcs = BIT(2) | BIT(1) | BIT(0),
+ .encoder_type = DRM_MODE_ENCODER_NONE,
+ .port = 0,
+ },
+ [RCAR_DU_OUTPUT_LVDS0] = {
+ .possible_crtcs = BIT(0),
+ .encoder_type = DRM_MODE_ENCODER_LVDS,
+ .port = 1,
+ },
+ [RCAR_DU_OUTPUT_LVDS1] = {
+ .possible_crtcs = BIT(2) | BIT(1),
+ .encoder_type = DRM_MODE_ENCODER_LVDS,
+ .port = 2,
+ },
+ },
+ .num_lvds = 2,
+};
+
static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS,
@@ -174,6 +200,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
};

static const struct of_device_id rcar_du_of_table[] = {
+ { .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7742_info },
{ .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
{ .compatible = "renesas,du-r8a7744", .data = &rzg1_du_r8a7743_info },
{ .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
--
2.17.1


[PATCH 4.4.y-cip 2/9] display: renesas,du: Document the r8a7742 bindings

Lad Prabhakar
 

commit c3415d91832cf47bf54973ef5415caeaba5249c6 upstream.

Document the RZ/G1H (R8A7742) SoC in the R-Car DU bindings.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[PL: Manually applied the changes, dropped Port3 column changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
index 96cc0805da56..d2f8a74c6718 100644
--- a/Documentation/devicetree/bindings/display/renesas,du.txt
+++ b/Documentation/devicetree/bindings/display/renesas,du.txt
@@ -3,6 +3,7 @@
Required Properties:

- compatible: must be one of the following.
+ - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU
- "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
- "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
@@ -46,6 +47,7 @@ corresponding to each DU output.

Port 0 Port1 Port2
-----------------------------------------------------------------------------
+ R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1
R8A7743 (RZ/G1M) DPAD 0 LVDS 0 -
R8A7744 (RZ/G1N) DPAD 0 LVDS 0 -
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 -
--
2.17.1


[PATCH 4.4.y-cip 1/9] pinctrl: renesas: r8a7790: Optimize pinctrl image size for R8A7742

Lad Prabhakar
 

From: Biju Das <biju.das.jz@bp.renesas.com>

commit 529b8eecb5c3b61cc53a21b72a12304a03e83c9f upstream.

This driver supports both RZ/G1H and R-Car H2 SoCs.
Optimize pinctrl image size for RZ/G1H, when support for R-Car H2
(R8A7790) is not enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index f85bd1623d46..62e3664ff227 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2412,6 +2412,8 @@ static const unsigned int intc_irq3_pins[] = {
static const unsigned int intc_irq3_mux[] = {
IRQ3_MARK,
};
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
/* - MLB+ ------------------------------------------------------------------- */
static const unsigned int mlb_3pin_pins[] = {
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
@@ -2419,6 +2421,8 @@ static const unsigned int mlb_3pin_pins[] = {
static const unsigned int mlb_3pin_mux[] = {
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
+
/* - MMCIF0 ----------------------------------------------------------------- */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
@@ -4046,7 +4050,9 @@ static const unsigned int vin3_clk_mux[] = {

static const struct {
struct sh_pfc_pin_group common[298];
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
struct sh_pfc_pin_group automotive[1];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@@ -4348,9 +4354,11 @@ static const struct {
SH_PFC_PIN_GROUP(vin3_clkenb),
SH_PFC_PIN_GROUP(vin3_clk),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
.automotive = {
SH_PFC_PIN_GROUP(mlb_3pin),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
};

static const char * const audio_clk_groups[] = {
@@ -4494,9 +4502,11 @@ static const char * const intc_groups[] = {
"intc_irq3",
};

+#ifdef CONFIG_PINCTRL_PFC_R8A7790
static const char * const mlb_groups[] = {
"mlb_3pin",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */

static const char * const mmc0_groups[] = {
"mmc0_data1",
@@ -4831,7 +4841,9 @@ static const char * const vin3_groups[] = {

static const struct {
struct sh_pfc_function common[58];
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
struct sh_pfc_function automotive[1];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -4893,9 +4905,11 @@ static const struct {
SH_PFC_FUNCTION(vin2),
SH_PFC_FUNCTION(vin3),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
.automotive = {
SH_PFC_FUNCTION(mlb),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
};

static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.17.1


[PATCH 4.4.y-cip 0/9] Renesas RZ/G1 add support for DU, TPU, PWM, LCD

Lad Prabhakar
 

Hi All,

This patch series adds support for TPU, PWM, DU to R8A7742 SoC and
enable LCD on iwg21d board.

All the patches have been cherry picked from v5.11-rc3.

Cheers,
Prabhakar

Biju Das (1):
pinctrl: renesas: r8a7790: Optimize pinctrl image size for R8A7742

Lad Prabhakar (8):
display: renesas,du: Document the r8a7742 bindings
drm: rcar-du: Add r8a7742 support
ARM: dts: r8a7742: Add DU support
dt-bindings: pwm: renesas,tpu-pwm: Document r8a7742 support
ARM: dts: r8a7742: Add TPU support
dt-bindings: pwm: renesas,pwm-rcar: Add r8a7742 support
ARM: dts: r8a7742: Add PWM SoC support
ARM: dts: r8a7742-iwg21d-q7: Add LCD support

.../bindings/display/renesas,du.txt | 2 +
.../bindings/pwm/renesas,pwm-rcar.txt | 1 +
.../bindings/pwm/renesas,tpu-pwm.txt | 1 +
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 73 ++++++++++++
arch/arm/boot/dts/r8a7742.dtsi | 112 ++++++++++++++++++
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 27 +++++
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 14 +++
7 files changed, 230 insertions(+)

--
2.17.1


Cip-kernel-sec Updates for Week of 2021-01-14

Chen-Yu Tsai (Moxa) <wens@...>
 

Hi everyone,

Three new issues this week:

- CVE-2020-28374 [target/xcopy] - fixed
Fix is missing from 4.4 and 4.9; notified Sasha on IRC
- CVE-2020-35508 [fork copy_process race] - fixed for all kernels
- CVE-2021-20177 [netfilter kernel panic] - fixed for all kernels
Findings were also reported back to Debian


Regards
ChenYu


Re: [isar-cip-core] [PATCH] swupdate-img.bbclass: add checksum in non signed case as well

Henning Schild <henning.schild@...>
 

Am Wed, 13 Jan 2021 12:33:12 +0100
schrieb Jan Kiszka <jan.kiszka@siemens.com>:

On 13.01.21 12:02, Claudius Heine wrote:
On 2021-01-13 11:55, Jan Kiszka wrote:
On 13.01.21 11:52, Claudius Heine wrote:
Hi Jan,

On 2021-01-13 11:46, Jan Kiszka wrote:
On 11.01.21 16:48, Henning Schild wrote:
From: Claudius Heine <ch@denx.de>
Can you also provide a reasoning here?
I can, but I guess you mean that a commit message should be added
here.
...or that you provide me a text I can fill in on merge.
Ok here is my take:

```
Also unsigned images should contain a checksum in the
swdescription, for instance in case `DISABLE_CPIO_CRC=y` is set in
swupdate and a USB stick is used for update delivery, only such a
checksum would protect against file corruption.
```
Thanks, applied with this text.
Sweet, thanks!

@claudius this might be ready to pull into our layer anytime soon,
should be patch-free now

Henning

Jan


Re: [isar-cip-core] [PATCH] swupdate-img.bbclass: add checksum in non signed case as well

Henning Schild <henning.schild@...>
 

Am Wed, 13 Jan 2021 11:46:03 +0100
schrieb Jan Kiszka <jan.kiszka@siemens.com>:

On 11.01.21 16:48, Henning Schild wrote:
From: Claudius Heine <ch@denx.de>
Can you also provide a reasoning here?
This is taken from a layer where we use a postupdate-script as part of
an swu. The whole swu is not signed, still we want basic integrity
checking based on checksums.

My guess is that whenever you have SWU_ADDITIONAL_FILES and do not
sign, you might get a problem because of missing checksums.

But i would wait for Claudius to provide the reasoning. I guess it
should become part of the commit message in a v2.

Henning

Signed-off-by: Claudius Heine <ch@denx.de>
Signed-off-by: Henning Schild <henning.schild@siemens.com>
---
classes/swupdate-img.bbclass | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/classes/swupdate-img.bbclass
b/classes/swupdate-img.bbclass index a21d6ec..a7a70f6 100644
--- a/classes/swupdate-img.bbclass
+++ b/classes/swupdate-img.bbclass
@@ -39,14 +39,14 @@ do_swupdate_image() {
image_do_mounts
cp -f '${SIGN_KEY}' '${WORKDIR}/dev.key'
test -e '${SIGN_CRT}' && cp -f '${SIGN_CRT}'
'${WORKDIR}/dev.crt' -
- # Fill in file check sums
- for file in ${SWU_ADDITIONAL_FILES}; do
- sed -i "s:$file-sha256:$(sha256sum
'${WORKDIR}/swu/'$file | cut -f 1 -d ' '):g" \
- '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
- done
fi

+ # Fill in file check sums
+ for file in ${SWU_ADDITIONAL_FILES}; do
+ sed -i "s:$file-sha256:$(sha256sum '${WORKDIR}/swu/'$file
| cut -f 1 -d ' '):g" \
+ '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
+ done
+
cd "${WORKDIR}/swu"
for file in '${SWU_DESCRIPTION_FILE}' ${SWU_ADDITIONAL_FILES};
do echo "$file"
Jan


Re: [isar-cip-core] [PATCH] swupdate-img.bbclass: add checksum in non signed case as well

Claudius Heine <ch@...>
 

On 2021-01-13 11:55, Jan Kiszka wrote:
On 13.01.21 11:52, Claudius Heine wrote:
Hi Jan,

On 2021-01-13 11:46, Jan Kiszka wrote:
On 11.01.21 16:48, Henning Schild wrote:
From: Claudius Heine <ch@denx.de>
Can you also provide a reasoning here?
I can, but I guess you mean that a commit message should be added here.
...or that you provide me a text I can fill in on merge.
Ok here is my take:

```
Also unsigned images should contain a checksum in the swdescription, for instance in case `DISABLE_CPIO_CRC=y` is set in swupdate and a USB stick is used for update delivery, only such a checksum would protect against file corruption.
```

regards,
Claudius

Jan

Our swupdate has `DISABLE_CPIO_CRC=y` (because our images might be >2GB)
and we also currently support update via usb stick without any
signatures. So the only checksum that we have would be the sha256sum
inside the swdescription.

regards,
Claudius


Signed-off-by: Claudius Heine <ch@denx.de>
Signed-off-by: Henning Schild <henning.schild@siemens.com>
---
  classes/swupdate-img.bbclass | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/classes/swupdate-img.bbclass b/classes/swupdate-img.bbclass
index a21d6ec..a7a70f6 100644
--- a/classes/swupdate-img.bbclass
+++ b/classes/swupdate-img.bbclass
@@ -39,14 +39,14 @@ do_swupdate_image() {
          image_do_mounts
          cp -f '${SIGN_KEY}' '${WORKDIR}/dev.key'
          test -e '${SIGN_CRT}' && cp -f '${SIGN_CRT}'
'${WORKDIR}/dev.crt'
-
-        # Fill in file check sums
-        for file in ${SWU_ADDITIONAL_FILES}; do
-            sed -i "s:$file-sha256:$(sha256sum
'${WORKDIR}/swu/'$file | cut -f 1 -d ' '):g" \
-                '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
-        done
      fi
  +    # Fill in file check sums
+    for file in ${SWU_ADDITIONAL_FILES}; do
+        sed -i "s:$file-sha256:$(sha256sum '${WORKDIR}/swu/'$file |
cut -f 1 -d ' '):g" \
+            '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
+    done
+
      cd "${WORKDIR}/swu"
      for file in '${SWU_DESCRIPTION_FILE}' ${SWU_ADDITIONAL_FILES}; do
          echo "$file"
Jan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-54 Fax: (+49)-8142-66989-80 Email: ch@denx.de

PGP key: 6FF2 E59F 00C6 BC28 31D8 64C1 1173 CB19 9808 B153
Keyserver: hkp://pool.sks-keyservers.net


Re: [isar-cip-core] [PATCH] swupdate-img.bbclass: add checksum in non signed case as well

Claudius Heine <ch@...>
 

Hi Jan,

On 2021-01-13 11:46, Jan Kiszka wrote:
On 11.01.21 16:48, Henning Schild wrote:
From: Claudius Heine <ch@denx.de>
Can you also provide a reasoning here?
I can, but I guess you mean that a commit message should be added here.

Our swupdate has `DISABLE_CPIO_CRC=y` (because our images might be >2GB) and we also currently support update via usb stick without any signatures. So the only checksum that we have would be the sha256sum inside the swdescription.

regards,
Claudius


Signed-off-by: Claudius Heine <ch@denx.de>
Signed-off-by: Henning Schild <henning.schild@siemens.com>
---
classes/swupdate-img.bbclass | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/classes/swupdate-img.bbclass b/classes/swupdate-img.bbclass
index a21d6ec..a7a70f6 100644
--- a/classes/swupdate-img.bbclass
+++ b/classes/swupdate-img.bbclass
@@ -39,14 +39,14 @@ do_swupdate_image() {
image_do_mounts
cp -f '${SIGN_KEY}' '${WORKDIR}/dev.key'
test -e '${SIGN_CRT}' && cp -f '${SIGN_CRT}' '${WORKDIR}/dev.crt'
-
- # Fill in file check sums
- for file in ${SWU_ADDITIONAL_FILES}; do
- sed -i "s:$file-sha256:$(sha256sum '${WORKDIR}/swu/'$file | cut -f 1 -d ' '):g" \
- '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
- done
fi
+ # Fill in file check sums
+ for file in ${SWU_ADDITIONAL_FILES}; do
+ sed -i "s:$file-sha256:$(sha256sum '${WORKDIR}/swu/'$file | cut -f 1 -d ' '):g" \
+ '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
+ done
+
cd "${WORKDIR}/swu"
for file in '${SWU_DESCRIPTION_FILE}' ${SWU_ADDITIONAL_FILES}; do
echo "$file"
Jan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-54 Fax: (+49)-8142-66989-80 Email: ch@denx.de

PGP key: 6FF2 E59F 00C6 BC28 31D8 64C1 1173 CB19 9808 B153
Keyserver: hkp://pool.sks-keyservers.net


Re: [isar-cip-core] [PATCH] swupdate-img.bbclass: add checksum in non signed case as well

Jan Kiszka
 

On 13.01.21 12:02, Claudius Heine wrote:
On 2021-01-13 11:55, Jan Kiszka wrote:
On 13.01.21 11:52, Claudius Heine wrote:
Hi Jan,

On 2021-01-13 11:46, Jan Kiszka wrote:
On 11.01.21 16:48, Henning Schild wrote:
From: Claudius Heine <ch@denx.de>
Can you also provide a reasoning here?
I can, but I guess you mean that a commit message should be added here.
...or that you provide me a text I can fill in on merge.
Ok here is my take:

```
Also unsigned images should contain a checksum in the swdescription, for
instance in case `DISABLE_CPIO_CRC=y` is set in swupdate and a USB stick
is used for update delivery, only such a checksum would protect against
file corruption.
```
Thanks, applied with this text.

Jan

--
Siemens AG, T RDA IOT
Corporate Competence Center Embedded Linux


Re: [isar-cip-core] [PATCH] swupdate-img.bbclass: add checksum in non signed case as well

Jan Kiszka
 

On 13.01.21 11:52, Claudius Heine wrote:
Hi Jan,

On 2021-01-13 11:46, Jan Kiszka wrote:
On 11.01.21 16:48, Henning Schild wrote:
From: Claudius Heine <ch@denx.de>
Can you also provide a reasoning here?
I can, but I guess you mean that a commit message should be added here.
...or that you provide me a text I can fill in on merge.

Jan

Our swupdate has `DISABLE_CPIO_CRC=y` (because our images might be >2GB)
and we also currently support update via usb stick without any
signatures. So the only checksum that we have would be the sha256sum
inside the swdescription.

regards,
Claudius


Signed-off-by: Claudius Heine <ch@denx.de>
Signed-off-by: Henning Schild <henning.schild@siemens.com>
---
  classes/swupdate-img.bbclass | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/classes/swupdate-img.bbclass b/classes/swupdate-img.bbclass
index a21d6ec..a7a70f6 100644
--- a/classes/swupdate-img.bbclass
+++ b/classes/swupdate-img.bbclass
@@ -39,14 +39,14 @@ do_swupdate_image() {
          image_do_mounts
          cp -f '${SIGN_KEY}' '${WORKDIR}/dev.key'
          test -e '${SIGN_CRT}' && cp -f '${SIGN_CRT}'
'${WORKDIR}/dev.crt'
-
-        # Fill in file check sums
-        for file in ${SWU_ADDITIONAL_FILES}; do
-            sed -i "s:$file-sha256:$(sha256sum
'${WORKDIR}/swu/'$file | cut -f 1 -d ' '):g" \
-                '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
-        done
      fi
  +    # Fill in file check sums
+    for file in ${SWU_ADDITIONAL_FILES}; do
+        sed -i "s:$file-sha256:$(sha256sum '${WORKDIR}/swu/'$file |
cut -f 1 -d ' '):g" \
+            '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
+    done
+
      cd "${WORKDIR}/swu"
      for file in '${SWU_DESCRIPTION_FILE}' ${SWU_ADDITIONAL_FILES}; do
          echo "$file"
Jan

--
Siemens AG, T RDA IOT
Corporate Competence Center Embedded Linux


Re: [isar-cip-core] [PATCH] swupdate-img.bbclass: add checksum in non signed case as well

Jan Kiszka
 

On 11.01.21 16:48, Henning Schild wrote:
From: Claudius Heine <ch@denx.de>
Can you also provide a reasoning here?

Signed-off-by: Claudius Heine <ch@denx.de>
Signed-off-by: Henning Schild <henning.schild@siemens.com>
---
classes/swupdate-img.bbclass | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/classes/swupdate-img.bbclass b/classes/swupdate-img.bbclass
index a21d6ec..a7a70f6 100644
--- a/classes/swupdate-img.bbclass
+++ b/classes/swupdate-img.bbclass
@@ -39,14 +39,14 @@ do_swupdate_image() {
image_do_mounts
cp -f '${SIGN_KEY}' '${WORKDIR}/dev.key'
test -e '${SIGN_CRT}' && cp -f '${SIGN_CRT}' '${WORKDIR}/dev.crt'
-
- # Fill in file check sums
- for file in ${SWU_ADDITIONAL_FILES}; do
- sed -i "s:$file-sha256:$(sha256sum '${WORKDIR}/swu/'$file | cut -f 1 -d ' '):g" \
- '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
- done
fi

+ # Fill in file check sums
+ for file in ${SWU_ADDITIONAL_FILES}; do
+ sed -i "s:$file-sha256:$(sha256sum '${WORKDIR}/swu/'$file | cut -f 1 -d ' '):g" \
+ '${WORKDIR}/swu/${SWU_DESCRIPTION_FILE}'
+ done
+
cd "${WORKDIR}/swu"
for file in '${SWU_DESCRIPTION_FILE}' ${SWU_ADDITIONAL_FILES}; do
echo "$file"
Jan

--
Siemens AG, T RDA IOT
Corporate Competence Center Embedded Linux

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