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[PATCH 5.10.y-cip 02/61] dt-bindings: net: renesas,etheravb: Fix optional second clock name
Lad Prabhakar
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 6799e3f281e962628be531e8331bacd05b866134 upstream. If the optional "clock-names" property is present, but the optional TXC reference clock is not, "make dtbs_check" complains: ethernet@e6800000: clock-names: ['fck'] is too short Fix this by declaring that a single clock name is valid. While at it, drop the superfluous upper limit on the number of clocks, as it is implied by the list of descriptions. Fixes: 6f43735b6da64bd4 ("dt-bindings: net: renesas,etheravb: Add additional clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b3d91c9f70a15792ad19c87e4ea35fc876600fae.1620118901.git.geert+renesas@glider.be Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml index 7b32363ad8b4..8d1f467c95ba 100644 --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml @@ -50,12 +50,12 @@ properties: clocks: minItems: 1 - maxItems: 2 items: - description: AVB functional clock - description: Optional TXC reference clock clock-names: + minItems: 1 items: - const: fck - const: refclk -- 2.17.1
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[PATCH 5.10.y-cip 01/61] dt-bindings: net: renesas,etheravb: Add additional clocks
Lad Prabhakar
From: Adam Ford <aford173@gmail.com>
commit 6f43735b6da64bd46bc1ee2af5edce584a09012d upstream. The AVB driver assumes there is an external crystal, but it could be clocked by other means. In order to enable a programmable clock, it needs to be added to the clocks list and enabled in the driver. Since there currently only one clock, there is no clock-names list either. Update bindings to add the additional optional clock, and explicitly name both of them. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../devicetree/bindings/net/renesas,etheravb.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml index de9dd574a2f9..7b32363ad8b4 100644 --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml @@ -49,7 +49,16 @@ properties: interrupt-names: true clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + items: + - description: AVB functional clock + - description: Optional TXC reference clock + + clock-names: + items: + - const: fck + - const: refclk iommus: maxItems: 1 -- 2.17.1
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[PATCH 5.10.y-cip 00/61] Add Ethernet support to RZ/G2L
Lad Prabhakar
Hi All,
This patch series adds Ethernet support to RZ/G2L SoC and enables ETH support on RZ/G2L SMARC EVK. All the patches have been cherry picked from v5.16-rc8. Patches apply on top of [0]. [0] https://patchwork.kernel.org/project/cip-dev/cover/ 20220110115348.14297-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Adam Ford (3): dt-bindings: net: renesas,etheravb: Add additional clocks net: ethernet: ravb: Enable optional refclk net: ethernet: ravb: Fix release of refclk Biju Das (53): dt-bindings: net: renesas,etheravb: Document Gigabit Ethernet IP dt-bindings: net: renesas,etheravb: Drop "int_" prefix and "_n" suffix from interrupt names ravb: Fix a typo in comment ravb: Use unsigned int for num_tx_desc variable in struct ravb_private ravb: Add struct ravb_hw_info to driver data ravb: Add aligned_tx to struct ravb_hw_info ravb: Add max_rx_len to struct ravb_hw_info ravb: Add stats_len to struct ravb_hw_info ravb: Add gstrings_stats and gstrings_size to struct ravb_hw_info ravb: Add net_features and net_hw_features to struct ravb_hw_info ravb: Add internal delay hw feature to struct ravb_hw_info ravb: Add tx_counters to struct ravb_hw_info ravb: Remove the macros NUM_TX_DESC_GEN[23] ravb: Add multi_irq to struct ravb_hw_info ravb: Add no_ptp_cfg_active to struct ravb_hw_info ravb: Add ptp_cfg_active to struct ravb_hw_info ravb: Factorise ravb_ring_free function ravb: Factorise ravb_ring_format function ravb: Factorise ravb_ring_init function ravb: Factorise ravb_rx function ravb: Factorise ravb_adjust_link function ravb: Factorise ravb_set_features ravb: Factorise ravb_dmac_init function ravb: Factorise ravb_emac_init function ravb: Add reset support ravb: Rename "ravb_set_features_rx_csum" function to "ravb_set_features_rcar" ravb: Rename "no_ptp_cfg_active" and "ptp_cfg_active" variables ravb: Add nc_queue to struct ravb_hw_info ravb: Add support for RZ/G2L SoC ravb: Initialize GbEthernet DMAC ravb: Exclude gPTP feature support for RZ/G2L ravb: Add tsrq to struct ravb_hw_info ravb: Add magic_pkt to struct ravb_hw_info ravb: Add half_duplex to struct ravb_hw_info ravb: Remove extra TAB ravb: Initialize GbEthernet E-MAC ravb: Add rx_max_buf_size to struct ravb_hw_info ravb: Use ALIGN macro for max_rx_len ravb: Fillup ravb_alloc_rx_desc_gbeth() stub ravb: Fillup ravb_rx_ring_free_gbeth() stub ravb: Fillup ravb_rx_ring_format_gbeth() stub ravb: Fillup ravb_rx_gbeth() stub ravb: Add carrier_counters to struct ravb_hw_info ravb: Add support to retrieve stats for GbEthernet ravb: Rename "tsrq" variable ravb: Optimize ravb_emac_init_gbeth function ravb: Rename "nc_queue" feature bit ravb: Update ravb_emac_init_gbeth() ravb: Fix typo AVB->DMAC clk: renesas: r9a07g044: Add ethernet clock sources clk: renesas: r9a07g044: Add GbEthernet clock/reset arm64: dts: renesas: r9a07g044: Add GbEthernet nodes arm64: dts: renesas: rzg2l-smarc-som: Enable Ethernet Geert Uytterhoeven (2): dt-bindings: net: renesas,etheravb: Fix optional second clock name ravb: Remove checks for unsupported internal delay modes Sergey Shtylyov (2): ravb: remove APSR_DM ravb: update "undocumented" annotations Yang Yingliang (1): net: ethernet: ravb: Use devm_platform_get_and_ioremap_resource() .../bindings/net/renesas,etheravb.yaml | 50 +- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 40 + .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 97 ++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 1 - drivers/clk/renesas/r9a07g044-cpg.c | 29 +- drivers/clk/renesas/rzg2l-cpg.h | 3 + drivers/net/ethernet/renesas/ravb.h | 116 +- drivers/net/ethernet/renesas/ravb_main.c | 991 ++++++++++++++---- drivers/net/ethernet/renesas/ravb_ptp.c | 8 +- 9 files changed, 1082 insertions(+), 253 deletions(-) -- 2.17.1
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[PATCH v2 5.10.y-cip 15/15] clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 664bb2e45b89cd8213e3c9772713323f75e21892 upstream. Add IA55_CLK and DMAC_ACLK as critical clocks. Previously it worked ok, because of a bug in clock status function and the following patch in this series fixes the original bug. Fixes: c3e67ad6f5a2 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions") Fixes: eb829e549ba6 ("clk: renesas: r9a07g044: Add DMAC clocks/resets") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922112405.26413-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 4c94b94c4125..1490446985e2 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -186,6 +186,8 @@ static struct rzg2l_reset r9a07g044_resets[] = { static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A07G044_GIC600_GICCLK, + MOD_CLK_BASE + R9A07G044_IA55_CLK, + MOD_CLK_BASE + R9A07G044_DMAC_ACLK, }; const struct rzg2l_cpg_info r9a07g044_cpg_info = { -- 2.17.1
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[PATCH v2 5.10.y-cip 14/15] arm64: dts: renesas: rzg2l-smarc: Enable CANFD
Lad Prabhakar
commit 7ae09309c324120b145224789102e730a98950d5 upstream.
Enable CANFD on RZ/G2L SMARC platform. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210924102338.11595-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> [PL: manually applied the changes] Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 8e02311ff0a6..f2dc0c0f5fd3 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -30,6 +30,20 @@ }; }; +&canfd { + pinctrl-0 = <&can0_pins &can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -79,6 +93,32 @@ }; &pinctrl { + can0_pins: can0 { + pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */ + <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */ + }; + + /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ + can0-stb { + gpio-hog; + gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "can0_stb"; + }; + + can1_pins: can1 { + pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */ + <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */ + }; + + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ + can1-stb { + gpio-hog; + gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "can1_stb"; + }; + i2c0_pins: i2c0 { pins = "RIIC0_SDA", "RIIC0_SCL"; input-enable; -- 2.17.1
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[PATCH v2 5.10.y-cip 13/15] arm64: dts: renesas: rzg2l-smarc-som: Enable ADC on SMARC platform
Lad Prabhakar
commit 03f7d78e8850ddb8cb1e623ef93e9018e4049ad7 upstream.
Enable the ADC which is present on RZ/G2L SMARC SOM. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922212049.19851-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 0748f2e7396a..da1ee2206e1a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + / { memory@48000000 { device_type = "memory"; @@ -13,6 +15,21 @@ }; }; +&adc { + pinctrl-0 = <&adc_pins>; + pinctrl-names = "default"; + status = "okay"; + + /delete-node/ channel@6; + /delete-node/ channel@7; +}; + &extal_clk { clock-frequency = <24000000>; }; + +&pinctrl { + adc_pins: adc { + pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */ + }; +}; -- 2.17.1
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[PATCH v2 5.10.y-cip 12/15] arm64: dts: renesas: rzg2l-smarc-som: Move extal and memory nodes to SOM DTSI
Lad Prabhakar
commit 55c6826119f64be75c4b423a0092a8c1353a7a81 upstream.
Move extal and memory nodes to SOM DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922212049.19851-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../boot/dts/renesas/r9a07g044l2-smarc.dts | 7 +------ .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 4 ---- 3 files changed, 19 insertions(+), 10 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index d3f72ec62f03..247b0b3f1b58 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -7,15 +7,10 @@ /dts-v1/; #include "r9a07g044l2.dtsi" +#include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc.dtsi" / { model = "Renesas SMARC EVK based on r9a07g044l2"; compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi new file mode 100644 index 000000000000..0748f2e7396a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC SOM common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/ { + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 8ecc5b45fc99..8e02311ff0a6 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -39,10 +39,6 @@ status = "okay"; }; -&extal_clk { - clock-frequency = <24000000>; -}; - &hsusb { dr_mode = "otg"; status = "okay"; -- 2.17.1
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[PATCH v2 5.10.y-cip 11/15] arm64: dts: renesas: rzg2l-smarc: Enable I2C{0,1,3} support
Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 04637e2f73d1e77dc00aa046b4845af5fe7e7cef upstream. Enable I2C{0,1,3} support on RZ/G2L SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210920182955.13445-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 7ecd4a3f4175..8ecc5b45fc99 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -11,6 +11,9 @@ / { aliases { serial0 = &scif0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c3 = &i2c3; }; chosen { @@ -45,6 +48,27 @@ status = "okay"; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &ohci0 { dr_mode = "otg"; status = "okay"; @@ -59,6 +83,21 @@ }; &pinctrl { + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c3_pins: i2c3 { + pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */ + <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */ + }; + scif0_pins: scif0 { pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ -- 2.17.1
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[PATCH v2 5.10.y-cip 10/15] arm64: defconfig: Enable RZG2L_ADC
Lad Prabhakar
commit 93207e415d134e6fbcee6a723ab4cf060ef3926e upstream.
Enable ADC driver support for Renesas RZ/G2L based platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210927193551.22422-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 349933a08790..54cd7f1430d7 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -974,6 +974,7 @@ CONFIG_EXYNOS_ADC=y CONFIG_MAX9611=m CONFIG_QCOM_SPMI_ADC5=m CONFIG_ROCKCHIP_SARADC=m +CONFIG_RZG2L_ADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m CONFIG_IIO_CROS_EC_LIGHT_PROX=m -- 2.17.1
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[PATCH v2 5.10.y-cip 09/15] arm64: dts: renesas: r9a07g044: Add ADC node
Lad Prabhakar
commit b3f894354aa08eb853044a7f5029dbdfc7f3b792 upstream.
Add ADC node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210804202118.25745-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6eefba96f5c7..2fa29d81c2a7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -218,6 +218,48 @@ status = "disabled"; }; + adc: adc@10059000 { + compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; + reg = <0 0x10059000 0 0x400>; + interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G044_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G044_ADC_PRESETN>, + <&cpg R9A07G044_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; -- 2.17.1
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[PATCH v2 5.10.y-cip 08/15] clk: renesas: r9a07g044: Add clock and reset entries for ADC
Lad Prabhakar
commit 1b87d5bba32c1f25a12ba0625546e5375e3f998d upstream.
Add clock and reset entries for ADC block in CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210719085840.21842-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index f1e0be50283f..4c94b94c4125 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -145,6 +145,10 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x594, 0), DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, 0x598, 0), + DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, + 0x5a8, 0), + DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, + 0x5a8, 1), }; static struct rzg2l_reset r9a07g044_resets[] = { @@ -176,6 +180,8 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0), + DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1), }; static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { -- 2.17.1
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[PATCH v2 5.10.y-cip 07/15] clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
commit d520af345189c04095bdd256d3601864601ac562 upstream. Add SSIF-2 clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210702135010.5937-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 0c45cad4ee65..f1e0be50283f 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -97,6 +97,22 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, 0x52c, 1), + DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, + 0x570, 0), + DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 1), + DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, + 0x570, 2), + DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 3), + DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, + 0x570, 4), + DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 5), + DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, + 0x570, 6), + DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 7), DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, 0x578, 0), DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, @@ -137,6 +153,10 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), + DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), + DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2), + DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3), DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0), DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1), DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2), -- 2.17.1
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[PATCH v2 5.10.y-cip 06/15] iio: adc: rzg2l_adc: add missing clk_disable_unprepare() in rzg2l_adc_pm_runtime_resume()
Lad Prabhakar
From: Yang Yingliang <yangyingliang@huawei.com>
commit fa002b364981b49d04e818abbc06fd47a5ec7b51 upstream. Add clk_disable_unprepare() on error path in rzg2l_adc_pm_runtime_resume(). Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210819132416.175644-1-yangyingliang@huawei.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/iio/adc/rzg2l_adc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c index 6472170be9d1..e2cf11cb7495 100644 --- a/drivers/iio/adc/rzg2l_adc.c +++ b/drivers/iio/adc/rzg2l_adc.c @@ -559,8 +559,10 @@ static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev) return ret; ret = clk_prepare_enable(adc->adclk); - if (ret) + if (ret) { + clk_disable_unprepare(adc->pclk); return ret; + } rzg2l_adc_pwr(adc, true); -- 2.17.1
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[PATCH v2 5.10.y-cip 05/15] iio: adc: rzg2l_adc: Fix -EBUSY timeout error return
Lad Prabhakar
From: Colin Ian King <colin.king@canonical.com>
commit 9909a395e9807aa79145c9289d0c13d0133359a2 upstream. Currently when a timeout occurs in rzg2l_adc_hw_init the error -EBUSY is assigned to ret but the error code is used as the function is hard-coded to return 0. The variable ret is 0 before entering the while-loop hence the fix is just to return ret at the end of the function to return the success 0 or -EBUSY return code. Addresses-Coverity: ("Unused value") Fixes: d484c21bacfa ("iio: adc: Add driver for Renesas RZ/G2L A/D converter") Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210817172111.495897-1-colin.king@canonical.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/iio/adc/rzg2l_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c index 919108d798ba..6472170be9d1 100644 --- a/drivers/iio/adc/rzg2l_adc.c +++ b/drivers/iio/adc/rzg2l_adc.c @@ -390,7 +390,7 @@ static int rzg2l_adc_hw_init(struct rzg2l_adc *adc) exit_hw_init: clk_disable_unprepare(adc->pclk); - return 0; + return ret; } static void rzg2l_adc_pm_runtime_disable(void *data) -- 2.17.1
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[PATCH v2 5.10.y-cip 04/15] iio: adc: Add driver for Renesas RZ/G2L A/D converter
Lad Prabhakar
commit d484c21bacfa8bd2fa9fc26393ec59108f508c4c upstream.
Add ADC driver support for Renesas RZ/G2L A/D converter in SW trigger mode. A/D Converter block is a successive approximation analog-to-digital converter with a 12-bit accuracy and supports a maximum of 8 input channels. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210804202118.25745-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> [PL: Dropped read_label callback] Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- MAINTAINERS | 8 + drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rzg2l_adc.c | 589 ++++++++++++++++++++++++++++++++++++ 4 files changed, 608 insertions(+) create mode 100644 drivers/iio/adc/rzg2l_adc.c diff --git a/MAINTAINERS b/MAINTAINERS index 591b401f4fbe..c0d2a2cfcfd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14941,6 +14941,14 @@ L: linux-renesas-soc@vger.kernel.org S: Maintained F: drivers/phy/renesas/phy-rcar-gen3-usb*.c +RENESAS RZ/G2L A/D DRIVER +M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> +L: linux-iio@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml +F: drivers/iio/adc/rzg2l_adc.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel <p.zabel@pengutronix.de> S: Maintained diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index e39b679126a2..dfa5e1d2a0ca 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -876,6 +876,16 @@ config ROCKCHIP_SARADC To compile this driver as a module, choose M here: the module will be called rockchip_saradc. +config RZG2L_ADC + tristate "Renesas RZ/G2L ADC driver" + depends on ARCH_R9A07G044 || COMPILE_TEST + help + Say yes here to build support for the ADC found in Renesas + RZ/G2L family. + + To compile this driver as a module, choose M here: the + module will be called rzg2l_adc. + config SC27XX_ADC tristate "Spreadtrum SC27xx series PMICs ADC" depends on MFD_SC27XX_PMIC || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 90f94ada7b30..9c106945e2e4 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o obj-$(CONFIG_RCAR_GYRO_ADC) += rcar-gyroadc.o obj-$(CONFIG_RN5T618_ADC) += rn5t618-adc.o obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o +obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o obj-$(CONFIG_SPEAR_ADC) += spear_adc.o obj-$(CONFIG_STX104) += stx104.o diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c new file mode 100644 index 000000000000..919108d798ba --- /dev/null +++ b/drivers/iio/adc/rzg2l_adc.c @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L A/D Converter driver + * + * Copyright (c) 2021 Renesas Electronics Europe GmbH + * + * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/iio/iio.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> + +#define DRIVER_NAME "rzg2l-adc" + +#define RZG2L_ADM(n) ((n) * 0x4) +#define RZG2L_ADM0_ADCE BIT(0) +#define RZG2L_ADM0_ADBSY BIT(1) +#define RZG2L_ADM0_PWDWNB BIT(2) +#define RZG2L_ADM0_SRESB BIT(15) +#define RZG2L_ADM1_TRG BIT(0) +#define RZG2L_ADM1_MS BIT(2) +#define RZG2L_ADM1_BS BIT(4) +#define RZG2L_ADM1_EGA_MASK GENMASK(13, 12) +#define RZG2L_ADM2_CHSEL_MASK GENMASK(7, 0) +#define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24) +#define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16) +#define RZG2L_ADM3_ADCMP_E FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, 0xe) +#define RZG2L_ADM3_ADSMP_MASK GENMASK(15, 0) + +#define RZG2L_ADINT 0x20 +#define RZG2L_ADINT_INTEN_MASK GENMASK(7, 0) +#define RZG2L_ADINT_CSEEN BIT(16) +#define RZG2L_ADINT_INTS BIT(31) + +#define RZG2L_ADSTS 0x24 +#define RZG2L_ADSTS_CSEST BIT(16) +#define RZG2L_ADSTS_INTST_MASK GENMASK(7, 0) + +#define RZG2L_ADIVC 0x28 +#define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0) +#define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4) + +#define RZG2L_ADFIL 0x2c + +#define RZG2L_ADCR(n) (0x30 + ((n) * 0x4)) +#define RZG2L_ADCR_AD_MASK GENMASK(11, 0) + +#define RZG2L_ADSMP_DEFUALT_SAMPLING 0x578 + +#define RZG2L_ADC_MAX_CHANNELS 8 +#define RZG2L_ADC_CHN_MASK 0x7 +#define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4) + +struct rzg2l_adc_data { + const struct iio_chan_spec *channels; + u8 num_channels; +}; + +struct rzg2l_adc { + void __iomem *base; + struct clk *pclk; + struct clk *adclk; + struct reset_control *presetn; + struct reset_control *adrstn; + struct completion completion; + const struct rzg2l_adc_data *data; + struct mutex lock; + u16 last_val[RZG2L_ADC_MAX_CHANNELS]; +}; + +static const char * const rzg2l_adc_channel_name[] = { + "adc0", + "adc1", + "adc2", + "adc3", + "adc4", + "adc5", + "adc6", + "adc7", +}; + +static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg) +{ + return readl(adc->base + reg); +} + +static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val) +{ + writel(val, adc->base + reg); +} + +static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on) +{ + u32 reg; + + reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); + if (on) + reg |= RZG2L_ADM0_PWDWNB; + else + reg &= ~RZG2L_ADM0_PWDWNB; + rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); + udelay(2); +} + +static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start) +{ + int timeout = 5; + u32 reg; + + reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); + if (start) + reg |= RZG2L_ADM0_ADCE; + else + reg &= ~RZG2L_ADM0_ADCE; + rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); + + if (start) + return; + + do { + usleep_range(100, 200); + reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); + timeout--; + if (!timeout) { + pr_err("%s stopping ADC timed out\n", __func__); + break; + } + } while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE))); +} + +static void rzg2l_set_trigger(struct rzg2l_adc *adc) +{ + u32 reg; + + /* + * Setup ADM1 for SW trigger + * EGA[13:12] - Set 00 to indicate hardware trigger is invalid + * BS[4] - Enable 1-buffer mode + * MS[1] - Enable Select mode + * TRG[0] - Enable software trigger mode + */ + reg = rzg2l_adc_readl(adc, RZG2L_ADM(1)); + reg &= ~RZG2L_ADM1_EGA_MASK; + reg &= ~RZG2L_ADM1_BS; + reg &= ~RZG2L_ADM1_TRG; + reg |= RZG2L_ADM1_MS; + rzg2l_adc_writel(adc, RZG2L_ADM(1), reg); +} + +static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch) +{ + u32 reg; + + if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY) + return -EBUSY; + + rzg2l_set_trigger(adc); + + /* Select analog input channel subjected to conversion. */ + reg = rzg2l_adc_readl(adc, RZG2L_ADM(2)); + reg &= ~RZG2L_ADM2_CHSEL_MASK; + reg |= BIT(ch); + rzg2l_adc_writel(adc, RZG2L_ADM(2), reg); + + /* + * Setup ADINT + * INTS[31] - Select pulse signal + * CSEEN[16] - Enable channel select error interrupt + * INTEN[7:0] - Select channel interrupt + */ + reg = rzg2l_adc_readl(adc, RZG2L_ADINT); + reg &= ~RZG2L_ADINT_INTS; + reg &= ~RZG2L_ADINT_INTEN_MASK; + reg |= (RZG2L_ADINT_CSEEN | BIT(ch)); + rzg2l_adc_writel(adc, RZG2L_ADINT, reg); + + return 0; +} + +static int rzg2l_adc_set_power(struct iio_dev *indio_dev, bool on) +{ + struct device *dev = indio_dev->dev.parent; + + if (on) + return pm_runtime_resume_and_get(dev); + + return pm_runtime_put_sync(dev); +} + +static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch) +{ + int ret; + + ret = rzg2l_adc_set_power(indio_dev, true); + if (ret) + return ret; + + ret = rzg2l_adc_conversion_setup(adc, ch); + if (ret) { + rzg2l_adc_set_power(indio_dev, false); + return ret; + } + + reinit_completion(&adc->completion); + + rzg2l_adc_start_stop(adc, true); + + if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) { + rzg2l_adc_writel(adc, RZG2L_ADINT, + rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK); + rzg2l_adc_start_stop(adc, false); + rzg2l_adc_set_power(indio_dev, false); + return -ETIMEDOUT; + } + + return rzg2l_adc_set_power(indio_dev, false); +} + +static int rzg2l_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct rzg2l_adc *adc = iio_priv(indio_dev); + int ret; + u8 ch; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (chan->type != IIO_VOLTAGE) + return -EINVAL; + + mutex_lock(&adc->lock); + ch = chan->channel & RZG2L_ADC_CHN_MASK; + ret = rzg2l_adc_conversion(indio_dev, adc, ch); + if (ret) { + mutex_unlock(&adc->lock); + return ret; + } + *val = adc->last_val[ch]; + mutex_unlock(&adc->lock); + + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + +static const struct iio_info rzg2l_adc_iio_info = { + .read_raw = rzg2l_adc_read_raw, +}; + +static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id) +{ + struct rzg2l_adc *adc = dev_id; + unsigned long intst; + u32 reg; + int ch; + + reg = rzg2l_adc_readl(adc, RZG2L_ADSTS); + + /* A/D conversion channel select error interrupt */ + if (reg & RZG2L_ADSTS_CSEST) { + rzg2l_adc_writel(adc, RZG2L_ADSTS, reg); + return IRQ_HANDLED; + } + + intst = reg & RZG2L_ADSTS_INTST_MASK; + if (!intst) + return IRQ_NONE; + + for_each_set_bit(ch, &intst, RZG2L_ADC_MAX_CHANNELS) + adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK; + + /* clear the channel interrupt */ + rzg2l_adc_writel(adc, RZG2L_ADSTS, reg); + + complete(&adc->completion); + + return IRQ_HANDLED; +} + +static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc) +{ + struct iio_chan_spec *chan_array; + struct fwnode_handle *fwnode; + struct rzg2l_adc_data *data; + unsigned int channel; + int num_channels; + int ret; + u8 i; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + num_channels = device_get_child_node_count(&pdev->dev); + if (!num_channels) { + dev_err(&pdev->dev, "no channel children\n"); + return -ENODEV; + } + + if (num_channels > RZG2L_ADC_MAX_CHANNELS) { + dev_err(&pdev->dev, "num of channel children out of range\n"); + return -EINVAL; + } + + chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array), + GFP_KERNEL); + if (!chan_array) + return -ENOMEM; + + i = 0; + device_for_each_child_node(&pdev->dev, fwnode) { + ret = fwnode_property_read_u32(fwnode, "reg", &channel); + if (ret) + return ret; + + if (channel >= RZG2L_ADC_MAX_CHANNELS) + return -EINVAL; + + chan_array[i].type = IIO_VOLTAGE; + chan_array[i].indexed = 1; + chan_array[i].channel = channel; + chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW); + chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel]; + i++; + } + + data->num_channels = num_channels; + data->channels = chan_array; + adc->data = data; + + return 0; +} + +static int rzg2l_adc_hw_init(struct rzg2l_adc *adc) +{ + int timeout = 5; + u32 reg; + int ret; + + ret = clk_prepare_enable(adc->pclk); + if (ret) + return ret; + + /* SW reset */ + reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); + reg |= RZG2L_ADM0_SRESB; + rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); + + while (!(rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_SRESB)) { + if (!timeout) { + ret = -EBUSY; + goto exit_hw_init; + } + timeout--; + usleep_range(100, 200); + } + + /* Only division by 4 can be set */ + reg = rzg2l_adc_readl(adc, RZG2L_ADIVC); + reg &= ~RZG2L_ADIVC_DIVADC_MASK; + reg |= RZG2L_ADIVC_DIVADC_4; + rzg2l_adc_writel(adc, RZG2L_ADIVC, reg); + + /* + * Setup AMD3 + * ADIL[31:24] - Should be always set to 0 + * ADCMP[23:16] - Should be always set to 0xe + * ADSMP[15:0] - Set default (0x578) sampling period + */ + reg = rzg2l_adc_readl(adc, RZG2L_ADM(3)); + reg &= ~RZG2L_ADM3_ADIL_MASK; + reg &= ~RZG2L_ADM3_ADCMP_MASK; + reg &= ~RZG2L_ADM3_ADSMP_MASK; + reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFUALT_SAMPLING); + rzg2l_adc_writel(adc, RZG2L_ADM(3), reg); + +exit_hw_init: + clk_disable_unprepare(adc->pclk); + + return 0; +} + +static void rzg2l_adc_pm_runtime_disable(void *data) +{ + struct device *dev = data; + + pm_runtime_disable(dev->parent); +} + +static void rzg2l_adc_pm_runtime_set_suspended(void *data) +{ + struct device *dev = data; + + pm_runtime_set_suspended(dev->parent); +} + +static void rzg2l_adc_reset_assert(void *data) +{ + reset_control_assert(data); +} + +static int rzg2l_adc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct rzg2l_adc *adc; + int ret; + int irq; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc = iio_priv(indio_dev); + + ret = rzg2l_adc_parse_properties(pdev, adc); + if (ret) + return ret; + + mutex_init(&adc->lock); + + adc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(adc->base)) + return PTR_ERR(adc->base); + + adc->pclk = devm_clk_get(dev, "pclk"); + if (IS_ERR(adc->pclk)) { + dev_err(dev, "Failed to get pclk"); + return PTR_ERR(adc->pclk); + } + + adc->adclk = devm_clk_get(dev, "adclk"); + if (IS_ERR(adc->adclk)) { + dev_err(dev, "Failed to get adclk"); + return PTR_ERR(adc->adclk); + } + + adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n"); + if (IS_ERR(adc->adrstn)) { + dev_err(dev, "failed to get adrstn\n"); + return PTR_ERR(adc->adrstn); + } + + adc->presetn = devm_reset_control_get_exclusive(dev, "presetn"); + if (IS_ERR(adc->presetn)) { + dev_err(dev, "failed to get presetn\n"); + return PTR_ERR(adc->presetn); + } + + ret = reset_control_deassert(adc->adrstn); + if (ret) { + dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret); + return ret; + } + + ret = devm_add_action_or_reset(&pdev->dev, + rzg2l_adc_reset_assert, adc->adrstn); + if (ret) { + dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n", + ret); + return ret; + } + + ret = reset_control_deassert(adc->presetn); + if (ret) { + dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret); + return ret; + } + + ret = devm_add_action_or_reset(&pdev->dev, + rzg2l_adc_reset_assert, adc->presetn); + if (ret) { + dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n", + ret); + return ret; + } + + ret = rzg2l_adc_hw_init(adc); + if (ret) { + dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret); + return ret; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "no irq resource\n"); + return irq; + } + + ret = devm_request_irq(dev, irq, rzg2l_adc_isr, + 0, dev_name(dev), adc); + if (ret < 0) + return ret; + + init_completion(&adc->completion); + + platform_set_drvdata(pdev, indio_dev); + + indio_dev->name = DRIVER_NAME; + indio_dev->info = &rzg2l_adc_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = adc->data->channels; + indio_dev->num_channels = adc->data->num_channels; + + pm_runtime_set_suspended(dev); + ret = devm_add_action_or_reset(&pdev->dev, + rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev); + if (ret) + return ret; + + pm_runtime_enable(dev); + ret = devm_add_action_or_reset(&pdev->dev, + rzg2l_adc_pm_runtime_disable, &indio_dev->dev); + if (ret) + return ret; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rzg2l_adc_match[] = { + { .compatible = "renesas,rzg2l-adc",}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg2l_adc_match); + +static int __maybe_unused rzg2l_adc_pm_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct rzg2l_adc *adc = iio_priv(indio_dev); + + rzg2l_adc_pwr(adc, false); + clk_disable_unprepare(adc->adclk); + clk_disable_unprepare(adc->pclk); + + return 0; +} + +static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct rzg2l_adc *adc = iio_priv(indio_dev); + int ret; + + ret = clk_prepare_enable(adc->pclk); + if (ret) + return ret; + + ret = clk_prepare_enable(adc->adclk); + if (ret) + return ret; + + rzg2l_adc_pwr(adc, true); + + return 0; +} + +static const struct dev_pm_ops rzg2l_adc_pm_ops = { + SET_RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend, + rzg2l_adc_pm_runtime_resume, + NULL) +}; + +static struct platform_driver rzg2l_adc_driver = { + .probe = rzg2l_adc_probe, + .driver = { + .name = DRIVER_NAME, + .of_match_table = rzg2l_adc_match, + .pm = &rzg2l_adc_pm_ops, + }, +}; + +module_platform_driver(rzg2l_adc_driver); + +MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); +MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver"); +MODULE_LICENSE("GPL v2"); -- 2.17.1
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[PATCH v2 5.10.y-cip 03/15] dt-bindings: iio: adc: Add binding documentation for Renesas RZ/G2L A/D converter
Lad Prabhakar
commit 08080963162740abdd8a35f6c3aad0e744f71627 upstream.
Add binding documentation for Renesas RZ/G2L A/D converter block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210804202118.25745-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../bindings/iio/adc/renesas,rzg2l-adc.yaml | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml new file mode 100644 index 000000000000..c80201d6a716 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L ADC + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: | + A/D Converter block is a successive approximation analog-to-digital converter + with a 12-bit accuracy. Up to eight analog input channels can be selected. + Conversions can be performed in single or repeat mode. Result of the ADC is + stored in a 32-bit data register corresponding to each channel. + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-adc # RZ/G2{L,LC} + - const: renesas,rzg2l-adc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: converter clock + - description: peripheral clock + + clock-names: + items: + - const: adclk + - const: pclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: presetn + - const: adrst-n + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + - reset-names + +patternProperties: + "^channel@[0-7]$": + $ref: "adc.yaml" + type: object + description: | + Represents the external channels which are connected to the ADC. + + properties: + reg: + description: | + The channel number. It can have up to 8 channels numbered from 0 to 7. + items: + - minimum: 0 + maximum: 7 + + required: + - reg + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + adc: adc@10059000 { + compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; + reg = <0x10059000 0x400>; + interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G044_ADC_PCLK>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_ADC_PRESETN>, + <&cpg R9A07G044_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; -- 2.17.1
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[PATCH v2 5.10.y-cip 01/15] i2c: riic: Add RZ/G2L support
Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 010e765b406f8e08685ea5b687c63a5ea234719a upstream. RZ/G2L i2c controller is compatible with RZ/A i2c controller. By default IP is in reset state, so need to perform release reset before accessing any register. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/i2c/busses/i2c-riic.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 4eccc0f69861..78b84445ee6a 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -42,8 +42,10 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/reset.h> #define RIIC_ICCR1 0x00 #define RIIC_ICCR2 0x04 @@ -86,6 +88,11 @@ #define RIIC_INIT_MSG -1 +enum riic_type { + RIIC_RZ_A, + RIIC_RZ_G2L, +}; + struct riic_dev { void __iomem *base; u8 *buf; @@ -395,7 +402,9 @@ static int riic_i2c_probe(struct platform_device *pdev) struct i2c_adapter *adap; struct resource *res; struct i2c_timings i2c_t; + struct reset_control *rstc; int i, ret; + enum riic_type type; riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL); if (!riic) @@ -412,6 +421,17 @@ static int riic_i2c_probe(struct platform_device *pdev) return PTR_ERR(riic->clk); } + type = (enum riic_type)of_device_get_match_data(&pdev->dev); + if (type == RIIC_RZ_G2L) { + rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(rstc)) { + dev_err(&pdev->dev, "Error: missing reset ctrl\n"); + return PTR_ERR(rstc); + } + + reset_control_deassert(rstc); + } + for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) { res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num); if (!res) @@ -472,7 +492,8 @@ static int riic_i2c_remove(struct platform_device *pdev) } static const struct of_device_id riic_i2c_dt_ids[] = { - { .compatible = "renesas,riic-rz" }, + { .compatible = "renesas,riic-r9a07g044", .data = (void *)RIIC_RZ_G2L }, + { .compatible = "renesas,riic-rz", .data = (void *)RIIC_RZ_A }, { /* Sentinel */ }, }; -- 2.17.1
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[PATCH v2 5.10.y-cip 02/15] arm64: defconfig: Enable RIIC
Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
commit df364a82bf5b2dc2d78212c53205bbb91e40f850 upstream. Enable RIIC driver support for Renesas RZ/G2L based platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210611165624.30749-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index afc696d94c89..349933a08790 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -443,6 +443,7 @@ CONFIG_I2C_PXA=y CONFIG_I2C_QCOM_CCI=m CONFIG_I2C_QCOM_GENI=m CONFIG_I2C_QUP=y +CONFIG_I2C_RIIC=y CONFIG_I2C_RK3X=y CONFIG_I2C_SH_MOBILE=y CONFIG_I2C_TEGRA=y -- 2.17.1
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[PATCH v2 5.10.y-cip 00/15] Add ADC/CANFD/IIC support for RZ/G2L
Lad Prabhakar
Hi All,
This patch series adds Sound and ADC support for Renesas RZ/G2L SoC and enables RIIC/SOUND/CANFD/ADC on Renesas SMARC EVK. I have also included the missing driver patch for riic and kernel configs. All the patches have been cherry picked from v5.16-rc7. I have created a MR [0] for cip-kernel-config to support build testing and can be merged once this patch series is accepted. Note: I have kept the clock related patches for audio as this will avoid conflicts with the later patches. [0] https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/merge_requests/55 Changes for v2: * Dropped sound support v1: https://patchwork.kernel.org/project/cip-dev/cover/ 20211229101530.22783-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Biju Das (5): i2c: riic: Add RZ/G2L support arm64: defconfig: Enable RIIC clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries arm64: dts: renesas: rzg2l-smarc: Enable I2C{0,1,3} support clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical Colin Ian King (1): iio: adc: rzg2l_adc: Fix -EBUSY timeout error return Lad Prabhakar (8): dt-bindings: iio: adc: Add binding documentation for Renesas RZ/G2L A/D converter iio: adc: Add driver for Renesas RZ/G2L A/D converter clk: renesas: r9a07g044: Add clock and reset entries for ADC arm64: dts: renesas: r9a07g044: Add ADC node arm64: defconfig: Enable RZG2L_ADC arm64: dts: renesas: rzg2l-smarc-som: Move extal and memory nodes to SOM DTSI arm64: dts: renesas: rzg2l-smarc-som: Enable ADC on SMARC platform arm64: dts: renesas: rzg2l-smarc: Enable CANFD Yang Yingliang (1): iio: adc: rzg2l_adc: add missing clk_disable_unprepare() in rzg2l_adc_pm_runtime_resume() .../bindings/iio/adc/renesas,rzg2l-adc.yaml | 134 ++++ MAINTAINERS | 8 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 42 ++ .../boot/dts/renesas/r9a07g044l2-smarc.dts | 7 +- .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 35 ++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 83 ++- arch/arm64/configs/defconfig | 2 + drivers/clk/renesas/r9a07g044-cpg.c | 28 + drivers/i2c/busses/i2c-riic.c | 23 +- drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rzg2l_adc.c | 591 ++++++++++++++++++ 12 files changed, 953 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi create mode 100644 drivers/iio/adc/rzg2l_adc.c -- 2.17.1
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Re: [isar-cip-core][PATCH 4/4] enable cip-core-image-kernelci
Jan Kiszka
On 07.01.22 14:40, Alice Ferrazzi wrote:
On Fri, Jan 7, 2022 at 8:18 PM Jan Kiszka <jan.kiszka@siemens.com> wrote:I've sent a patch that removes the superfluous semicolons, you were onyou are right. I just checked my pipeline backlog and found that some CC. Just rebase on top and follow that new pattern. Thanks, Jan -- Siemens AG, Technology Competence Center Embedded Linux
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