Date   

Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Nobuhiro Iwamatsu
 

Hi,

Thanks for your work.

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Wednesday, October 28, 2020 1:56 AM
To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi All,

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both

Cheers,
Prabhakar

Lad Prabhakar (5):
dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
arm64: dts: renesas: r8a774c0: Add PCIe EP node
arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
controllers
I have reviewed this patch series. There seems to be no problem.
I will apply this if there is no other opinion.

Best regards,
Nobuhiro


.../devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++-
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
drivers/misc/pci_endpoint_test.c | 7 +++-
5 files changed, 105 insertions(+), 4 deletions(-)

--
2.17.1


[PATCH 4.19.y-cip 5/5] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers

Lad Prabhakar
 

commit cfb824ddd1c040a7ac65eea3f900f14268e8f383 upstream.

Add Renesas R8A774A1 and R8A774B1 in pci_device_id table so that
pci-epf-test can be used for testing PCIe EP on RZ/G2M and RZ/G2N.

Link: https://lore.kernel.org/r/20200814173037.17822-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/misc/pci_endpoint_test.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index aff8cbca5d18..a1083f568d2c 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -80,6 +80,8 @@
#define is_am654_pci_dev(pdev) \
((pdev)->device == PCI_DEVICE_ID_TI_AM654)

+#define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
+#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d

static DEFINE_IDA(pci_endpoint_test_ida);
@@ -816,8 +818,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
.driver_data = (kernel_ulong_t)&am654_data
},
- { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
- },
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
--
2.17.1


[PATCH 4.19.y-cip 4/5] arm64: dts: renesas: r8a774b1: Add PCIe EP nodes

Lad Prabhakar
 

commit d12d16205f7993da195002eea24b7467deb9ac8c upstream.

Add PCIe EP nodes to R8A774B1 (RZ/G2N) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 11cc0f274ef3..0e5bfaeda983 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1984,6 +1984,44 @@
status = "disabled";
};

+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774b1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774b1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
--
2.17.1


[PATCH 4.19.y-cip 3/5] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes

Lad Prabhakar
 

commit 578450883bb1ff878ac8e3d38060802b222adcbe upstream.

Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 16166f3b66a0..90f5fb49957e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2115,6 +2115,44 @@
status = "disabled";
};

+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774a1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774a1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
--
2.17.1


[PATCH 4.19.y-cip 2/5] arm64: dts: renesas: r8a774c0: Add PCIe EP node

Lad Prabhakar
 

commit 0c77ecdcfcd35e97c677e49a8516a0b10c1e8fb7 upstream.

Add PCIe EP node to R8A774C0 (RZ/G2E) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 7ba934c32696..44d66fcb412d 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1698,6 +1698,25 @@
status = "disabled";
};

+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774c0-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
vspb0: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
--
2.17.1


[PATCH 4.19.y-cip 1/5] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1

Lad Prabhakar
 

commit 2de82ec8667465236e15f8c6af7cecf8da63fc60 upstream.

Document the support for R-Car PCIe EP on R8A774A1 and R8A774B1 SoC
devices.

Also constify "renesas,rcar-gen3-pcie-ep" so that it can be used as
fallback compatible string for R-Car Gen3 and RZ/G2 devices as the
PCIe module is identical.

Link: https://lore.kernel.org/r/20200814173037.17822-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
index aa483c7f27fd..70c45f72ab20 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
@@ -14,8 +14,11 @@ maintainers:
properties:
compatible:
items:
- - const: renesas,r8a774c0-pcie-ep
- - const: renesas,rcar-gen3-pcie-ep
+ - enum:
+ - renesas,r8a774a1-pcie-ep # RZ/G2M
+ - renesas,r8a774b1-pcie-ep # RZ/G2N
+ - renesas,r8a774c0-pcie-ep # RZ/G2E
+ - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2

reg:
maxItems: 5
--
2.17.1


[PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Lad Prabhakar
 

Hi All,

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both

Cheers,
Prabhakar

Lad Prabhakar (5):
dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
arm64: dts: renesas: r8a774c0: Add PCIe EP node
arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
controllers

.../devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++-
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
drivers/misc/pci_endpoint_test.c | 7 +++-
5 files changed, 105 insertions(+), 4 deletions(-)

--
2.17.1


Re: Direct Pushes for cip-kernel-sec

Ben Hutchings <ben.hutchings@...>
 

On Tue, 2020-10-27 at 14:49 +0800, Chen-Yu Tsai wrote:
On Fri, Oct 23, 2020 at 1:27 AM Ben Hutchings
<ben.hutchings@codethink.co.uk> wrote:
On Thu, 2020-10-22 at 18:00 +0800, Chen-Yu Tsai wrote:
Hi,

After today's CIP weekly meeting, Pavel proposed the idea of skipping
merge requests for the cip-kernel-sec repository:
[...]
Ben, could you share your thoughts on this?
I was going to suggest you do that, for other reasons. I didn't
realise you weren't able to do so. It looks you have been granted that
permission now, is that right?
Yes. So in the future I'll push all script-imported updates directly.
Would you still like to review manual data input, or should I push those
directly as well?
Please push them directly.

Ben.

--
Ben Hutchings, Software Developer Codethink Ltd
https://www.codethink.co.uk/ Dale House, 35 Dale Street
Manchester, M1 2HF, United Kingdom


Re: Direct Pushes for cip-kernel-sec

Chen-Yu Tsai (Moxa) <wens@...>
 

On Fri, Oct 23, 2020 at 1:27 AM Ben Hutchings
<ben.hutchings@codethink.co.uk> wrote:

On Thu, 2020-10-22 at 18:00 +0800, Chen-Yu Tsai wrote:
Hi,

After today's CIP weekly meeting, Pavel proposed the idea of skipping
merge requests for the cip-kernel-sec repository:
[...]
Ben, could you share your thoughts on this?
I was going to suggest you do that, for other reasons. I didn't
realise you weren't able to do so. It looks you have been granted that
permission now, is that right?
Yes. So in the future I'll push all script-imported updates directly.
Would you still like to review manual data input, or should I push those
directly as well?

ChenYu


[ANNOUNCE] Release v4.19.152-cip37

Nobuhiro Iwamatsu
 

Hi,

CIP kernel team has released Linux kernel v4.19.152-cip37.
The linux-4.19.y-cip tree has been updated base version from v4.19.150
to v4.19.152. And this release adds PCI-E driver support for Renesas RZ/G2.

You can get this release via the git tree at:

v4.19.152-cip37:
repository:
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git
branch:
linux-4.19.y-cip
commit hash:
6dbf6c14540a8a35584b4414d02f3e08294c6c36
added commits:
CIP: Bump version suffix to -cip37 after merge from stable
misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller
arm64: defconfig: Enable R-Car PCIe endpoint driver
PCI: rcar: Add endpoint mode support
dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller
PCI: rcar: Fix calculating mask for PCIEPAMR register
PCI: rcar: Move shareable code to a common file
arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST
PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c
PCI: endpoint: functions/pci-epf-test: Print throughput information
PCI: endpoint: Add support to handle multiple base for mapping outbound memory
PCI: endpoint: Pass page size as argument to pci_epc_mem_init()
PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
PCI: pci-epf-test: Add support to defer core initialization
PCI: endpoint: Add notification for core init completion
PCI: endpoint: Add core init notifying feature
PCI: endpoint: Assign function number for each PF in EPC core
PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex
PCI: endpoint: Replace spinlock with mutex
PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF
tools: PCI: Fix fd leakage
tools: PCI: Exit with error code when test fails
PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address
PCI: endpoint: Fix clearing start entry in configfs
PCI: endpoint: Cast the page number to phys_addr_t
PCI: endpoint: Clear BAR before freeing its space
PCI: endpoint: Skip odd BAR when skipping 64bit BAR
PCI: endpoint: Allocate enough space for fixed size BAR
PCI: endpoint: Set endpoint controller pointer to NULL
PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
PCI: endpoint: Fix a potential NULL pointer dereference
PCI: endpoint: Remove features member in struct pci_epc
PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
PCI: pci-epf-test: Remove setting epf_bar flags in function driver
PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
PCI: endpoint: Add helper to get first unreserved BAR
PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
PCI: endpoint: Add new pci_epc_ops to get EPC features

Best regards,
Nobuhiro


Re: [PATCH 4.19.y-cip 4/6] PCI: rcar: Add endpoint mode support

Pavel Machek
 

Hi!

+ pm_runtime_enable(dev);
+ err = pm_runtime_get_sync(dev);
+ if (err < 0) {
+ dev_err(dev, "pm_runtime_get_sync failed\n");
+ goto err_pm_disable;
+ }
I believe this should go to pm_put.
Agreed pm_runtime_get_sync() increments the runtime PM usage counter even when it fails. I'll fix this in upstream first and then backport.
Thank you. This one is worth backporting, I don't believe we need the
other cleanups in -cip.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 1/6] PCI: rcar: Move shareable code to a common file

Pavel Machek
 

Hi!

+int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
+{
+ unsigned int timeout = 10000;
+
+ while (timeout--) {
+ if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
+ return 0;
+
+ udelay(5);
+ cpu_relax();
+ }
+
+ return -ETIMEDOUT;
+}
This has same problem. Plus, I don't believe cpu_relax() is good idea
there. Relaxing CPU every 5usec will not change anything.
Agreed (as above). wrt cpu_relax() I believe this was added to improve the performance of other HW threads.
Yes, but you'd need to call it in a loop. It will be effective if done
inside udelay(), but not like this.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 4/6] PCI: rcar: Add endpoint mode support

Lad Prabhakar
 

Hi Pavel,

Thank you for the review.

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 23 October 2020 20:42
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 4/6] PCI: rcar: Add endpoint mode support

Hi!


Add support for R-Car PCIe controller to work in endpoint mode.
+static int rcar_pcie_ep_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_pcie_endpoint *ep;
+ struct rcar_pcie *pcie;
+ struct pci_epc *epc;
+ int err;
+
+ ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
+ if (!ep)
+ return -ENOMEM;
+
+ pcie = &ep->pcie;
+ pcie->dev = dev;
+
+ pm_runtime_enable(dev);
+ err = pm_runtime_get_sync(dev);
+ if (err < 0) {
+ dev_err(dev, "pm_runtime_get_sync failed\n");
+ goto err_pm_disable;
+ }
I believe this should go to pm_put.
Agreed pm_runtime_get_sync() increments the runtime PM usage counter even when it fails. I'll fix this in upstream first and then backport.

Cheers,
Prabhakar

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 1/6] PCI: rcar: Move shareable code to a common file

Lad Prabhakar
 

Hi Pavel,

Thank you for the review.

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 23 October 2020 20:41
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 1/6] PCI: rcar: Move shareable code to a common file

Hi!

Move shareable code to common file pcie-rcar.c and the #defines to
pcie-rcar.h so that the common code can be reused with endpoint driver.
There are no functional changes with this patch for the host controller
driver.
I have merged the patches, but this should be cleaned up IMO...

+int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
+{
+ unsigned int timeout = 10;
+
+ while (timeout--) {
+ if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
+ return 0;
+
+ msleep(5);
+ }
+
+ return -ETIMEDOUT;
Kind of fun. We test the PHYRDY, not ready, so we wait (now phy
becomes ready).. and we time out.

What about

while (1) {
if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
return 0;
timeout--;
if (!timeout)
return -ETIMEDOUT;
msleep(5);
}

?
Agreed, Ill get this upstream first and then backport.

+int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
+{
+ unsigned int timeout = 10000;
+
+ while (timeout--) {
+ if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
+ return 0;
+
+ udelay(5);
+ cpu_relax();
+ }
+
+ return -ETIMEDOUT;
+}
This has same problem. Plus, I don't believe cpu_relax() is good idea
there. Relaxing CPU every 5usec will not change anything.
Agreed (as above). wrt cpu_relax() I believe this was added to improve the performance of other HW threads.

Cheers,
Prabhakar

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/6] Add PCIe EP driver to Renesas R-Car Gen3 and RZ/G2x

Lad Prabhakar
 

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 23 October 2020 20:37
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/6] Add PCIe EP driver to Renesas R-Car Gen3 and RZ/G2x

Hi!

This patch series is part of RFC series [1] ("Add PCIe EP support for
Renesas R-Car Gen3 and RZ/G2x").

* Patches 38-42 and 47 from the RFC are included in this series.
* Patch 1/6 (== 38/50) now have changes to pcie-rcar-host.c driver which
were dropped earlier in RFC series as per suggestion from Pavel.
* Rest of the patches are unchanged
* I have dropped patches 43-46 and 48 from the RFC series and will re-send
them once it hits the -rc (currently they are present in -next)
Thanks, patches look good and CIP testing did not find any problems,
so I applied them and pushed out.
Thank you.

I'll have some additional comments, but those can be solved
post-merge.
Ill get it sorted.

Cheers,
Prabhakar

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 4/6] PCI: rcar: Add endpoint mode support

Pavel Machek
 

Hi!


Add support for R-Car PCIe controller to work in endpoint mode.
+static int rcar_pcie_ep_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_pcie_endpoint *ep;
+ struct rcar_pcie *pcie;
+ struct pci_epc *epc;
+ int err;
+
+ ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
+ if (!ep)
+ return -ENOMEM;
+
+ pcie = &ep->pcie;
+ pcie->dev = dev;
+
+ pm_runtime_enable(dev);
+ err = pm_runtime_get_sync(dev);
+ if (err < 0) {
+ dev_err(dev, "pm_runtime_get_sync failed\n");
+ goto err_pm_disable;
+ }
I believe this should go to pm_put.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 1/6] PCI: rcar: Move shareable code to a common file

Pavel Machek
 

Hi!

Move shareable code to common file pcie-rcar.c and the #defines to
pcie-rcar.h so that the common code can be reused with endpoint driver.
There are no functional changes with this patch for the host controller
driver.
I have merged the patches, but this should be cleaned up IMO...

+int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
+{
+ unsigned int timeout = 10;
+
+ while (timeout--) {
+ if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
+ return 0;
+
+ msleep(5);
+ }
+
+ return -ETIMEDOUT;
Kind of fun. We test the PHYRDY, not ready, so we wait (now phy
becomes ready).. and we time out.

What about

while (1) {
if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
return 0;
timeout--;
if (!timeout)
return -ETIMEDOUT;
msleep(5);
}

?

+int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
+{
+ unsigned int timeout = 10000;
+
+ while (timeout--) {
+ if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
+ return 0;
+
+ udelay(5);
+ cpu_relax();
+ }
+
+ return -ETIMEDOUT;
+}
This has same problem. Plus, I don't believe cpu_relax() is good idea
there. Relaxing CPU every 5usec will not change anything.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/6] Add PCIe EP driver to Renesas R-Car Gen3 and RZ/G2x

Pavel Machek
 

Hi!

This patch series is part of RFC series [1] ("Add PCIe EP support for
Renesas R-Car Gen3 and RZ/G2x").

* Patches 38-42 and 47 from the RFC are included in this series.
* Patch 1/6 (== 38/50) now have changes to pcie-rcar-host.c driver which
were dropped earlier in RFC series as per suggestion from Pavel.
* Rest of the patches are unchanged
* I have dropped patches 43-46 and 48 from the RFC series and will re-send
them once it hits the -rc (currently they are present in -next)
Thanks, patches look good and CIP testing did not find any problems,
so I applied them and pushed out.

I'll have some additional comments, but those can be solved
post-merge.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


[PATCH 4.19.y-cip 6/6] misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller

Lad Prabhakar
 

commit b03025c57396b23fe2423384c25aa580000e9883 upstream.

Add Renesas R8A774C0 in pci_device_id table so that pci-epf-test can be
used for testing PCIe EP on RZ/G2E.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1589493809-2602-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/misc/pci_endpoint_test.c | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 7d166f57f624..aff8cbca5d18 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -80,6 +80,8 @@
#define is_am654_pci_dev(pdev) \
((pdev)->device == PCI_DEVICE_ID_TI_AM654)

+#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
+
static DEFINE_IDA(pci_endpoint_test_ida);

#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
@@ -814,6 +816,8 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
.driver_data = (kernel_ulong_t)&am654_data
},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
+ },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
--
2.17.1


[PATCH 4.19.y-cip 5/6] arm64: defconfig: Enable R-Car PCIe endpoint driver

Lad Prabhakar
 

commit cd8bc7d4eb6608afe78ac51422ef94b7824f1646 upstream.

Enable R-Car PCIe endpoint driver on RZ/G2E board, including enabling
endpoint configurations CONFIG_PCI_ENDPOINT, CONFIG_PCI_ENDPOINT_CONFIGFS,
CONFIG_PCI_EPF_TEST and CONFIG_PCI_ENDPOINT_TEST required to use and test
the driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200811140357.564-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes to defconfig file]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ace1b58f3ff5..c8cc683d6e97 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -78,6 +78,7 @@ CONFIG_HOTPLUG_PCI_ACPI=y
CONFIG_PCI_AARDVARK=y
CONFIG_PCI_TEGRA=y
CONFIG_PCIE_RCAR_HOST=y
+CONFIG_PCIE_RCAR_EP=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_XGENE=y
CONFIG_PCI_HOST_THUNDER_PEM=y
@@ -88,6 +89,9 @@ CONFIG_PCI_HISI=y
CONFIG_PCIE_QCOM=y
CONFIG_PCIE_ARMADA_8K=y
CONFIG_PCIE_KIRIN=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=m
CONFIG_PCIE_HISI_STB=y
CONFIG_ARM64_VA_BITS_48=y
CONFIG_SCHED_MC=y
@@ -194,6 +198,7 @@ CONFIG_BLK_DEV_NBD=m
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_NVME=m
CONFIG_SRAM=y
+CONFIG_PCI_ENDPOINT_TEST=m
CONFIG_EEPROM_AT25=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
--
2.17.1

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