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[PATCH 5.10.y-cip 25/29] dt-bindings: thermal: Document Renesas RZ/G2L TSU
From: Biju Das <biju.das.jz@...> commit 9460347192add5644236d492f79ecab6d83504d4 upstream. Document the Thermal Sensor Unit(TSU) in the RZ/G2L SoC. Signed-off-by: Biju Das <biju.das.jz@...
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From: Biju Das <biju.das.jz@...> commit 9460347192add5644236d492f79ecab6d83504d4 upstream. Document the Thermal Sensor Unit(TSU) in the RZ/G2L SoC. Signed-off-by: Biju Das <biju.das.jz@...
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By
Lad Prabhakar
· #7988
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[PATCH 5.10.y-cip 24/29] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
From: Biju Das <biju.das.jz@...> commit 86e122c0754951094a3857870ad9f4022e056f6b upstream. Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU frequency. Define CPG_PL1_DDIV, so
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From: Biju Das <biju.das.jz@...> commit 86e122c0754951094a3857870ad9f4022e056f6b upstream. Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU frequency. Define CPG_PL1_DDIV, so
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By
Lad Prabhakar
· #7987
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[PATCH 5.10.y-cip 23/29] clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
From: Biju Das <biju.das.jz@...> commit 98ee8b2f66ebff2fafe85668b9d00c3433b76566 upstream. Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree mentioned in the hardware
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From: Biju Das <biju.das.jz@...> commit 98ee8b2f66ebff2fafe85668b9d00c3433b76566 upstream. Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree mentioned in the hardware
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By
Lad Prabhakar
· #7986
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[PATCH 5.10.y-cip 22/29] clk: renesas: r9a07g044: Add TSU clock and reset entry
From: Biju Das <biju.das.jz@...> commit 33b22d9c3272003a525ba2d6b7b851f3d4f30574 upstream. Add TSU clock and reset entry to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...>
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From: Biju Das <biju.das.jz@...> commit 33b22d9c3272003a525ba2d6b7b851f3d4f30574 upstream. Add TSU clock and reset entry to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...>
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By
Lad Prabhakar
· #7985
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[PATCH 5.10.y-cip 21/29] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
From: Biju Das <biju.das.jz@...> commit d6dabaf678971733da56b2e84793348f714d42ff upstream. Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual Rev.1.00. This patch adds clo
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From: Biju Das <biju.das.jz@...> commit d6dabaf678971733da56b2e84793348f714d42ff upstream. Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual Rev.1.00. This patch adds clo
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By
Lad Prabhakar
· #7984
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[PATCH 5.10.y-cip 20/29] arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog
From: Biju Das <biju.das.jz@...> commit 44c2d2c2d25e87741b84aaa9e0dad396abdd148d upstream. Enable watchdog{0, 1, 2} interfaces on RZ/G2L SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@...
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From: Biju Das <biju.das.jz@...> commit 44c2d2c2d25e87741b84aaa9e0dad396abdd148d upstream. Enable watchdog{0, 1, 2} interfaces on RZ/G2L SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@...
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By
Lad Prabhakar
· #7983
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[PATCH 5.10.y-cip 19/29] arm64: dts: renesas: r9a07g044: Add WDT nodes
From: Biju Das <biju.das.jz@...> commit eb7621ce3362639025e7db125559e235a76d814f upstream. Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Re
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From: Biju Das <biju.das.jz@...> commit eb7621ce3362639025e7db125559e235a76d814f upstream. Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Re
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By
Lad Prabhakar
· #7982
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[PATCH 5.10.y-cip 18/29] arm64: dts: renesas: rzg2l-smarc-som: Enable OSTM
From: Biju Das <biju.das.jz@...> commit 00d071e23c61b1be528227427da3f805feddef19 upstream. Enable OSTM{1, 2} interfaces on RZ/G2L SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju
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From: Biju Das <biju.das.jz@...> commit 00d071e23c61b1be528227427da3f805feddef19 upstream. Enable OSTM{1, 2} interfaces on RZ/G2L SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju
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By
Lad Prabhakar
· #7981
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[PATCH 5.10.y-cip 17/29] arm64: dts: renesas: r9a07g044: Add OSTM nodes
From: Biju Das <biju.das.jz@...> commit 59a7d68b69846ac012c33c1ac425b9388661d1f2 upstream. Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Rev
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From: Biju Das <biju.das.jz@...> commit 59a7d68b69846ac012c33c1ac425b9388661d1f2 upstream. Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Rev
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By
Lad Prabhakar
· #7980
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[PATCH 5.10.y-cip 16/29] clocksource/drivers/renesas,ostm: Make RENESAS_OSTM symbol visible
From: Biju Das <biju.das.jz@...> commit a2807f657976b943bf0eb81d026398d28aa89863 upstream. As RZ/G2L uses the ARM Architected Timer as system timer, enabling the OSTM is not mandatory. Make
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From: Biju Das <biju.das.jz@...> commit a2807f657976b943bf0eb81d026398d28aa89863 upstream. As RZ/G2L uses the ARM Architected Timer as system timer, enabling the OSTM is not mandatory. Make
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By
Lad Prabhakar
· #7979
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[PATCH 5.10.y-cip 15/29] clocksource/drivers/renesas-ostm: Add RZ/G2L OSTM support
From: Biju Das <biju.das.jz@...> commit 3a3e9f23c2cae907677a236fa547610ca747e6fb upstream. RZ/G2L SoC has Generic Timer Module(a.k.a OSTM) which needs to deassert the reset line before acce
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From: Biju Das <biju.das.jz@...> commit 3a3e9f23c2cae907677a236fa547610ca747e6fb upstream. RZ/G2L SoC has Generic Timer Module(a.k.a OSTM) which needs to deassert the reset line before acce
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By
Lad Prabhakar
· #7978
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[PATCH 5.10.y-cip 14/29] reset: Add of_reset_control_get_optional_exclusive()
From: Biju Das <biju.das.jz@...> commit c4f5b30dda01f2f6979a9681142de454991182ee upstream. Add optional variant of of_reset_control_get_exclusive(). If the requested reset is not specified
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From: Biju Das <biju.das.jz@...> commit c4f5b30dda01f2f6979a9681142de454991182ee upstream. Add optional variant of of_reset_control_get_exclusive(). If the requested reset is not specified
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By
Lad Prabhakar
· #7977
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[PATCH 5.10.y-cip 13/29] dt-bindings: timer: renesas: ostm: Document Renesas RZ/G2L OSTM
From: Biju Das <biju.das.jz@...> commit 92d06a3f67ad809649d26aa7698e4d42362585a8 upstream. Document the General Timer Module(a.k.a OSTM) found on the RZ/G2L SoC. Signed-off-by: Biju Das <bi
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From: Biju Das <biju.das.jz@...> commit 92d06a3f67ad809649d26aa7698e4d42362585a8 upstream. Document the General Timer Module(a.k.a OSTM) found on the RZ/G2L SoC. Signed-off-by: Biju Das <bi
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By
Lad Prabhakar
· #7976
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[PATCH 5.10.y-cip 12/29] clk: renesas: r9a07g044: Add OSTM clock and reset entries
From: Biju Das <biju.das.jz@...> commit 161450134ae9bab3778c5f5732941162626d0eaa upstream. Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...
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From: Biju Das <biju.das.jz@...> commit 161450134ae9bab3778c5f5732941162626d0eaa upstream. Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...
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By
Lad Prabhakar
· #7975
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[PATCH 5.10.y-cip 11/29] watchdog: Add Watchdog Timer driver for RZ/G2L
From: Biju Das <biju.das.jz@...> commit 2cbc5cd0b55fa2310cc557c77b0665f5e00272de upstream. Add Watchdog Timer driver for RZ/G2L SoC. WDT IP block supports normal watchdog timer function and
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From: Biju Das <biju.das.jz@...> commit 2cbc5cd0b55fa2310cc557c77b0665f5e00272de upstream. Add Watchdog Timer driver for RZ/G2L SoC. WDT IP block supports normal watchdog timer function and
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By
Lad Prabhakar
· #7974
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[PATCH 5.10.y-cip 10/29] units: Add SI metric prefix definitions
From: Andy Shevchenko <andriy.shevchenko@...> commit 26471d4a6cf8d5d0bd0fb55c7169de7d67cc703a upstream. Sometimes it's useful to have well-defined SI metric prefix to be used to self-descr
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From: Andy Shevchenko <andriy.shevchenko@...> commit 26471d4a6cf8d5d0bd0fb55c7169de7d67cc703a upstream. Sometimes it's useful to have well-defined SI metric prefix to be used to self-descr
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By
Lad Prabhakar
· #7973
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[PATCH 5.10.y-cip 09/29] dt-bindings: watchdog: renesas,wdt: Add support for RZ/G2L
From: Biju Das <biju.das.jz@...> commit ab02a00c9e32a5eb1525689b990ad9d345f0832e upstream. Describe the WDT hardware in the RZ/G2L series. Signed-off-by: Biju Das <biju.das.jz@...
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From: Biju Das <biju.das.jz@...> commit ab02a00c9e32a5eb1525689b990ad9d345f0832e upstream. Describe the WDT hardware in the RZ/G2L series. Signed-off-by: Biju Das <biju.das.jz@...
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By
Lad Prabhakar
· #7972
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[PATCH 5.10.y-cip 08/29] clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros
From: Biju Das <biju.das.jz@...> commit dc446cba4301bbe2dbe16711091635d987626410 upstream. Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match th
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From: Biju Das <biju.das.jz@...> commit dc446cba4301bbe2dbe16711091635d987626410 upstream. Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match th
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By
Lad Prabhakar
· #7971
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[PATCH 5.10.y-cip 07/29] clk: renesas: r9a07g044: Add WDT clock and reset entries
From: Biju Das <biju.das.jz@...> commit 073da9e7c768b0d81f9ce22cc907227450612d88 upstream. Add WDT{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...
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From: Biju Das <biju.das.jz@...> commit 073da9e7c768b0d81f9ce22cc907227450612d88 upstream. Add WDT{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...
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By
Lad Prabhakar
· #7970
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[PATCH 5.10.y-cip 06/29] arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board
commit 7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2 upstream. RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board d
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commit 7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2 upstream. RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board d
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By
Lad Prabhakar
· #7969
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