[PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree


Biju Das <biju.das@...>
 

The initial r8A7743 SoC device tree including CPU0, GIC and timer.

Signed-off-by: Biju Das <biju.das@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7743.dtsi

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
new file mode 100644
index 0000000..8575a2f
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Device Tree Source for the r8a7743 SoC
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "renesas,r8a7743";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ };
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
1.9.1


Ben Hutchings <ben.hutchings@...>
 

On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
The initial r8A7743 SoC device tree including CPU0, GIC and timer.

Signed-off-by: Biju Das <biju.das@...>
I compared this to the upstream version (commit
34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand why
the clocks are described differently, but can you explain why there's no
soc node?

Ben.

---
arch/arm/boot/dts/r8a7743.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7743.dtsi

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
new file mode 100644
index 0000000..8575a2f
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Device Tree Source for the r8a7743 SoC
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "renesas,r8a7743";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ };
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
Ben Hutchings
Software Developer, Codethink Ltd.


Biju Das <biju.das@...>
 

-----Original Message-----
From: Ben Hutchings [mailto:ben.hutchings@...]
Sent: 22 August 2017 19:08
To: Biju Das <biju.das@...>
Cc: Chris Paterson <Chris.Paterson2@...>; cip-dev@...
project.org
Subject: Re: [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree

On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
The initial r8A7743 SoC device tree including CPU0, GIC and timer.

Signed-off-by: Biju Das <biju.das@...>
I compared this to the upstream version (commit
34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand why
the clocks are described differently, but can you explain why there's no soc
node?
Thanks for the comments.

RZ/G1M(r8a7743) and R-Car M2(r8a7791) are almost identical. To make consistant
with other R-Car Gen2 dtsi patches on 4.4 kernel version, I have dropped the soc node.

Do you see any issues with this approach?

Ben.

---
arch/arm/boot/dts/r8a7743.dtsi | 56
++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7743.dtsi

diff --git a/arch/arm/boot/dts/r8a7743.dtsi
b/arch/arm/boot/dts/r8a7743.dtsi new file mode 100644 index
0000000..8575a2f
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Device Tree Source for the r8a7743 SoC
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public
+License
+ * version 2. This program is licensed "as is" without any warranty
+of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+compatible = "renesas,r8a7743";
+interrupt-parent = <&gic>;
+#address-cells = <2>;
+#size-cells = <2>;
+
+cpus {
+#address-cells = <1>;
+#size-cells = <0>;
+
+cpu0: cpu@0 {
+device_type = "cpu";
+compatible = "arm,cortex-a15";
+reg = <0>;
+clock-frequency = <1500000000>;
+};
+};
+
+gic: interrupt-controller@f1001000 {
+compatible = "arm,gic-400";
+#interrupt-cells = <3>;
+#address-cells = <0>;
+interrupt-controller;
+reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+};
+
+timer {
+compatible = "arm,armv7-timer";
+interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <1 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+};
+};
--
Ben Hutchings
Software Developer, Codethink Ltd.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.


Ben Hutchings <ben.hutchings@...>
 

On Wed, 2017-08-23 at 07:36 +0000, Biju Das wrote:


-----Original Message-----
From: Ben Hutchings [mailto:ben.hutchings@...]
Sent: 22 August 2017 19:08
To: Biju Das <biju.das@...>
Cc: Chris Paterson <Chris.Paterson2@...>; cip-dev@...
project.org
Subject: Re: [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree

On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
The initial r8A7743 SoC device tree including CPU0, GIC and timer.

Signed-off-by: Biju Das <biju.das@...>
I compared this to the upstream version (commit
34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand why
the clocks are described differently, but can you explain why there's no soc
node?
Thanks for the comments.

RZ/G1M(r8a7743) and R-Car M2(r8a7791) are almost identical. To make consistant
with other R-Car Gen2 dtsi patches on 4.4 kernel version, I have dropped the soc node.
But in the upstream device tree sources, r8a7743.dtsi has an soc node
and r8a7791.dtsi does not. If it's OK for the two chips to be described
differently upstream, I don't see why they should be described
consistently here.

Do you see any issues with this approach?
[...]

I think that consistency with upstream is more important than
consistency within the platform. (Of course, the kernel and FDT need to
actually *work*, and if introducing the soc node gets in the way of that
then we shouldn't do it.)

Ben.

--
Ben Hutchings
Software Developer, Codethink Ltd.


Biju Das <biju.das@...>
 

-----Original Message-----
From: Ben Hutchings [mailto:ben.hutchings@...]
Sent: 25 August 2017 16:41
To: Biju Das <biju.das@...>
Cc: Chris Paterson <Chris.Paterson2@...>; cip-dev@...
project.org
Subject: Re: [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree

On Wed, 2017-08-23 at 07:36 +0000, Biju Das wrote:


-----Original Message-----
From: Ben Hutchings [mailto:ben.hutchings@...]
Sent: 22 August 2017 19:08
To: Biju Das <biju.das@...>
Cc: Chris Paterson <Chris.Paterson2@...>; cip-dev@...
project.org
Subject: Re: [PATCH 01/14] ARM: dts: r8a7743: initial SoC device
tree

On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
The initial r8A7743 SoC device tree including CPU0, GIC and timer.

Signed-off-by: Biju Das <biju.das@...>
I compared this to the upstream version (commit
34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand
why the clocks are described differently, but can you explain why
there's no soc node?
Thanks for the comments.

RZ/G1M(r8a7743) and R-Car M2(r8a7791) are almost identical. To make
consistant with other R-Car Gen2 dtsi patches on 4.4 kernel version, I have
dropped the soc node.

But in the upstream device tree sources, r8a7743.dtsi has an soc node and
r8a7791.dtsi does not. If it's OK for the two chips to be described differently
upstream, I don't see why they should be described consistently here.

Do you see any issues with this approach?
[...]

I think that consistency with upstream is more important than consistency
within the platform. (Of course, the kernel and FDT need to actually *work*,
and if introducing the soc node gets in the way of that then we shouldn't do it.)
OK. I will investigate this and let you know.

Ben.

--
Ben Hutchings
Software Developer, Codethink Ltd.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.