Hi All,

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec
(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded devices
with video capabilities.

Patches add support for the following:
* Documentation for RZ/G2{L,LC,UL} SoC variants
* Documentation for Renesas SMARC EVK
* SYSC binding doc required for SoC identification
* SoC identification support
* Enabling ARCH_R9A07G044 in defconfig

All the patches have been cherry picked from v5.16-rc5

[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rzg2l-general-purpose-microprocessors-dual-
core-arm-cortex-a55-12-ghz-cpus-3d-graphics-and-video-codec
[1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rtk9744l23s01000be-rzg2l-evaluation-board-kit

Cheers,
Prabhakar


Lad Prabhakar (7):
dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC
dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants
dt-bindings: arm: renesas: Document SMARC EVK
dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation
for SYSC controller
soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's
soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC}
SoC's
arm64: defconfig: Enable ARCH_R9A07G044

.../devicetree/bindings/arm/renesas.yaml | 18 ++++++
.../bindings/power/renesas,rzg2l-sysc.yaml | 63 +++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/soc/renesas/Kconfig | 5 ++
drivers/soc/renesas/renesas-soc.c | 33 +++++++++-
5 files changed, 119 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml

--
2.17.1

Hi!

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec
(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded devices
with video capabilities.

I have reviewed patches and they look okay to me. I'll proceed with
testing.

Do we have suitable board in the test lab / is there plan to add one?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Hi Pavel,

Hello Pavel,

From: cip-dev@... <cip-dev@...> On
Behalf Of Pavel Machek via lists.cip-project.org
Sent: 15 December 2021 10:06

Hi!

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video

codec

(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded

devices

with video capabilities.

I have reviewed patches and they look okay to me. I'll proceed with
testing.

Do we have suitable board in the test lab / is there plan to add one?

We don't have any boards in the CIP labs yet, but there is a plan to add some.

Kind regards, Chris

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Hi all,

I have reviewed patches and they look okay to me. I'll proceed with
testing.

Do we have suitable board in the test lab / is there plan to add one?

We don't have any boards in the CIP labs yet, but there is a plan to add some.

I think I need to add the board to LAB first. Of course, source code reviews and
build tests are possible.
And If my understand is correctoly, I think this is a new board that is not on the
reference board list. I don't think this has been discussed at TSC.
I think it needs to be on the agenda at TSC, whether it's a reference board for the 5.10-cip kernel.

Best regards,
Nobuhiro

Best regards,
Nobuhiro

________________________________________
差出人: Chris Paterson <Chris.Paterson2@...>
送信日時: 2021年12月15日 19:34
宛先: cip-dev@...; Prabhakar Mahadev Lad
CC: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ); Pavel Machek; Biju Das
件名: RE: [cip-dev] [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK

Hello Pavel,

From: cip-dev@... <cip-dev@...> On
Behalf Of Pavel Machek via lists.cip-project.org
Sent: 15 December 2021 10:06

Hi!

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video

codec

(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded

devices

with video capabilities.

I have reviewed patches and they look okay to me. I'll proceed with
testing.

Do we have suitable board in the test lab / is there plan to add one?

We don't have any boards in the CIP labs yet, but there is a plan to add some.

Kind regards, Chris

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Hi!

Hi All,

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec
(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded devices
with video capabilities.

Patches add support for the following:
* Documentation for RZ/G2{L,LC,UL} SoC variants
* Documentation for Renesas SMARC EVK
* SYSC binding doc required for SoC identification
* SoC identification support
* Enabling ARCH_R9A07G044 in defconfig

All the patches have been cherry picked from v5.16-rc5

[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rzg2l-general-purpose-microprocessors-dual-
core-arm-cortex-a55-12-ghz-cpus-3d-graphics-and-video-codec
[1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rtk9744l23s01000be-rzg2l-evaluation-board-kit

LGTM. I can merge this seriese, If there is no objection.

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>

Best regards,
Nobuhiro



________________________________________
差出人: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
送信日時: 2021年12月15日 9:46
宛先: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ); Pavel Machek
CC: Biju Das; Lad Prabhakar
件名: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK

Hi All,

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec
(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded devices
with video capabilities.

Patches add support for the following:
* Documentation for RZ/G2{L,LC,UL} SoC variants
* Documentation for Renesas SMARC EVK
* SYSC binding doc required for SoC identification
* SoC identification support
* Enabling ARCH_R9A07G044 in defconfig

All the patches have been cherry picked from v5.16-rc5

[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rzg2l-general-purpose-microprocessors-dual-
core-arm-cortex-a55-12-ghz-cpus-3d-graphics-and-video-codec
[1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rtk9744l23s01000be-rzg2l-evaluation-board-kit

Cheers,
Prabhakar


Lad Prabhakar (7):
dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC
dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants
dt-bindings: arm: renesas: Document SMARC EVK
dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation
for SYSC controller
soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's
soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC}
SoC's
arm64: defconfig: Enable ARCH_R9A07G044

.../devicetree/bindings/arm/renesas.yaml | 18 ++++++
.../bindings/power/renesas,rzg2l-sysc.yaml | 63 +++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/soc/renesas/Kconfig | 5 ++
drivers/soc/renesas/renesas-soc.c | 33 +++++++++-
5 files changed, 119 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml

--
2.17.1

Hi!

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec
(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded devices
with video capabilities.

Patches add support for the following:
* Documentation for RZ/G2{L,LC,UL} SoC variants
* Documentation for Renesas SMARC EVK
* SYSC binding doc required for SoC identification
* SoC identification support
* Enabling ARCH_R9A07G044 in defconfig

All the patches have been cherry picked from v5.16-rc5

[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rzg2l-general-purpose-microprocessors-dual-
core-arm-cortex-a55-12-ghz-cpus-3d-graphics-and-video-codec
[1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rtk9744l23s01000be-rzg2l-evaluation-board-kit

LGTM. I can merge this seriese, If there is no objection.

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>

Looks good to me too. I have series ready due to testing, so I'll push
it.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Hello,

From: nobuhiro1.iwamatsu@...
<nobuhiro1.iwamatsu@...>
Sent: 16 December 2021 00:40

Hi all,

I have reviewed patches and they look okay to me. I'll proceed with
testing.

Do we have suitable board in the test lab / is there plan to add one?

We don't have any boards in the CIP labs yet, but there is a plan to add

some.

I think I need to add the board to LAB first. Of course, source code reviews
and
build tests are possible.
And If my understand is correctoly, I think this is a new board that is not on
the
reference board list. I don't think this has been discussed at TSC.
I think it needs to be on the agenda at TSC, whether it's a reference board for
the 5.10-cip kernel.

We are planning to propose it as a CIP reference board and we plan to add some hardware to the CIP's LAVA infrastructure.
If the board is not accepted as a CIP reference board, we would still like to add support for it in the CIP Kernel as we have done for other non-reference boards such as the iWave RZ/G1E, HiHope RZ/G2H boards etc.

Kind regards, Chris

Hi Chris,

We are planning to propose it as a CIP reference board and we plan to add some hardware to the CIP's LAVA infrastructure.
If the board is not accepted as a CIP reference board, we would still like to add support for it in the CIP Kernel as we have done for other non-reference boards such as the iWave RZ/G1E, HiHope RZ/G2H boards etc.

I see. Thanks for the explanation.

Best regards,
Nobuhiro
________________________________________
差出人: Chris Paterson <Chris.Paterson2@...>
送信日時: 2021年12月16日 18:52
宛先: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ); cip-dev@...; Prabhakar Mahadev Lad
CC: pavel@...; Biju Das
件名: RE: [cip-dev] [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK

Hello,

From: nobuhiro1.iwamatsu@...
<nobuhiro1.iwamatsu@...>
Sent: 16 December 2021 00:40

Hi all,

I have reviewed patches and they look okay to me. I'll proceed with
testing.

Do we have suitable board in the test lab / is there plan to add one?

We don't have any boards in the CIP labs yet, but there is a plan to add

some.

I think I need to add the board to LAB first. Of course, source code reviews
and
build tests are possible.
And If my understand is correctoly, I think this is a new board that is not on
the
reference board list. I don't think this has been discussed at TSC.
I think it needs to be on the agenda at TSC, whether it's a reference board for
the 5.10-cip kernel.

We are planning to propose it as a CIP reference board and we plan to add some hardware to the CIP's LAVA infrastructure.
If the board is not accepted as a CIP reference board, we would still like to add support for it in the CIP Kernel as we have done for other non-reference boards such as the iWave RZ/G1E, HiHope RZ/G2H boards etc.

Kind regards, Chris