Hi All,

This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
- CPU
- CPG
- GIC
* Initial device tree for RZ/G2L SMARC EVK
- memory
- External input clock
- SCIF

All the patches have been cherry picked from 5.16-rc5. For testing purpose
MR [0] can be used.

[0] https://gitlab.com/cip-project/cip-kernel/
cip-kernel-config/-/merge_requests/52

Cheers,
Prabhakar

Biju Das (9):
serial: sh-sci: Add support for RZ/G2L SoC
clk: renesas: r9a07g044: Rename divider table
clk: renesas: r9a07g044: Fix P1 Clock
clk: renesas: r9a07g044: Add P2 Clock support
clk: renesas: rzg2l: Add multi clock PM support
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions
clk: renesas: rzg2l: Add support to handle MUX clocks
clk: renesas: rzg2l: Add support to handle coupled clocks
clk: renesas: rzg2l: Fix clk status function

Dan Carpenter (2):
clk: renesas: rzg2l: Fix a double free on error
clk: renesas: rzg2l: Avoid mixing error pointers and NULL

Dmitry Baryshkov (1):
clk: mux: provide devm_clk_hw_register_mux()

Geert Uytterhoeven (1):
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]

Lad Prabhakar (9):
dt-bindings: serial: renesas,scif: Document r9a07g044 bindings
dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
clk: renesas: Add CPG core wrapper for RZ/G2L SoC
clk: renesas: Add support for R9A07G044 SoC
arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's
arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK
arm64: dts: renesas: r9a07g044: Add SYSC node
clk: renesas: rzg2l: Fix off-by-one check in
rzg2l_cpg_clk_src_twocell_get()

Yang Li (2):
clk: renesas: rzg2l: Remove unneeded semicolon
clk: renesas: rzg2l: Fix return value and unused assignment

.../bindings/clock/renesas,rzg2l-cpg.yaml | 83 ++
.../bindings/serial/renesas,scif.yaml | 4 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 132 +++
arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 25 +
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 +
arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi | 13 +
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 27 +
drivers/clk/clk-mux.c | 35 +
drivers/clk/renesas/Kconfig | 9 +
drivers/clk/renesas/Makefile | 2 +
drivers/clk/renesas/r9a07g044-cpg.c | 142 +++
drivers/clk/renesas/rzg2l-cpg.c | 844 ++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.h | 176 ++++
drivers/tty/serial/sh-sci.c | 12 +-
drivers/tty/serial/sh-sci.h | 1 +
include/dt-bindings/clock/r9a07g044-cpg.h | 219 +++++
include/linux/clk-provider.h | 13 +
18 files changed, 1759 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c
create mode 100644 drivers/clk/renesas/rzg2l-cpg.c
create mode 100644 drivers/clk/renesas/rzg2l-cpg.h
create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h

--
2.17.1

Hi Prabhakar,

This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
- CPU
- CPG
- GIC
* Initial device tree for RZ/G2L SMARC EVK
- memory
- External input clock
- SCIF

All the patches have been cherry picked from 5.16-rc5. For testing purpose
MR [0] can be used.

I will check this series, and I am also checking the build.
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/431663140

Best regards,
Nobuhiro

________________________________________
差出人: cip-dev@... <cip-dev@...> が Lad Prabhakar <prabhakar.mahadev-lad.rj@...> の代理で送信
送信日時: 2021年12月16日 21:54
宛先: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ); Pavel Machek
CC: Biju Das
件名: [cip-dev] [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK

Hi All,

This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
- CPU
- CPG
- GIC
* Initial device tree for RZ/G2L SMARC EVK
- memory
- External input clock
- SCIF

All the patches have been cherry picked from 5.16-rc5. For testing purpose
MR [0] can be used.

[0] https://gitlab.com/cip-project/cip-kernel/
cip-kernel-config/-/merge_requests/52

Cheers,
Prabhakar

Biju Das (9):
serial: sh-sci: Add support for RZ/G2L SoC
clk: renesas: r9a07g044: Rename divider table
clk: renesas: r9a07g044: Fix P1 Clock
clk: renesas: r9a07g044: Add P2 Clock support
clk: renesas: rzg2l: Add multi clock PM support
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions
clk: renesas: rzg2l: Add support to handle MUX clocks
clk: renesas: rzg2l: Add support to handle coupled clocks
clk: renesas: rzg2l: Fix clk status function

Dan Carpenter (2):
clk: renesas: rzg2l: Fix a double free on error
clk: renesas: rzg2l: Avoid mixing error pointers and NULL

Dmitry Baryshkov (1):
clk: mux: provide devm_clk_hw_register_mux()

Geert Uytterhoeven (1):
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]

Lad Prabhakar (9):
dt-bindings: serial: renesas,scif: Document r9a07g044 bindings
dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
clk: renesas: Add CPG core wrapper for RZ/G2L SoC
clk: renesas: Add support for R9A07G044 SoC
arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's
arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK
arm64: dts: renesas: r9a07g044: Add SYSC node
clk: renesas: rzg2l: Fix off-by-one check in
rzg2l_cpg_clk_src_twocell_get()

Yang Li (2):
clk: renesas: rzg2l: Remove unneeded semicolon
clk: renesas: rzg2l: Fix return value and unused assignment

.../bindings/clock/renesas,rzg2l-cpg.yaml | 83 ++
.../bindings/serial/renesas,scif.yaml | 4 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 132 +++
arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 25 +
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 +
arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi | 13 +
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 27 +
drivers/clk/clk-mux.c | 35 +
drivers/clk/renesas/Kconfig | 9 +
drivers/clk/renesas/Makefile | 2 +
drivers/clk/renesas/r9a07g044-cpg.c | 142 +++
drivers/clk/renesas/rzg2l-cpg.c | 844 ++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.h | 176 ++++
drivers/tty/serial/sh-sci.c | 12 +-
drivers/tty/serial/sh-sci.h | 1 +
include/dt-bindings/clock/r9a07g044-cpg.h | 219 +++++
include/linux/clk-provider.h | 13 +
18 files changed, 1759 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c
create mode 100644 drivers/clk/renesas/rzg2l-cpg.c
create mode 100644 drivers/clk/renesas/rzg2l-cpg.h
create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h

--
2.17.1

Hi!

This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
- CPU
- CPG
- GIC
* Initial device tree for RZ/G2L SMARC EVK
- memory
- External input clock
- SCIF

All the patches have been cherry picked from 5.16-rc5. For testing purpose
MR [0] can be used.

I will check this series, and I am also checking the build.

https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/431663140

Thank you. I checked the series and only found some details (some of
them were fixed later in the series). I believe we can apply it.

Reviewed-by: Pavel Machek <pavel@...>
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Hi all,

Thank you. I checked the series and only found some details (some of
them were fixed later in the series). I believe we can apply it.

Reviewed-by: Pavel Machek <pavel@...>

I pushed this series.

Best regards,
Nobuhiro
________________________________________
差出人: Pavel Machek
送信: 2021 12 月 17 日 (金曜日) 19:39
宛先: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
Cc: cip-dev@...; pavel@...; biju.das.jz@...
件名: Re: [cip-dev] [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK


Hi!

This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
   - CPU
   - CPG
   - GIC
* Initial device tree for RZ/G2L SMARC EVK
   - memory
   - External input clock
   - SCIF

All the patches have been cherry picked from 5.16-rc5. For testing purpose
MR [0] can be used.

I will check this series, and I am also checking the build.

https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/431663140

Thank you. I checked the series and only found some details (some of
them were fixed later in the series). I believe we can apply it.

Reviewed-by: Pavel Machek <pavel@...>
                                                                Pavel
--
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Hi Nobuhiro/Pavel.