commit 3733db1f77130588c9a2c1596937294998bd7d27 upstream.

Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Rob Herring <robh@...>
Link: https://lore.kernel.org/r/20220315142915.17764-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc616b..311a93590597 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -10,7 +10,7 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@...>

description: |
- On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
+ On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.

They provide the following functionalities:
@@ -23,8 +23,9 @@ description: |
properties:
compatible:
enum:
- - renesas,r9a07g044-cpg # RZ/G2{L,LC}
- - renesas,r9a07g054-cpg # RZ/V2L
+ - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
+ - renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ - renesas,r9a07g054-cpg # RZ/V2L

reg:
maxItems: 1
--
2.25.1