commit e6a9acc370c6cb9e6ff6225b034a7a4374df0134 upstream.

Add OPP table for RZ/G2UL SoC.

Signed-off-by: Biju Das <biju.das.jz@...>
Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 82fe61991204..e2300d5c6a15 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -42,6 +42,33 @@ extal_clk: extal-clk {
clock-frequency = <0>;
};

+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -53,6 +80,7 @@ cpu0: cpu@0 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
};

L3_CA55: cache-controller-0 {
--
2.25.1