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[isar-cip-core][PATCH v4 4/8] add opensbi with u-boot payload for riscv64
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Felix Moessbauer <felix.moessbauer@...>
This patch adds the opensbi firmware with u-boot payload (smode) for the
qemu-riscv64 machine. Using that, the generated riscv64 images can be booted on qemu. Signed-off-by: Felix Moessbauer <felix.moessbauer@...> --- recipes-bsp/opensbi/files/qemu-riscv64-rules | 12 ++++ .../opensbi/opensbi-qemu-riscv64_1.2.bb | 8 +++ recipes-bsp/opensbi/opensbi.inc | 45 +++++++++++++++ ...iscv-Fix-build-against-binutils-2.38.patch | 55 +++++++++++++++++++ .../u-boot/u-boot-qemu-riscv64_2022.07.bb | 22 ++++++++ 5 files changed, 142 insertions(+) create mode 100644 recipes-bsp/opensbi/files/qemu-riscv64-rules create mode 100644 recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb create mode 100644 recipes-bsp/opensbi/opensbi.inc create mode 100644 recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch create mode 100644 recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb diff --git a/recipes-bsp/opensbi/files/qemu-riscv64-rules b/recipes-bsp/opensbi/files/qemu-riscv64-rules new file mode 100644 index 0000000..960e10c --- /dev/null +++ b/recipes-bsp/opensbi/files/qemu-riscv64-rules @@ -0,0 +1,12 @@ +#!/usr/bin/make -f + +ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE)) +export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)- +endif + +override_dh_auto_build: + CFLAGS= LDFLAGS= $(MAKE) $(PARALLEL_MAKE) PLATFORM=generic \ + FW_PAYLOAD_PATH=/usr/lib/u-boot/qemu-riscv64/u-boot.bin + +%: + dh $@ diff --git a/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb b/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb new file mode 100644 index 0000000..b503afc --- /dev/null +++ b/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb @@ -0,0 +1,8 @@ +# +# Copyright (c) Siemens AG, 2023 +# +# SPDX-License-Identifier: MIT + +include opensbi.inc + +SRC_URI[opensbi.sha256sum] = "8fcbce598a73acc2c7f7d5607d46b9d5107d3ecbede8f68f42631dcfc25ef2b2" diff --git a/recipes-bsp/opensbi/opensbi.inc b/recipes-bsp/opensbi/opensbi.inc new file mode 100644 index 0000000..b41a8bb --- /dev/null +++ b/recipes-bsp/opensbi/opensbi.inc @@ -0,0 +1,45 @@ +# +# Copyright (c) Siemens AG, 2023 +# +# SPDX-License-Identifier: MIT + +inherit dpkg + +U_BOOT_PACKAGE ?= "u-boot-${MACHINE}" +PLATFORM ?= "generic" + +DEPLOYDIR_FIRMWARE = "${WORKDIR}/deploy-fw" +SSTATETASKS += "do_deploy" + +SRC_URI = " \ + https://github.com/riscv/opensbi/archive/v${PV}.tar.gz;downloadfilename=opensbi-${PV}.tar.gz;name=opensbi \ + file://${MACHINE}-rules" + +S = "${WORKDIR}/opensbi-${PV}" + +DEPENDS += "${U_BOOT_PACKAGE}" +DEBIAN_BUILD_DEPENDS .= ",${U_BOOT_PACKAGE}" + +do_prepare_build[cleandirs] += "${S}/debian" +do_prepare_build() { + cp ${WORKDIR}/${MACHINE}-rules ${WORKDIR}/rules + deb_debianize + + echo "build/platform/${PLATFORM}/firmware/fw_payload.bin /usr/lib/opensbi/${MACHINE}/" > ${S}/debian/install +} + +do_deploy[cleandirs] += "${DEPLOYDIR_FIRMWARE}" +do_deploy[sstate-inputdirs] = "${DEPLOYDIR_FIRMWARE}" +do_deploy[sstate-outputdirs] = "${DEPLOY_DIR_IMAGE}" +do_deploy() { + dpkg --fsys-tarfile "${WORKDIR}/${PN}_${PV}_${DISTRO_ARCH}.deb" | \ + tar xOf - "./usr/lib/opensbi/${MACHINE}/fw_payload.bin" \ + > "${DEPLOYDIR_FIRMWARE}/fw_payload.bin" +} + +python do_deploy_setscene () { + sstate_setscene(d) +} +addtask do_deploy_setscene + +addtask deploy after do_dpkg_build before do_deploy_deb diff --git a/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch new file mode 100644 index 0000000..6f8a2ae --- /dev/null +++ b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch @@ -0,0 +1,55 @@ +From 5df4b2299f86933fa79aa3bc6a3986fc7e55b7e0 Mon Sep 17 00:00:00 2001 +From: Alexandre Ghiti <alexandre.ghiti@...> +Date: Mon, 3 Oct 2022 18:07:54 +0200 +Subject: [PATCH 1/2] riscv: Fix build against binutils 2.38 + +The following description is copied from the equivalent patch for the +Linux Kernel proposed by Aurelien Jarno: + +>From version 2.38, binutils default to ISA spec version 20191213. This +means that the csr read/write (csrr*/csrw*) instructions and fence.i +instruction has separated from the `I` extension, become two standalone +extensions: Zicsr and Zifencei. As the kernel uses those instruction, +this causes the following build failure: + +arch/riscv/cpu/mtrap.S: Assembler messages: +arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' +arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' +arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' +arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' + +Signed-off-by: Alexandre Ghiti <alexandre.ghiti@...> +Reviewed-by: Bin Meng <bmeng.cn@...> +Tested-by: Heinrich Schuchardt <heinrich.schuchardt@...> +Tested-by: Heiko Stuebner <heiko@...> +Tested-by: Christian Stewart <christian@...> +Reviewed-by: Rick Chen <rick@...> +--- + arch/riscv/Makefile | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 0b80eb8d86..53d1194ffb 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany + endif + +-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ ++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) ++ ++# Newer binutils versions default to ISA spec version 20191213 which moves some ++# instructions from the I extension to the Zicsr and Zifencei extensions. ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) ++ifeq ($(toolchain-need-zicsr-zifencei),y) ++ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei ++endif ++ ++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ + -mcmodel=$(CMODEL) + + PLATFORM_CPPFLAGS += $(ARCH_FLAGS) +-- +2.30.2 + diff --git a/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb new file mode 100644 index 0000000..8dfac45 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb @@ -0,0 +1,22 @@ +# +# CIP Core, generic profile +# +# Copyright (c) Siemens AG, 2022 +# +# Authors: +# Jan Kiszka <jan.kiszka@...> +# +# SPDX-License-Identifier: MIT +# + +require u-boot-qemu-common.inc + +# we run as OpenSBI payload, hence use smode +U_BOOT_CONFIG = "${MACHINE}_smode_defconfig" + +EFI_ARCH = "riscv64" + +SRC_URI += " \ + file://riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch" + +U_BOOT_BIN = "u-boot.bin" -- 2.34.1 |
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Jan Kiszka
On 03.03.23 13:48, Felix Moessbauer wrote:
This patch adds the opensbi firmware with u-boot payload (smode) for theThis triggers fetcher warnings for other machines. Moving to the machine-specific recipe. Jan +-- Siemens AG, Technology Competence Center Embedded Linux |
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