[PATCH 5.10.y-cip 10/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash


Biju Das
 

commit 018d7b93477fbb04ba7b4bc4c355793d644e45da upstream.

Enable mt25qu512a flash connected to QSPI0.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220307192436.13237-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 88a7938017aa..80c9a1146cb7 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -110,6 +110,18 @@ gpio-sd0-pwr-en-hog {
line-name = "gpio_sd0_pwr_en";
};

+ qspi0_pins: qspi0 {
+ qspi0-data {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
+ power-source = <1800>;
+ };
+
+ qspi0-ctrl {
+ pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
+ power-source = <1800>;
+ };
+ };
+
/*
* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
* The below switch logic can be used to select the device between
@@ -175,6 +187,34 @@ sd0_mux_uhs {
};
};

+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,mt25qu512a", "jedec,spi-nor";
+ reg = <0>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ reg = <0x00000000 0x2000000>;
+ read-only;
+ };
+ user@2000000 {
+ reg = <0x2000000 0x2000000>;
+ };
+ };
+ };
+};
+
#if (!SW_SD0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
--
2.25.1