[PATCH 5.10.y-cip] clk: renesas: rzg2l: Fix reset status function


Biju Das
 

commit 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 upstream.

As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means
reset signal is not applied (deassert state) and 1 means reset signal
is applied (assert state).

reset_control_status() expects a positive value if the reset line is
asserted. But rzg2l_cpg_status function returns zero for asserted
state.

This patch fixes the issue by adding double inverted logic, so that
reset_control_status returns a positive value if the reset line is
asserted.

Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Biju Das <biju.das.jz@...>
Link: https://lore.kernel.org/r/20220531071657.104121-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[Biju: Manually applied the changes]
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/clk/renesas/rzg2l-cpg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index f626d2704477..a03bc9cbbd4b 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -742,7 +742,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
unsigned int reg = info->resets[id].off;
u32 bitmask = BIT(info->resets[id].bit);

- return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
+ return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
}

static const struct reset_control_ops rzg2l_cpg_reset_ops = {
--
2.25.1


Pavel Machek
 

Hi!

commit 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 upstream.

As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means
reset signal is not applied (deassert state) and 1 means reset signal
is applied (assert state).

reset_control_status() expects a positive value if the reset line is
asserted. But rzg2l_cpg_status function returns zero for asserted
state.

This patch fixes the issue by adding double inverted logic, so that
reset_control_status returns a positive value if the reset line is
asserted.
Looks ok to me. I can apply it if it passes testing and there are no
other comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Nobuhiro Iwamatsu
 

Hi all,

-----Original Message-----
From: Pavel Machek <pavel@...>
Sent: Monday, August 22, 2022 10:05 PM
To: Biju Das <biju.das.jz@...>
Cc: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □SWC◯A
CT) <nobuhiro1.iwamatsu@...>; Pavel Machek
<pavel@...>; Chris Paterson <chris.paterson2@...>;
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>
Subject: Re: [PATCH 5.10.y-cip] clk: renesas: rzg2l: Fix reset status function

Hi!

commit 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 upstream.

As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0
means reset signal is not applied (deassert state) and 1 means reset
signal is applied (assert state).

reset_control_status() expects a positive value if the reset line is
asserted. But rzg2l_cpg_status function returns zero for asserted
state.

This patch fixes the issue by adding double inverted logic, so that
reset_control_status returns a positive value if the reset line is
asserted.
Looks ok to me. I can apply it if it passes testing and there are no other
comments.
LGTM too.
I can not find Pavel's test, so I am running in following pilpeline:
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/621098021

If test is OK, I will apply this.

Best regards,
Nobuhiro


Nobuhiro Iwamatsu
 

Hi all,

-----Original Message-----
From: iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
Sent: Wednesday, August 24, 2022 10:50 AM
To: Pavel Machek <pavel@...>; Biju Das <biju.das.jz@...>
Cc: cip-dev@...; Chris Paterson
<chris.paterson2@...>; Prabhakar Mahadev Lad
<prabhakar.mahadev-lad.rj@...>
Subject: RE: [PATCH 5.10.y-cip] clk: renesas: rzg2l: Fix reset status function

Hi all,

-----Original Message-----
From: Pavel Machek <pavel@...>
Sent: Monday, August 22, 2022 10:05 PM
To: Biju Das <biju.das.jz@...>
Cc: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □SWC◯

CT) <nobuhiro1.iwamatsu@...>; Pavel Machek
<pavel@...>;
Chris Paterson <chris.paterson2@...>; Prabhakar Mahadev Lad
<prabhakar.mahadev-lad.rj@...>
Subject: Re: [PATCH 5.10.y-cip] clk: renesas: rzg2l: Fix reset status
function

Hi!

commit 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 upstream.

As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0
means reset signal is not applied (deassert state) and 1 means reset
signal is applied (assert state).

reset_control_status() expects a positive value if the reset line is
asserted. But rzg2l_cpg_status function returns zero for asserted
state.

This patch fixes the issue by adding double inverted logic, so that
reset_control_status returns a positive value if the reset line is
asserted.
Looks ok to me. I can apply it if it passes testing and there are no
other comments.
LGTM too.
I can not find Pavel's test, so I am running in following pilpeline:
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/621098021

If test is OK, I will apply this.
The test looks good. I just pushed.

Best regards,
Nobuhiro