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[PATCH 5.10.y-cip 03/26] clk: renesas: Add support for RZ/G2UL SoC
commit c8b088224c25ef4f5270f9de6a3516181b63f38c upstream. The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG ar
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commit c8b088224c25ef4f5270f9de6a3516181b63f38c upstream. The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG ar
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Biju Das
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[PATCH 5.10.y-cip 04/26] clk: renesas: r9a07g043: Add GPIO clock and reset entries
commit 6c185664b3d481292c41fbfe66ea19c84cb0237a upstream. Add GPIO clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj
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commit 6c185664b3d481292c41fbfe66ea19c84cb0237a upstream. Add GPIO clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj
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Biju Das
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[PATCH 5.10.y-cip 05/26] clk: renesas: r9a07g043: Add ethernet clock sources
commit f201eb84450f98decb1834e73409bb2271441dd7 upstream. Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. Signed-o
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commit f201eb84450f98decb1834e73409bb2271441dd7 upstream. Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. Signed-o
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Biju Das
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[PATCH 5.10.y-cip 06/26] clk: renesas: r9a07g043: Add GbEthernet clock/reset
commit e11f804afc12e1c622f0a6f966fafd05b7022f8a upstream. Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj
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commit e11f804afc12e1c622f0a6f966fafd05b7022f8a upstream. Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj
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Biju Das
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[PATCH 5.10.y-cip 07/26] clk: renesas: r9a07g043: Add SDHI clock and reset entries
commit 59086e4193f4fc920a23d2045a473f62450b4269 upstream. Add SDHI{0,1} mux, clock and reset entries to CPG driver Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahad
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commit 59086e4193f4fc920a23d2045a473f62450b4269 upstream. Add SDHI{0,1} mux, clock and reset entries to CPG driver Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahad
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Biju Das
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[PATCH 5.10.y-cip 08/26] clk: renesas: r9a07g043: Add I2C clocks/resets
commit a9391e019015e96d4ed40587ce0f648edf1c32d3 upstream. Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.156720-2-bi
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commit a9391e019015e96d4ed40587ce0f648edf1c32d3 upstream. Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.156720-2-bi
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Biju Das
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[PATCH 5.10.y-cip 09/26] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries
commit be5b5fcbc779f04a6ad38e9d4772712fe05b6f15 upstream. Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/202204250
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commit be5b5fcbc779f04a6ad38e9d4772712fe05b6f15 upstream. Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/202204250
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Biju Das
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[PATCH 5.10.y-cip 10/26] clk: renesas: r9a07g043: Add USB clocks/resets
commit 666b5a010ef1e8d08227f5aa6e5b431ce0feca07 upstream. Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r
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commit 666b5a010ef1e8d08227f5aa6e5b431ce0feca07 upstream. Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r
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Biju Das
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[PATCH 5.10.y-cip 11/26] clk: renesas: r9a07g043: Add clock and reset entries for CANFD
commit 1cbda37757ab5581a18214b62e83a914acfcf3e8 upstream. Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.
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commit 1cbda37757ab5581a18214b62e83a914acfcf3e8 upstream. Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.
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Biju Das
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[PATCH 5.10.y-cip 12/26] clk: renesas: r9a07g043: Add OSTM clock and reset entries
commit 6c05648b57aba4c677eaf9c6c4c10bf4e713c1c0 upstream. Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/2022042509524
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commit 6c05648b57aba4c677eaf9c6c4c10bf4e713c1c0 upstream. Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/2022042509524
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Biju Das
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[PATCH 5.10.y-cip 13/26] clk: renesas: r9a07g043: Add WDT clock and reset entries
commit 5d33481f54758eb050473af0692a043c084ad581 upstream. Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.1
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commit 5d33481f54758eb050473af0692a043c084ad581 upstream. Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.1
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Biju Das
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[PATCH 5.10.y-cip 14/26] pinctrl: renesas: rzg2l: Add RZ/G2UL support
commit bfc69bdbaad141ac408e6de86b7e0d771c8e3ccb upstream. RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible
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commit bfc69bdbaad141ac408e6de86b7e0d771c8e3ccb upstream. RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible
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Biju Das
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[PATCH 5.10.y-cip 15/26] pinctrl: renesas: rzg2l: Restore pin config order
From: Geert Uytterhoeven <geert+renesas@...> commit f7bc5f52d2354b41d5a111942be7ee01e5560c78 upstream. The PIN_CFG_* capabilities are always listed in the order they are defined, except in the "TMS/SW
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From: Geert Uytterhoeven <geert+renesas@...> commit f7bc5f52d2354b41d5a111942be7ee01e5560c78 upstream. The PIN_CFG_* capabilities are always listed in the order they are defined, except in the "TMS/SW
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Biju Das
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[PATCH 5.10.y-cip 16/26] pinctrl: renesas: rzg2l: Return -EINVAL for pins which have input disabled
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> commit 5223c511eb4f919e6b423b2f66e02674e97e77e3 upstream. Pin status reported by pinconf-pins file always reported pin status as "input enabled" even
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> commit 5223c511eb4f919e6b423b2f66e02674e97e77e3 upstream. Pin status reported by pinconf-pins file always reported pin status as "input enabled" even
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Biju Das
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[PATCH 5.10.y-cip 17/26] arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
commit cf40c9689e5109bf5e4c29038c9f450223aaad2b upstream. Add initial DTSI for RZ/G2UL SoC. Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share the common dtsi (rz-smarc.dtsi) file.
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commit cf40c9689e5109bf5e4c29038c9f450223aaad2b upstream. Add initial DTSI for RZ/G2UL SoC. Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share the common dtsi (rz-smarc.dtsi) file.
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Biju Das
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[PATCH 5.10.y-cip 18/26] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
commit 895199bc4e5261b67b688a915c592dd4c3af113c upstream. Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11): - memory - External input clock - CPG - DMA - SCIF It shares the same carrier
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commit 895199bc4e5261b67b688a915c592dd4c3af113c upstream. Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11): - memory - External input clock - CPG - DMA - SCIF It shares the same carrier
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Biju Das
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[PATCH 5.10.y-cip 19/26] arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node
commit 2d10555298576a95b637a5087751d0aad570964d upstream. Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahade
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commit 2d10555298576a95b637a5087751d0aad570964d upstream. Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahade
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Biju Das
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[PATCH 5.10.y-cip 20/26] arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins
commit 4e44055440e1fef93e830bd06111bbbb0a89fa44 upstream. Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting the pinctrl-0 and pinctrl-names properties for scif0 node so that we now ac
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commit 4e44055440e1fef93e830bd06111bbbb0a89fa44 upstream. Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting the pinctrl-0 and pinctrl-names properties for scif0 node so that we now ac
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Biju Das
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[PATCH 5.10.y-cip 21/26] arm64: dts: renesas: r9a07g043: Add SDHI nodes
commit 20e63d3948985672b9e8efa98ff3643d91378e84 upstream. Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
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commit 20e63d3948985672b9e8efa98ff3643d91378e84 upstream. Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
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Biju Das
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[PATCH 5.10.y-cip 22/26] arm64: dts: renesas: r9a07g043: Add GbEthernet nodes
commit 13ea8b3584c09f0ab94d5447ff2965d255329a88 upstream. Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@..
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commit 13ea8b3584c09f0ab94d5447ff2965d255329a88 upstream. Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@..
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Biju Das
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