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[PATCH 5.10.y-cip 14/26] pinctrl: renesas: rzg2l: Add RZ/G2UL support
commit bfc69bdbaad141ac408e6de86b7e0d771c8e3ccb upstream. RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible
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commit bfc69bdbaad141ac408e6de86b7e0d771c8e3ccb upstream. RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible
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By
Biju Das
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[PATCH 5.10.y-cip 13/26] clk: renesas: r9a07g043: Add WDT clock and reset entries
commit 5d33481f54758eb050473af0692a043c084ad581 upstream. Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.1
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commit 5d33481f54758eb050473af0692a043c084ad581 upstream. Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.1
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Biju Das
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[PATCH 5.10.y-cip 12/26] clk: renesas: r9a07g043: Add OSTM clock and reset entries
commit 6c05648b57aba4c677eaf9c6c4c10bf4e713c1c0 upstream. Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/2022042509524
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commit 6c05648b57aba4c677eaf9c6c4c10bf4e713c1c0 upstream. Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/2022042509524
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Biju Das
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[PATCH 5.10.y-cip 11/26] clk: renesas: r9a07g043: Add clock and reset entries for CANFD
commit 1cbda37757ab5581a18214b62e83a914acfcf3e8 upstream. Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.
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commit 1cbda37757ab5581a18214b62e83a914acfcf3e8 upstream. Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.
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Biju Das
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[PATCH 5.10.y-cip 10/26] clk: renesas: r9a07g043: Add USB clocks/resets
commit 666b5a010ef1e8d08227f5aa6e5b431ce0feca07 upstream. Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r
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commit 666b5a010ef1e8d08227f5aa6e5b431ce0feca07 upstream. Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r
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Biju Das
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[PATCH 5.10.y-cip 09/26] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries
commit be5b5fcbc779f04a6ad38e9d4772712fe05b6f15 upstream. Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/202204250
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commit be5b5fcbc779f04a6ad38e9d4772712fe05b6f15 upstream. Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/202204250
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Biju Das
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[PATCH 5.10.y-cip 08/26] clk: renesas: r9a07g043: Add I2C clocks/resets
commit a9391e019015e96d4ed40587ce0f648edf1c32d3 upstream. Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.156720-2-bi
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commit a9391e019015e96d4ed40587ce0f648edf1c32d3 upstream. Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20220425095244.156720-2-bi
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Biju Das
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[PATCH 5.10.y-cip 07/26] clk: renesas: r9a07g043: Add SDHI clock and reset entries
commit 59086e4193f4fc920a23d2045a473f62450b4269 upstream. Add SDHI{0,1} mux, clock and reset entries to CPG driver Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahad
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commit 59086e4193f4fc920a23d2045a473f62450b4269 upstream. Add SDHI{0,1} mux, clock and reset entries to CPG driver Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahad
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Biju Das
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[PATCH 5.10.y-cip 06/26] clk: renesas: r9a07g043: Add GbEthernet clock/reset
commit e11f804afc12e1c622f0a6f966fafd05b7022f8a upstream. Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj
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commit e11f804afc12e1c622f0a6f966fafd05b7022f8a upstream. Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj
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Biju Das
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[PATCH 5.10.y-cip 05/26] clk: renesas: r9a07g043: Add ethernet clock sources
commit f201eb84450f98decb1834e73409bb2271441dd7 upstream. Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. Signed-o
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commit f201eb84450f98decb1834e73409bb2271441dd7 upstream. Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. Signed-o
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Biju Das
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[PATCH 5.10.y-cip 04/26] clk: renesas: r9a07g043: Add GPIO clock and reset entries
commit 6c185664b3d481292c41fbfe66ea19c84cb0237a upstream. Add GPIO clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj
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commit 6c185664b3d481292c41fbfe66ea19c84cb0237a upstream. Add GPIO clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj
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Biju Das
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[PATCH 5.10.y-cip 03/26] clk: renesas: Add support for RZ/G2UL SoC
commit c8b088224c25ef4f5270f9de6a3516181b63f38c upstream. The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG ar
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commit c8b088224c25ef4f5270f9de6a3516181b63f38c upstream. The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG ar
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Biju Das
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[PATCH 5.10.y-cip 02/26] soc: renesas: Identify RZ/G2UL SoC
commit 2f89bef90de4740be33b2cb4ba95e0107df0d25e upstream. Add support for identifying the RZ/G2UL SoC. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@..
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commit 2f89bef90de4740be33b2cb4ba95e0107df0d25e upstream. Add support for identifying the RZ/G2UL SoC. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@..
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Biju Das
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[PATCH 5.10.y-cip 01/26] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
commit eb2789785428e2dbc3d5f413b16c67ff90d828c1 upstream. Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and als
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commit eb2789785428e2dbc3d5f413b16c67ff90d828c1 upstream. Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and als
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Biju Das
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[PATCH 5.10.y-cip 10/10] dt-bindings: net: renesas,etheravb: Document RZ/G2UL SoC
commit 5e2e8cc9dd3314e2cf2814d19d0aaa4c983b1d3d upstream. Document Gigabit Ethernet IP found on RZ/G2UL SoC. Gigabit Ethernet Interface is identical to one found on the RZ/G2L SoC. No driver changes a
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commit 5e2e8cc9dd3314e2cf2814d19d0aaa4c983b1d3d upstream. Document Gigabit Ethernet IP found on RZ/G2UL SoC. Gigabit Ethernet Interface is identical to one found on the RZ/G2L SoC. No driver changes a
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Biju Das
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[PATCH 5.10.y-cip 09/10] dt-bindings: mmc: renesas,sdhi: Document RZ/G2UL SoC
commit dc3d879c6ffa25e90875237265898e49b2cabb7e upstream. Document RZ/G2UL SDHI bindings. RZ/G2UL SDHI is almost identical to one found on the R-Car Gen3. No driver changes are required as generic com
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commit dc3d879c6ffa25e90875237265898e49b2cabb7e upstream. Document RZ/G2UL SDHI bindings. RZ/G2UL SDHI is almost identical to one found on the R-Car Gen3. No driver changes are required as generic com
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Biju Das
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[PATCH 5.10.y-cip 08/10] dt-bindings: dma: rz-dmac: Document RZ/G2UL SoC
commit 614c8beca7cd6e7093385c88da800e258b7eb0ca upstream. Document RZ/G2UL DMAC bindings. RZ/G2UL DMAC is identical to one found on the RZ/G2L SoC. No driver changes are required as generic compatible
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commit 614c8beca7cd6e7093385c88da800e258b7eb0ca upstream. Document RZ/G2UL DMAC bindings. RZ/G2UL DMAC is identical to one found on the RZ/G2L SoC. No driver changes are required as generic compatible
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Biju Das
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[PATCH 5.10.y-cip 07/10] dt-bindings: serial: renesas,sci: Document RZ/G2UL SoC
commit 5cfb02ced7e0928b5ae39b0320c2de408bb210ac upstream. Add SCI binding documentation for Renesas RZ/G2UL SoC. No driver changes are required as generic compatible string "renesas,sci" will be used
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commit 5cfb02ced7e0928b5ae39b0320c2de408bb210ac upstream. Add SCI binding documentation for Renesas RZ/G2UL SoC. No driver changes are required as generic compatible string "renesas,sci" will be used
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Biju Das
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[PATCH 5.10.y-cip 06/10] dt-bindings: serial: renesas,scif: Document RZ/G2UL SoC
commit ed265bc955cfa46490d07db0bf5de985b31367da upstream. Add SCIF binding documentation for Renesas RZ/G2UL SoC. SCIF block on RZ/G2UL is identical to one found on the RZ/G2L SoC. No driver changes a
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commit ed265bc955cfa46490d07db0bf5de985b31367da upstream. Add SCIF binding documentation for Renesas RZ/G2UL SoC. SCIF block on RZ/G2UL is identical to one found on the RZ/G2L SoC. No driver changes a
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Biju Das
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[PATCH 5.10.y-cip 05/10] dt-bindings: pinctrl: renesas: Document RZ/G2UL pinctrl
commit 74273035c7e486fa046ee7f80fbdb9c19169ef19 upstream. Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is almost identical to RZ/G2L and has lesser pins compared to RZ/G2L. Signed-off
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commit 74273035c7e486fa046ee7f80fbdb9c19169ef19 upstream. Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is almost identical to RZ/G2L and has lesser pins compared to RZ/G2L. Signed-off
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Biju Das
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