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[PATCH 5.10.y-cip 26/33] ravb: Add support for RZ/V2M
From: Phil Edworthy <phil.edworthy@...> commit e1154be73153ab6aafa1546d998987b692ffdc02 upstream. RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though some small parts are the same as R-
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From: Phil Edworthy <phil.edworthy@...> commit e1154be73153ab6aafa1546d998987b692ffdc02 upstream. RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though some small parts are the same as R-
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By
Biju Das
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[PATCH 5.10.y-cip 25/33] ravb: Use separate clock for gPTP
From: Phil Edworthy <phil.edworthy@...> commit 72069a7b2821443f57e5734f91e19936c48e4809 upstream. RZ/V2M has a separate gPTP reference clock that is used when the AVB-DMAC Mode Register (CCC) gPTP Clo
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From: Phil Edworthy <phil.edworthy@...> commit 72069a7b2821443f57e5734f91e19936c48e4809 upstream. RZ/V2M has a separate gPTP reference clock that is used when the AVB-DMAC Mode Register (CCC) gPTP Clo
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By
Biju Das
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[PATCH 5.10.y-cip 24/33] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
From: Phil Edworthy <phil.edworthy@...> commit b0265dcba3d6c1689e6ce315bed09192fb587403 upstream. R-Car has a combined interrupt line, ch22 = Line0_DiA | Line1_A | Line2_A. RZ/V2M has separate interru
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From: Phil Edworthy <phil.edworthy@...> commit b0265dcba3d6c1689e6ce315bed09192fb587403 upstream. R-Car has a combined interrupt line, ch22 = Line0_DiA | Line1_A | Line2_A. RZ/V2M has separate interru
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By
Biju Das
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[PATCH 5.10.y-cip 23/33] ravb: Separate handling of irq enable/disable regs into feature
From: Phil Edworthy <phil.edworthy@...> commit cb99badde146c327f150773921ffe080abe1eb44 upstream. Currently, when the HW has a single interrupt, the driver uses the GIC, TIC, RIC0 registers to enable
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From: Phil Edworthy <phil.edworthy@...> commit cb99badde146c327f150773921ffe080abe1eb44 upstream. Currently, when the HW has a single interrupt, the driver uses the GIC, TIC, RIC0 registers to enable
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By
Biju Das
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[PATCH 5.10.y-cip 22/33] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
From: Phil Edworthy <phil.edworthy@...> commit a7931ac16128bb3af5c4ac482057a711da117856 upstream. Document the Ethernet AVB IP found on RZ/V2M SoC. It includes the Ethernet controller (E-MAC) and Dedi
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From: Phil Edworthy <phil.edworthy@...> commit a7931ac16128bb3af5c4ac482057a711da117856 upstream. Document the Ethernet AVB IP found on RZ/V2M SoC. It includes the Ethernet controller (E-MAC) and Dedi
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By
Biju Das
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[PATCH 5.10.y-cip 21/33] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK
From: Phil Edworthy <phil.edworthy@...> commit ad1bd2bf658062c6edc5ff1ee1725565a4fc8930 upstream. Add basic support for RZ/V2M EVK (based on R9A09G011): - memory - External input clock - UART Signed-o
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From: Phil Edworthy <phil.edworthy@...> commit ad1bd2bf658062c6edc5ff1ee1725565a4fc8930 upstream. Add basic support for RZ/V2M EVK (based on R9A09G011): - memory - External input clock - UART Signed-o
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Biju Das
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[PATCH 5.10.y-cip 20/33] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC
From: Phil Edworthy <phil.edworthy@...> commit fb1929b98f2e1c012b4df596b7b2c9f6f28fbe54 upstream. Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-micropro
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From: Phil Edworthy <phil.edworthy@...> commit fb1929b98f2e1c012b4df596b7b2c9f6f28fbe54 upstream. Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-micropro
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Biju Das
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[PATCH 5.10.y-cip 19/33] clk: renesas: r9a09g011: Add eth clock and reset entries
From: Phil Edworthy <phil.edworthy@...> commit 23426d1be3c20907b4f3d72bf95234d4ee254393 upstream. Add ethernet clock/reset entries to CPG driver. Note that the AXI and CHI clocks are both enabled and
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From: Phil Edworthy <phil.edworthy@...> commit 23426d1be3c20907b4f3d72bf95234d4ee254393 upstream. Add ethernet clock/reset entries to CPG driver. Note that the AXI and CHI clocks are both enabled and
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Biju Das
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[PATCH 5.10.y-cip 18/33] clk: renesas: Add RZ/V2M support using the rzg2l driver
From: Phil Edworthy <phil.edworthy@...> commit 1dd65bb08604ad2906d839c243e1bede2b0efe53 upstream. The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have any CLK_MON registers. Signed
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From: Phil Edworthy <phil.edworthy@...> commit 1dd65bb08604ad2906d839c243e1bede2b0efe53 upstream. The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have any CLK_MON registers. Signed
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Biju Das
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[PATCH 5.10.y-cip 17/33] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
From: Phil Edworthy <phil.edworthy@...> commit 8090bea32484d45b19b57577dee4519cbc28571c upstream. The RZ/V2M doesn't have a matching set of reset monitor regs for each reset reg like the RZ/G2L. Inste
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From: Phil Edworthy <phil.edworthy@...> commit 8090bea32484d45b19b57577dee4519cbc28571c upstream. The RZ/V2M doesn't have a matching set of reset monitor regs for each reset reg like the RZ/G2L. Inste
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Biju Das
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[PATCH 5.10.y-cip 16/33] clk: renesas: rzg2l: Make use of CLK_MON registers optional
From: Phil Edworthy <phil.edworthy@...> commit 63804400f2a5ababe596b4ec908321d6b54f45aa upstream. The RZ/V2M SoC doesn't use CLK_MON registers, so make them optional. Signed-off-by: Phil Edworthy <phi
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From: Phil Edworthy <phil.edworthy@...> commit 63804400f2a5ababe596b4ec908321d6b54f45aa upstream. The RZ/V2M SoC doesn't use CLK_MON registers, so make them optional. Signed-off-by: Phil Edworthy <phi
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Biju Das
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[PATCH 5.10.y-cip 15/33] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
From: Phil Edworthy <phil.edworthy@...> commit 75b0ad42ccd9a87873e91598116471d9991b09ea upstream. All of the muxes and dividers that can be modified require the HIWORD flags, so make the macros set th
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From: Phil Edworthy <phil.edworthy@...> commit 75b0ad42ccd9a87873e91598116471d9991b09ea upstream. All of the muxes and dividers that can be modified require the HIWORD flags, so make the macros set th
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Biju Das
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[PATCH 5.10.y-cip 14/33] clk: renesas: rzg2l: Add read only versions of the clk macros
From: Phil Edworthy <phil.edworthy@...> commit 8282fe0029e0db02fc21500790bfb621572fd28c upstream. This just makes the clk tables easier to read. Signed-off-by: Phil Edworthy <phil.edworthy@...> Link:
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From: Phil Edworthy <phil.edworthy@...> commit 8282fe0029e0db02fc21500790bfb621572fd28c upstream. This just makes the clk tables easier to read. Signed-off-by: Phil Edworthy <phil.edworthy@...> Link:
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Biju Das
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[PATCH 5.10.y-cip 13/33] clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
From: Phil Edworthy <phil.edworthy@...> commit ceb3bfab2da49f804ec629a20f731611b9ece207 upstream. We only ever use ARRAY_SIZE() to populate the number of parents, so move this into the macro to always
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From: Phil Edworthy <phil.edworthy@...> commit ceb3bfab2da49f804ec629a20f731611b9ece207 upstream. We only ever use ARRAY_SIZE() to populate the number of parents, so move this into the macro to always
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Biju Das
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[PATCH 5.10.y-cip 12/33] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
From: Phil Edworthy <phil.edworthy@...> commit 4a526957e6368597dea08175a67f0e15569f3958 upstream. Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC. Signed-off-by: Phil Edworthy
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From: Phil Edworthy <phil.edworthy@...> commit 4a526957e6368597dea08175a67f0e15569f3958 upstream. Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC. Signed-off-by: Phil Edworthy
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Biju Das
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[PATCH 5.10.y-cip 11/33] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions
From: Phil Edworthy <phil.edworthy@...> commit 96055bf71ab1629cdedff15bcbc04609cfa1f198 upstream. Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs (CPG_CLK_ON* registers), and rese
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From: Phil Edworthy <phil.edworthy@...> commit 96055bf71ab1629cdedff15bcbc04609cfa1f198 upstream. Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs (CPG_CLK_ON* registers), and rese
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Biju Das
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[PATCH 5.10.y-cip 10/33] arm64: defconfig: Enable Renesas RZ/V2M SoC
From: Phil Edworthy <phil.edworthy@...> commit 0b8842db35518714942fe23c13f92778d58eb085 upstream. Enable the Renesas RZ/V2M SoC and the uart it uses. Signed-off-by: Phil Edworthy <phil.edworthy@...> R
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From: Phil Edworthy <phil.edworthy@...> commit 0b8842db35518714942fe23c13f92778d58eb085 upstream. Enable the Renesas RZ/V2M SoC and the uart it uses. Signed-off-by: Phil Edworthy <phil.edworthy@...> R
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Biju Das
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[PATCH 5.10.y-cip 09/33] soc: renesas: Add RZ/V2M (R9A09G011) config option
From: Phil Edworthy <phil.edworthy@...> commit 068eb5a9105bc43a60bdb20484840e5de945fe1d upstream. Add a configuration option for the RZ/V2M SoC. Signed-off-by: Phil Edworthy <phil.edworthy@...> Link:
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From: Phil Edworthy <phil.edworthy@...> commit 068eb5a9105bc43a60bdb20484840e5de945fe1d upstream. Add a configuration option for the RZ/V2M SoC. Signed-off-by: Phil Edworthy <phil.edworthy@...> Link:
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Biju Das
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[PATCH 5.10.y-cip 08/33] soc: renesas: Identify RZ/V2M SoC
From: Phil Edworthy <phil.edworthy@...> commit 7e20044052317d5f2942b061c4cacdb6790790a2 upstream. Add support for identifying the RZ/V2M (R9A09G011) SoC. Note that the SoC does not have a identificati
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From: Phil Edworthy <phil.edworthy@...> commit 7e20044052317d5f2942b061c4cacdb6790790a2 upstream. Add support for identifying the RZ/V2M (R9A09G011) SoC. Note that the SoC does not have a identificati
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Biju Das
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[PATCH 5.10.y-cip 07/33] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
From: Phil Edworthy <phil.edworthy@...> commit a884f187760ee0c6033296aa50845e2d1e0e8430 upstream. Add DT binding documentation for System Configuration (SYS) found on RZ/V2M SoC's. SYS block contains
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From: Phil Edworthy <phil.edworthy@...> commit a884f187760ee0c6033296aa50845e2d1e0e8430 upstream. Add DT binding documentation for System Configuration (SYS) found on RZ/V2M SoC's. SYS block contains
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Biju Das
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